Tomishima
Atsushi Tomishima, Chiba JP
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20110180898 | SEMICONDUCTOR DEVICE - According to the embodiments, a core block is formed on a semiconductor chip, and is constructed of an integrated circuit that can operate independently. A power-supply switch is formed on the semiconductor chip, and connects or disconnects the core block to or from a power line. A capacitor is formed on the semiconductor chip, and is connected to the power line in parallel to the core block. A selection switch is formed on the semiconductor chip, and connects or disconnects the capacitor to or from the power line. | 07-28-2011 |
Daisuke Tomishima, Ishikawa JP
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20110274050 | WIRELESS COMMUNICATION BASE STATION APPARATUS, WIRELESS COMMUNICATION TERMINAL DEVICE AND WIRELESS COMMUNICATION METHOD - A wireless communication base station apparatus which reduces the power consumed by UE in communication using VoIP when in a silent state; and a wireless communication terminal device and wireless communication method of the same. A residual amount control unit ( | 11-10-2011 |
Kazuki Tomishima, Saitama JP
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20100155382 | Method for Machining Valve Mechanism Component Member - A surface machining method to be adopted when machining a valve mechanism component member is provided so as to manufacture a product assuring a specific pulsation-reducing effect over an extended period of time with a high level of reliability. A plurality of recesses | 06-24-2010 |
Ryoichi Tomishima, Urayasu-City JP
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20080245762 | SQUARE BOTTLE MANUFACTURED FROM SYNTHETIC RESIN - Disclosed herein are bottle-shaped containers having a trunk portion approximating a square. The trunk portion comprises four tabular side walls arrayed about a center axis and four corner walls connected to adjacent side walls in a corner-cutting form. The width of the corner walls expands from the top end and the bottom end toward a position about midway between the top end and the bottom end. By making the widths of the side walls and the corner walls about equal at a location about midway between the top portion and the bottom portion, the distance between the corner walls in mutual opposition with respect to the center axis can be decreased, forming a waist portion. | 10-09-2008 |
Shigeki Tomishima, Boise, ID US
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20080225627 | APPARATUS FOR MEMORY DEVICE WORDLINE - A method and apparatus for improving the speed of a wordline in a memory device. A wordline structure includes a main wordline for selectively distributing a main wordline signal and a plurality of wordlines selectively coupled to the main wordline. Each of the wordlines is selectively coupled to a lower resistivity shared interconnection line by way of a selected one of a plurality of switching elements each commonly coupled on one end to the shared interconnection line and individually coupled on an opposing end to the plurality of wordlines. Each of the plurality of switching elements is selectively activated to couple one of the plurality of wordlines to the shared interconnection line when the main wordline signal is selectively coupled to one of the plurality of wordlines. | 09-18-2008 |
20090073791 | LOW VOLTAGE DATA PATH AND CURRENT SENSE AMPLIFIER - Methods, circuits, devices, and systems are provided, including a low voltage data path and current sense amplifier. One data path includes a local input/output (LIO) line and a global input/output (GIO) line each having first and second signal lines. A source follower circuit, coupled between the LIO line and the GIO line, includes first and second n-channel MOS (NMOS) transistors having a drain coupled to the first and the second signal lines of the GIO and a gate coupled to the first and the second signal lines of the LIO. A third NMOS transistor has a source coupled to the source of the first and the second NMOS transistors, a gate coupled to a reference voltage supply and a drain coupled to a drain of a fourth NMOS transistor. The fourth NMOS has a gate to which a selection signal is applied and a source coupled to a ground. | 03-19-2009 |
20110103125 | MEMORY CELLS HAVING A FOLDED DIGIT LINE ARCHITECTURE - Memory arrays having folded architectures and methods of making the same. Specifically, memory arrays having a portion of the transistors in a row that are reciprocated and shifted with respect to other transistors in the same row. Trenches formed between the rows may form a weave pattern throughout the array, in a direction of the row. Trenches formed between legs of the transistors may also form a weave pattern throughout the array in a direction of the row. | 05-05-2011 |
20110317509 | MEMORY DEVICE WORD LINE DRIVERS AND METHODS - Memory subsystems and methods, such as those involving a memory cell array formed over a semiconductor material of a first type, such as p-type substrate. In at least one such subsystem, all of the transistors used to selectively access cells within the array are transistors of a second type, such as n-type transistors. Local word line drivers are coupled to respective word lines extending through the array. Each local word line drivers includes at least one transistor. However, all of the transistors in the local word line drivers are of the second type. A well of semiconductor material of the second type, is also formed in the material of the first type, and a plurality of global word line drivers are formed using the well. Each global word line driver includes at least one transistor of the first type. Other subsystems and methods are disclosed. | 12-29-2011 |
20120117336 | CIRCUITS AND METHODS FOR PROVIDING DATA TO AND FROM ARRAYS OF MEMORY CELLS - A memory device uses a global input/output line or a pair of complementary global input/output lines to couple write data signals and read data signals to and from a memory array. The same input/output line or pairs of complementary global input/output lines may be used for coupling both write data signals and read data signals. | 05-10-2012 |
20150039843 | CIRCUITS AND METHODS FOR PROVIDING DATA TO AND FROM ARRAYS OF MEMORY CELLS - A memory device uses a global input/output line or a pair of complementary global input/output lines to couple write data signals and read data signals to and from a memory array. The same input/output line or pairs of complementary global input/output lines may be used for coupling both write data signals and read data signals. | 02-05-2015 |
Shigeki Tomishima, Tsukuba JP
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20090003038 | Capacitor supported precharching of memory digit lines - Circuits and methods are provided for precharging pairs of memory digit lines. The final precharge voltage of the digit lines is different from the average of the digit line voltages prior to precharging. The final precharge voltage can be set by appropriately selecting the size of a capacitor in the precharge circuit. | 01-01-2009 |
Shigeki Tomishima, Portland, OR US
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20120063256 | MEMORY DEVICE WORD LINE DRIVERS AND METHODS - Memory subsystems and methods, such as those involving a memory cell array formed over a semiconductor material of a first type, such as p-type substrate. In at least one such subsystem, all of the transistors used to selectively access cells within the array are transistors of a second type, such as n-type transistors. Local word line drivers are coupled to respective word lines extending through the array. Each local word line drivers includes at least one transistor. However, all of the transistors in the local word line drivers are of the second type. A well of semiconductor material of the second type, is also formed in the material of the first type, and a plurality of global word line drivers are formed using the well. Other subsystems and methods are disclosed. | 03-15-2012 |
20150014758 | MEMORY CELLS HAVING A FOLDED DIGIT LINE ARCHITECTURE - Memory arrays having folded architectures and methods of making the same. Specifically, memory arrays having a portion of the transistors in a row that are reciprocated and shifted with respect to other transistors in the same row. Trenches formed between the rows may form a weave pattern throughout the array, in a direction of the row. Trenches formed between legs of the transistors may also form a weave pattern throughout the array in a direction of the row. | 01-15-2015 |
Yasumitsu Tomishima, Tokyo JP
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20080312435 | Imine Compound - An imine compound represented by the formula: | 12-18-2008 |
Yuichiro Tomishima, Yokohama JP
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20130149014 | IMAGE FORMING APPARATUS AND COLOR REGISTRATION METHOD OF THE SAME - An image forming apparatus which obtains rotational variance factors of an intermediate transfer belt for each of plurality of colors based on locations with respect to second pattern image being obtained by a location calculation unit, corrects the location obtained with respect to a first pattern image based on the rotational variance factor obtained with respect to the color of the first pattern image, obtains an offset of another color with respect to a reference color based on the location after correction, and performs color registration based on the obtained offset to reduce the offset. | 06-13-2013 |