Toia
Alexander Toia, Vancouver, WA US
Patent application number | Description | Published |
---|---|---|
20140210895 | PRINTING SYSTEM WITH FORCE CONTROL MODE - A printing system includes a printhead to eject ink onto a print medium in a print zone. A first roller pair is adjacent to the print zone to advance a print medium into the print zone. A second roller pair upstream from the first roller pair, and driven by an independent motor, advances the print medium to the first roller pair in a position control mode. A controller causes the second roller pair to switch from the position control mode to a force control mode when a leading edge of the print medium reaches the first roller pair. The second roller pair applies a substantially constant force to the print medium in the force control mode to push the leading edge of the print medium against the first roller pair while the first roller pair is stationary. | 07-31-2014 |
20140210899 | CALIBRATION OF A RETRO-REFLECTIVE SENSOR - A printer system includes a handling system to move print media, a print medium detection sensor to produce a response indicative of an object, and a processor coupled to the handling system and to the print medium detection sensor to perform a two-point calibration of the sensor. The first point of the two-point calibration includes a first response from the sensor, and a second point of the two-point calibration includes a second response from the sensor. | 07-31-2014 |
20150266314 | MEDIA JAM CLEARING - A method for media jam clearing includes detecting a media jam with sensor in the printer, in which the media jam comprises a sheet of media stuck in a media path of the printer. The method further includes monitoring for user action that alters the mechanically alters the state of the printer and detecting a user action that mechanically alters the state of the printer. In response to detection of the user action, the printer automatically attempts to clear the media jam. | 09-24-2015 |
Fabrizio Toia, Busto Arsizio (va) IT
Patent application number | Description | Published |
---|---|---|
20150364249 | INTEGRATED TRANSFORMER - An integrated transformer includes a primary winding and a secondary winding each having a spiral planar arrangement coils. A dielectric portion of dielectric material is interposed between the primary winding and the secondary winding. A field plate winding is electrically coupled with the primary winding. The field plate winding includes at least one field plate coil having a first lateral extension greater than a second lateral extension of a primary outer coil of the primary winding. The field plate coil is superimposed in plan view to the primary outer coil of the primary winding. | 12-17-2015 |
Fabrizio Fausto Renzo Toia, Busto Arsizio(va) IT
Patent application number | Description | Published |
---|---|---|
20110175191 | ISOLATION TRENCHES FOR SEMICONDUCTOR LAYERS - A method is for the formation of at least one isolation trench filled with thermal oxide in a semiconductor layer and a semiconductor device include at least one isolation trench filled with thermal oxide. The method allows obtaining in an easy way, isolation trenches exhibiting excellent functional morphological properties. The method is based on the idea of exploiting the properties of the thermal oxidation mechanism of a semiconductor material in order to obtain at least an isolation trench filled with thermal oxide. | 07-21-2011 |
Fabrizio Fausto Renzo Toia, Busto Arsizio (va) IT
Patent application number | Description | Published |
---|---|---|
20110241158 | ISOLATION TRENCHES - A method is for the formation of at least one filled isolation trench having a protective cap in a semiconductor layer, and a semiconductor device with at least one filled isolation trench having a protective cap. The method allows obtaining, in an easy way, filled isolation trenches exhibiting excellent functional and morphological properties. The method therefore allows the obtainment of effective filled isolation trenches which help provide elevated, reliable and stable isolation properties. | 10-06-2011 |
20120098142 | ELECTRICAL CONTACT FOR A DEEP BURIED LAYER IN A SEMI-CONDUCTOR DEVICE - A semi-conductor device includes at least one deep buried layer with an electrical connection made thereto by an electrical contact. The electrical contact to the deep buried layer is made by formed an opening through the use of a first chemical attack and a second chemical attack after the first chemical attack. By making an opening, the electrical contact can be made with the deep buried layer without at the same time occupying excessively wide portions of the device. For example, it is possible to make electrical contacts having a width of less than 1.5 μm with deep layers having a depth of more than 5 μm. | 04-26-2012 |
Fabrizio Fausto Renzo Toia, Busto Arsizio IT
Patent application number | Description | Published |
---|---|---|
20140008722 | VERTICAL-GATE MOS TRANSISTOR WITH FIELD-PLATE ACCESS - An embodiment of a vertical-gate transistor disposed on a die includes a first substrate portion of a first conductivity and a second substrate portion of a second conductivity. The die includes front and rear surfaces, the first portion extending from the front surface and the second portion extending from the rear surface to the first portion, at least one drain region of the second conductivity extending from the rear surface, and at least one cell. Each cell includes a source region of the second conductivity extending from the front surface, a conductive gate region extending from the front surface to a gate depth, a conductive field-plate region extending from the front surface to a field depth, a gate-insulating layer that insulates the gate region, and a plate-insulating layer that insulates the field-plate region. An intermediate insulating layer insulates the gate region from the field-plate region. | 01-09-2014 |