Toh, Singapore
Ah Cheong Toh, Singapore SG
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20090217855 | PONTOON-TYPE FLOATING STRUCTURE - A pontoon-type floating structure comprising an upper deck that is to be maintained above water level and that is to receive and support a load by the load resting thereon; and a horizontal array of chambers disposed underneath the upper deck, with the chambers providing a first set of chambers that provide the structure with buoyancy, and a second set of chambers with water having access thereto so that the second set of chambers, under steady state conditions, do not provide buoyancy. | 09-03-2009 |
Beng Leong Toh, Singapore SG
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20130289456 | GARMENT BASED AIRWAY CLEARANCE SYSTEMS AND METHODS - A garment based airway clearance system for mobilizing secretions in a patient's airway and related methods are disclosed. The garment based airway clearance system comprises a therapy chamber mounted substantially around the circumference of the garment such that inflation of the therapy chamber causing a compressive force to be applied on the thorax or chest of the wearer of the garment. | 10-31-2013 |
20140163440 | PULSE GENERATOR SYSTEMS FOR THERAPY DEVICE - A system for providing continuous high frequency oscillation therapy is disclosed. A pulse generator comprises a valve stem which fluidly connects two ports when pressure in one of the two ports exceeds a threshold force. Fluidic connection between the two ports allows for fluid to flow back through an orifice and a needle valve to the pulse generator, the orifice and needle valve are components external to the pulse generator. Gases flowing through the needle valve and to the pulse generator apply a force on a diaphragm which deforms and pushes a valve button when gases flowing through the needle valve exceed a threshold. Motion of the valve button due to deformation of the diaphragm causes the valve button to exert force on the valve stem reducing fluid flow between the two ports. Reduction in fluid flow between the two ports causes drop in pressure of the gas flowing through the needle valve back into the pulse generator thereby reducing the force seeking to deform the first diaphragmnd move the valve button. The valve button falls back thereby allowing increased fluidic communication between the two ports again. This cyclical supply of high pressure gas is used for therapeutic purposes to provide high frequency oscillation. | 06-12-2014 |
Boon Keat Toh, Singapore SG
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20090257574 | INTERFACE FOR VOICE COMMUNICATIONS - There is provided an interface viewable on a display for a communications apparatus used during a session for voice communications between at least two parties. The interface includes at least one edge of the display having a row of objects, each object of the row being for representing each of the at least two parties; and a main portion of the display being for showing the object of the party speaking at a particular point in time, with a plurality of the objects being shown when a plurality of the parties are speaking at the particular point in time. Advantageously, the object of the speaking party is shown on the main portion when the speaking party's voice is detected by the speaking party's communications apparatus, a host server receiving information from the speaking party's communications apparatus to aid in displaying the object of the speaking party at the particular point in time. Alternatively, the object of the speaking party may also undergo a change of state, such as, for example, a blinking effect, a single occurrence resizing effect, a transitional blurring effect, a repeated resizing effect, and any combination of the aforementioned. | 10-15-2009 |
Boon Keat Eddy Toh, Singapore SG
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20110041368 | Method and Apparatus for Marketing an Object - There is provided a method and an apparatus for marketing an object. The apparatus includes a display with a first mode and a second mode; and a housing for containing the object adjacent to the display. The display may preferably be coupled to a controller circuit for activating transition of the display between the first mode and the second mode, with the object being viewable through the display in the second mode. The method includes carrying out activities to create an association between the apparatus and the object; using the apparatus for containment of items; and causing an increase in awareness in the object through use of the apparatus. | 02-24-2011 |
20110055724 | INTERFACE FOR VOICE COMMUNICATIONS - There is provided an interface viewable on a display for a communications apparatus used during a session for voice communications between at least two parties. The interface includes at least one edge of the display having a row of objects, each object of the row being for representing each of the at least two parties; and a main portion of the display being for showing the object of the party speaking at a particular point in time, with a plurality of the objects being shown when a plurality of the parties are speaking at the particular point in time. Advantageously, the object of the speaking party is shown on the main portion when the speaking party's voice is detected by the speaking party's communications apparatus, a host server receiving information from the speaking party's communications apparatus to aid in displaying the object of the speaking party at the particular point in time. Alternatively, the object of the speaking party may also undergo a change of state, such as, for example, a blinking effect, a single occurrence resizing effect, a transitional blurring effect, a repeated resizing effect, and any combination of the aforementioned. | 03-03-2011 |
20110218658 | SYSTEM FOR REPRODUCTION OF MEDIA CONTENT - There is provided a system for reproduction of media content. The system includes at least one sound reproduction apparatus being wirelessly connectable to at least one control apparatus via at least one data channel, the at least one control apparatus being connected to the at least one sound reproduction apparatus once the at least one control apparatus receives a first signal indicating a presence of the at least one sound reproduction apparatus; and the at least one control apparatus being wirelessly connectable to at least one data storage apparatus on a data network. Preferably, the at least one sound reproduction apparatus plays back audio signals of the media content which is either stored on the at least one control apparatus or received via the data network, and with the audio signals of the media content being received at a memory module of the at least one sound reproduction apparatus. The audio signals may be played back either in a streaming form or a stored-data playback form, the form depending on the audio signals stored in the memory module. | 09-08-2011 |
20110246886 | APPARATUS AND METHOD FOR CONTROLLING A SOUND REPRODUCTION APPARATUS - There is provided a control apparatus and method for controlling a sound reproduction apparatus. The control apparatus and method enables control of at least one parameter of audio reproduction depending on contact with a touch sensitive panel. The parameters which may be controlled include, for example, volume, bass, treble, equalizer settings and the like. The functions of the sound reproduction apparatus which may be controlled include, for example, radio channel selection, track selection, album selection and the like. | 10-06-2011 |
20120121111 | SOUND REPRODUCTION APPARATUS AND A METHOD FOR SPEAKER CHARGING/CALIBRATION EMPLOYED IN SAID APPARATUS - There is provided a sound reproduction apparatus including a sub-woofer unit and a plurality of wireless speakers. A method of speaker charging and speaker calibration using the sound reproduction apparatus is also provided. The sub-woofer unit may be configured to perform tasks of both charging a power source in each of the plurality of wireless speakers; and calibrating speaker identity for each of the plurality of wireless speakers. It is advantageous that both of the tasks are performed when the plurality of wireless speakers is coupled to the sub-woofer unit. The speaker identity may include, for example, left front, right front, left rear, right rear, and centre. | 05-17-2012 |
Chee Hock Toh, Singapore SG
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20080304674 | Hearing device test adapter - A hearing device test adapter is provided in order to connect a hearing device output to a test microphone in a soundproof manner. The hearing device test adapter has an expandable first section for enclosing one section of a hearing device shell or an earmold piece in a soundproof manner such that the sound output of the hearing device shell or of the earmold piece points to the tip of the first section. In addition, the hearing device test adapter has an expandable second section for enclosing a section of the test microphone in a soundproof manner, with the tip of the first section directly connecting to the second section and both being connected to one another via a sound transmission. | 12-11-2008 |
Chee Hwee Toh, Singapore SG
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20100058966 | DIVERSION OF SAILING VESSEL BY TETHERING METHOD AND APPARATUS THEREFOR WITH HARPOON MEANS - A method for diverting a sailing vessel is disclosed. A watercraft equipped with a harpoon having a hull-piercing head and a tail attached to a cable may swiftly approach the vessel in the aft position. Upon piercing the hull, an extraction-preventing means, such as spokes unfolded from the head, latching it in the hull and preventing the harpoon's withdrawal. Via a cable attached to the tail of the harpoon the watercraft may use low-speed high-traction propulsion means such as Voith-Schneider Propulsion (VSP) to pull and divert the vessel at the stern to a desired course. The watercraft may preferably have a combination of lifting hydrofoils with propellers and VSP propellers to provide the respective low-traction high-speed and high-traction low-speed modes of operation. | 03-11-2010 |
20120320206 | SYSTEM AND METHOD FOR TRACKING A LEAD OBJECT - An imaging system for tracking the location and direction of movement of a first object comprises a plurality of marker devices adapted to be disposed in a pattern on the first object, a sensing device, and a processor. The sensing device is adapted to be disposed on a second object so as to view the marker devices, the sensing device being operative to detect the relative positions of the plurality of marker devices on the first object, and the processor is coupled to the sensing device to form an image of the relative positions of the plurality of marker devices and to determine the direction of movement of the first object. | 12-20-2012 |
Cheeseng Toh, Singapore SG
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20090313426 | Buffer Management for Increased Write Speed in Large Sector Data Storage Device - An intelligent write command routine improves the operational efficiency of a data storage device (DSD) by avoiding media access of the disk when a logical block address (LBA) and the physical sector are unaligned, thus reducing write time. When a write command is received by the DSD from the host, the intelligent write command routine maintains the read data of the read buffer, instead of clearing the read buffer and performing a read of the target sector on the disk per standard protocol. The intelligent write command copies the necessary adjacent sector data from the read buffer as a data patch to the write buffer to splice around the write data received with the write command. Following each write command, the data written to the disk in the write buffer is copied to the read buffer. The read buffer is maintained with the most current data on the disk and does not need to be flushed unless the LBA of the write command is beyond the data ranges stored in the read buffer. | 12-17-2009 |
20120272038 | LOGICAL BLOCK ADDRESS MAPPING - A mapping table is modified to match one or more specified storage conditions of data stored in or expected to be stored in one or more logical block address ranges to physical addresses within a storage drive having performance characteristics that satisfy the specified storage conditions. For example, the performance characteristics may be a reliability of the physical location within the storage drive or a data throughput range of read/write operations. Existing data is moved and/or new data is written to physical addresses on the storage media possessing the performance characteristic(s), according to the mapping table. Further, a standard seeding or a seeding override for the re-mapped logical block addresses can prevent read operations from inadvertently reading incorrect physical addresses corresponding to the re-mapped logical block addresses. | 10-25-2012 |
Chee Seng Toh, Singapore SG
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20100059363 | SURFACE TREATMENT OF ALUMINA FILMS - A method of treating an alumina film comprising the step of exposing said alumina film to a carboxylic acid solution under conditions to reduce the hydropilic properties of the surface of said film. | 03-11-2010 |
Chee Tat Toh, Singapore SG
Patent application number | Description | Published |
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20110170330 | Graphene Memory Cell and Fabrication Methods Thereof - The disclosed memory cell ( | 07-14-2011 |
20140233297 | Graphene Ferroelectric Device and Opto-Electronic Control of Graphene Ferroelectric Memory Device - In accordance with an embodiment of the invention, there is provided a graphene ferroelectric device. The device comprises a graphene transistor channel and a ferroelectric gate of the graphene transistor channel, the ferroelectric gate comprising a linear polarization at a first applied gate voltage less than a threshold voltage, and a hysteretic polarization at a second applied gate voltage greater than the threshold voltage. The device may be configured to undergo optical switching of the graphene transistor channel between a high resistance state and a low resistance state in response to photoillumination of the device. | 08-21-2014 |
20150075602 | PHOTOVOLTAIC CELL WITH GRAPHENE-FERROELECTRIC ELECTRODE - A photovoltaic cell ( | 03-19-2015 |
Cher Lek Toh, Singapore SG
Patent application number | Description | Published |
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20090090878 | System and Method for Determining Volume of an Imaging Medium in a Cartridge - Systems and methods for determining the volume of imaging medium in a cartridge are disclosed. An imaging medium may include a movable housing portion and a device coupled to the movable housing portion. The movable housing portion may include a volume of imaging medium and may be configured to move in response to changes in the volume of imaging medium in the movable housing portion. The device may be configured to project a beam of electromagnetic energy onto a location of a beam-receiving photodetector, the beam-receiving location moving in response to movement of the movable housing portion such that the beam-receiving location is based at least on the volume of imaging medium on the movable housing portion. | 04-09-2009 |
20090279904 | Enhancing Mono Printing Speed on a Single Pass Color Laser Printer - A mono optimized color laser printer. The mono optimized color laser printer includes a provision in which mono toner cartridges may be inserted at each of four toner locations. The mono optimized color laser printer includes a mono optimization module which detects when mono toner cartridges are inserted into the four toner locations and controls printing so that each of the mono toner cartridges prints on about a quarter of a page. Such a mono optimized color laser printer reduces a time taken to transfer toner to the page to about a quarter that of a traditional color printer. Such a printer results in about a four times increase in printing speed for a mono print operation. | 11-12-2009 |
20120248688 | DEPINCHING MECHANISM FOR PAPER JAM REMOVAL IN PRINTER - A depinching mechanism including a frame, a star wheel assembly, a limiter arm, a rocker arm and a sensor is provided in present invention. Through the depinching mechanism the star wheel assembly is lifted from the first position to the second position when paper jam occurs, and thus depinched the media the user can clear the paper jam. And after that the star wheel assembly is lowered from the second position to the first position. The star wheel assembly remains in the first position in the normal printing process. Since when paper jam occurs the star wheel assembly is lifted by the depinching mechanism, the user can easily and conveniently remove the jammed paper. And thus, the depinching mechanism can facilitate the user to remove jammed paper when paper jam occurs in printer. Thus, the depinching mechanism can be used in printers to solve the paper jamming problems. | 10-04-2012 |
20120248690 | DEPINCHING MECHANISM FOR PAPER JAM REMOVAL IN PRINTER - A depinching mechanism including a frame, a star wheel assembly, a transmitting device and a sensor is provided in present invention. Through the transmitting device rotating reversely, the star wheel assembly is lifted to the second position when paper jam occurs, thus depinched the media so that user can clear the paper jam. After that the star wheel assembly is lowered to the first position again. The star wheel assembly remains in the first position in normal printing process. Using a one-way clutch and a cam with an outer predetermined profile, the transmitting device rotates forwardly without transmitting any torque during normal printing process, and rotates inversely with transmitting a torque to lift the star wheel assembly up and lower the star wheel assembly down when paper jam occurs. Thus, the depinching mechanism can be used in printers to auto fix the paper jamming problems. | 10-04-2012 |
20130126289 | GEAR CLUTCH ASSEMBLY AND ELECTRONIC DEVICE USING THE SAME - A gear clutch assembly and an electronic device are provided. The gear clutch assembly comprises a pivot, a driving gear engaged with the pivot and adapted to rotate along the pivot, and a driven gear disposed on the driving gear. The driving gear comprises a first surface, a ratchet integrally formed with the driving gear comprising a plurality of teeth disposed on the first surface. The driving gear comprises a second surface facing the first surface, and a pawl integrally formed with the driven gear on the second surface. When the driving gear rotates in a driving direction, one of the teeth is engaged with the pawl and drives the driven gear to rotates with the driving gear. When the driving gear rotates in an opposite direction, every tooth pushes up and slides under the pawl so the driven gear does not rotate along with the driving gear. | 05-23-2013 |
20130336696 | AUTOMATIC DOCUMENT FEEDER AND MEDIA RECORD EQUIPMENT USING THE SAME - An automatic document feeder and a media record equipment using the same are provided. The automatic document feeder includes a frame, a cover and a gear chain. An end of the cover pivoted to the frame has a cam. The gear chain disposed in the frame has multiple driven gears and a rotating unit. The driven gears engaged with each other rotate about a first axial direction. The rotating unit having a first rock arm contacting the cam and a second rock arm with one of the driven gears disposed thereon is capable of rotating about the first axial direction. The cam pushes the first rock arm to drive the rotating unit to rotate about the first axial direction, and then an engagement between the driven gear on the second rock arm is released by departing from another driven gear engaged therewith when the cover opens relative to the frame. | 12-19-2013 |
20140374949 | THREE-DIMENSIONAL PRINTING APPARATUS AND PRINGING METHOD THEREOF - A three-dimensional printing apparatus suitable for fabricating a three-dimensional object from a model of the three-dimensional object is provided. The three-dimensional printing apparatus includes a rotary base and a printing head. The rotary base has a carrying surface and is configured to rotate about a first axis and shift along the first axis. The printing head is disposed above the rotary base and configured to shift along a second axis perpendicular to the first axis for dispensing successive layers of building material onto the carrying surface. The successive layers of building material form the three-dimensional object. The shape of each layer of the building material is decided by the rotation of the rotary base about the first axis, the shifting of the rotary base along the first axis and the shifting of the printing head along the second axis. A printing method for the three-dimensional printing apparatus is also provided. | 12-25-2014 |
20150328837 | PRINTING HEAD MODULE - A printing head module includes a driving gear, a bi-directional motor, a first feeding module and a second feeding module. The bi-directional motor selectively drives the driving gear to rotate along a first direction and a second direction. The first feeding module disposed at a first side of the driving gear includes a first unidirectional gear and a first idler gear. The driving gear is engaged with the first unidirectional gear, and the first unidirectional gear unidirectionally drives the first idler gear to rotate. The second feeding module is disposed at a second side of the driving gear opposite to the first side, and includes a second unidirectional gear and a second idler gear, the driving gear is engaged with the second unidirectional gear to drive the second unidirectional gear to rotate, and the second unidirectional gear unidirectionally drive the second idler gear to rotate. | 11-19-2015 |
Chih Hock Toh, Singapore SG
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20090200662 | SEMICONDUCTOR PACKAGE AND METHOD OF MAKING THE SAME - The present invention relates to semiconductor devices comprising two or more dies stacked vertically on top of one another, and methods of making the semiconductor devices. The methods may comprise a combination of wafer-level through silicon interconnect fabrication and wafer-level assembly processes. | 08-13-2009 |
Chin Hock Toh, Singapore SG
Patent application number | Description | Published |
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20080290505 | MOLD DESIGN AND SEMICONDUCTOR PACKAGE - A chip package includes a carrier having a first and a second major surface. The first major surface includes an active region surrounded by an inactive region. The chip package includes contact pads in the active region for mating with chip contacts of a chip. A support structure is disposed on the inactive region of the first major surface. The support structure forms a dam that surrounds the active region. When a chip or chip stack is mounted in the active region, spacing exists between the dam and the chip or chip stack. The spacing creates convention paths for heat dissipation. | 11-27-2008 |
20080303031 | VENTED DIE AND PACKAGE - A die that includes a substrate having a first and second major surface is disclosed. The die has at least one unfilled through via passing through the major surfaces of the substrate. The unfilled through via serves as a vent to release pressure generated during assembly. | 12-11-2008 |
20080303163 | THROUGH SILICON VIA DIES AND PACKAGES - A method for preparing a die for packaging is disclosed. A die having first and second major surfaces is provided. Vias and a mask layer are formed on the first major surface of the die. The mask includes mask openings that expose the vias. The mask openings are filled with a conductive material. The method includes reflowing to at least partially fill the vias and contact openings to form via contacts in the vias and surface contacts in the mask openings. | 12-11-2008 |
20100013081 | PACKAGING STRUCTURAL MEMBER - A structural member for use in semiconductor packaging is disclosed. The structural member includes a plurality of packaging regions to facilitate packaging dies in, for example, a wafer format. A packaging region has a die attach region surrounded by a peripheral region. A die is attached to the die attach region. In one aspect, the die attach region has opening through the surfaces of the structural member for accommodating a die. Through-vias disposed are in the peripheral regions. The structural member reduces warpage that can occur during curing of the mold compound used in encapsulating the dies. In another aspect, the die attach region does not have an opening. In such cases, the structural member serves as an interposer between the die and a substrate. | 01-21-2010 |
20100109142 | INTERPOSER FOR SEMICONDUCTOR PACKAGE - An interposer is presented. The interposer includes an interposer base having first and second surfaces. A redistribution layer is disposed on a first surface of the interposer base. The interposer has at least one interposer pad coupled to the redistribution layer. It also includes at least one interposer contact on the second surface. The interposer contact is electrically coupled to the interposer pad via the redistribution layer. The interposer also includes at least one interposer via through the interposer base for coupling the interposer contact to the redistribution layer. The interposer via includes reflowed conductive material of the interposer contact. | 05-06-2010 |
20100109169 | SEMICONDUCTOR PACKAGE AND METHOD OF MAKING THE SAME - A stiffener is provided for use in making semiconductor devices. The stiffener and method of use provided prevent or reduce warpage of a semiconductor package during the assembly process. More particularly, the stiffener functions to prevent or reduce warpage during molding of an assembly of wafers and/or dies. The stiffener may be positioned above the backside or non-active side of an assembly of wafer and/or dies during molding. The presence of the stiffener prevents or reduces warpage caused by CTE mismatch between the mold material and the wafer and/or under the high temperatures encountered in the process of molding. After molding, the stiffener may continue to provide support to the assembly. | 05-06-2010 |
20100261313 | SEMICONDUCTOR PACKAGE AND METHOD OF PACKAGING SEMICONDUCTOR DEVICES - A method of forming a device stack is presented. The method includes providing a temporary substrate having a temporary mounting surface. A first chip is temporarily mounted to the temporary mounting surface. A first bottom surface of the first chip is temporarily mounted to the temporary mounting surface and a first top surface of the first chip comprises first interconnects. A second chip is stacked on the first chip. The second chip includes second conductive contacts on the second bottom surface. The method also includes bonding the first and second chips together to form the device stack. The second conductive contacts are coupled to the first interconnects. The first bottom surface of the first chip is separated from the substrate to separate the chip stack from the substrate. | 10-14-2010 |
20120018869 | MOLD DESIGN AND SEMICONDUCTOR PACKAGE - A chip package includes a carrier having a first and a second major surface. The first major surface includes an active region surrounded by an inactive region. The chip package includes contact pads in the active region for mating with chip contacts of a chip. A support structure is disposed on the inactive region of the first major surface. The support structure forms a dam that surrounds the active region. When a chip or chip stack is mounted in the active region, spacing exists between the dam and the chip or chip stack. The spacing creates convention paths for heat dissipation. | 01-26-2012 |
20120104628 | INTERPOSER FOR SEMICONDUCTOR PACKAGE - An interposer is presented. The interposer includes an interposer base having first and second surfaces. A redistribution layer is disposed on a first surface of the interposer base. The interposer has at least one interposer pad coupled to the redistribution layer. It also includes at least one interposer contact on the second surface. The interposer contact is electrically coupled to the interposer pad via the redistribution layer. The interposer also includes at least one interposer via through the interposer base for coupling the interposer contact to the redistribution layer. The interposer via includes reflowed conductive material of the interposer contact. | 05-03-2012 |
20120149150 | VENTED DIE AND PACKAGE - A die that includes a substrate having a first and second major surface is disclosed. The die has at least one unfilled through via passing through the major surfaces of the substrate. The unfilled through via serves as a vent to release pressure generated during assembly. | 06-14-2012 |
20120193812 | SEMICONDUCTOR PACKAGES AND METHODS OF PACKAGING SEMICONDUCTOR DEVICES - A method of forming semiconductor assemblies is disclosed. The method includes providing an interposer with through interposer vias. The interposer includes a first surface and a second surface. The through interposer vias extend from the first surface to the second surface of the interposer. A first die is mounted on the first surface of the interposer. The first die comprises a first surface with first conductive contacts thereon. The interposer comprises material with coefficient of thermal expansion (CTE) similar to that of the first die. The first conductive contacts of the first die are coupled to the through interposer vias on the first surface of the interposer. | 08-02-2012 |
20130119560 | PACKAGING STRUCTURAL MEMBER - A structural member for use in semiconductor packaging is disclosed. The structural member includes a plurality of packaging regions to facilitate packaging dies in, for example, a wafer format. A packaging region has a die attach region surrounded by a peripheral region. A die is attached to the die attach region. In one aspect, the die attach region has opening through the surfaces of the structural member for accommodating a die. Through-vias disposed are in the peripheral regions. The structural member reduces warpage that can occur during curing of the mold compound used in encapsulating the dies. In another aspect, the die attach region does not have an opening. In such cases, the structural member serves as an interposer between the die and a substrate. | 05-16-2013 |
20140045301 | THROUGH SILICON VIA DIES AND PACKAGES - A method for preparing a die for packaging is disclosed. A die having first and second major surfaces is provided. Vias and a mask layer are formed on the first major surface of the die. The mask includes mask openings that expose the vias. The mask openings are filled with a conductive material. The method includes reflowing to at least partially fill the vias and contact openings to form via contacts in the vias and surface contacts in the mask openings. | 02-13-2014 |
20140264954 | PASSIVATION AND WARPAGE CORRECTION BY NITRIDE FILM FOR MOLDED WAFERS - Embodiments of the invention generally relate to molded wafers having reduced warpage, bowing, and outgassing, and methods for forming the same. The molded wafers include a support layer of silicon nitride disposed on a surface thereof to facilitate rigidity and reduced outgassing. The silicon nitride layer may be formed on the molded wafer, for example, by plasma-enhanced chemical vapor deposition or hot-wire chemical vapor deposition. | 09-18-2014 |
20140273354 | FABRICATION OF 3D CHIP STACKS WITHOUT CARRIER PLATES - A method of fabricating a 3D chip stack uses an interposer and an electronic circuit substrate comprising a plurality of electronic circuits. The electrical contacts of the electronic circuit substrate are bonded and electrically coupled to bumps of the interposer. A molding compound is applied over the electronic circuits to form a molded structure. The molded structure is thinned to have a second molded thickness that is less than the first molded thickness, and the interposer is thinned to a second interposer thickness that is less than a first interposer thickness. | 09-18-2014 |
20150137383 | THIN SUBSTRATE AND MOLD COMPOUND HANDLING USING AN ELECTROSTATIC-CHUCKING CARRIER - Thin substrates and mold compound handling is described using an electrostatic-chucking carrier. In one example, a first part of a plurality of silicon chip packages is formed on a front side of a silicon substrate wafer at a first processing station. An a carrier wafer of an electrostatic chuck is attached over the front side of the silicon wafer. The substrate wafer is moved to a second processing station. A second part of the plurality of silicon chip packages are formed on a back side of the silicon wafer at a second processing station. The electrostatic chuck is then released. | 05-21-2015 |
20150140801 | PATTERNED PHOTORESIST TO ATTACH A CARRIER WAFER TO A SILICON DEVICE WAFER - Patterned photoresist is used to attach a carrier wafer to a silicon device wafer. In one example, a silicon wafer is patterned for contact bumps by applying a photoresist over a surface of the wafer and removing the photoresist in locations at which the contact bumps are to be formed. The contact bumps are formed in the locations at which the photoresist is removed. A temporary carrier is attached to the photoresist over the wafer. The back side of the wafer opposite the contact bumps is processed while handling the wafer using the temporary carrier. The temporary carrier is removed. The photoresist on the front side of the wafer with the contact bumps is removed after removing the temporary carrier. | 05-21-2015 |
20160005629 | PACKAGING STRUCTURAL MEMBER - A structural member for use in semiconductor packaging is disclosed. The structural member includes a plurality of packaging regions to facilitate packaging dies in, for example, a wafer format. A packaging region has a die attach region surrounded by a peripheral region. A die is attached to the die attach region. In one aspect, the die attach region has opening through the surfaces of the structural member for accommodating a die. Through-vias disposed are in the peripheral regions. The structural member reduces warpage that can occur during curing of the mold compound used in encapsulating the dies. In another aspect, the die attach region does not have an opening. In such cases, the structural member serves as an interposer between the die and a substrate. | 01-07-2016 |
20160064267 | SEALING STRUCTURE FOR WORKPIECE TO SUBSTRATE BONDING IN A PROCESSING CHAMBER - A sealing structure is between a workpiece or substrate and a carrier for plasma processing. In one example, a substrate carrier has a top surface for holding a substrate, the top surface having a perimeter and a resilient sealing ridge on the perimeter of the top surface to contact the substrate when the substrate is being carried on the carrier. | 03-03-2016 |
Chye Lin Toh, Singapore SG
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20100027233 | MICROELECTRONIC PACKAGES WITH SMALL FOOTPRINTS AND ASSOCIATED METHODS OF MANUFACTURING - Several embodiments of stacked-die microelectronic packages with small footprints and associated methods of manufacturing are disclosed herein. In one embodiment, the package includes a substrate, a first die carried by the substrate, and a second die between the first die and the substrate. The first die has a first footprint, and the second die has a second footprint that is smaller than the first footprint of the first die. The package further includes an adhesive having a first portion adjacent to a second portion. The first portion is between the first die and the second die, and the second portion being between the first die and the substrate. | 02-04-2010 |
Eeyian Toh, Singapore SG
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20130269877 | SEMICONDUCTOR PROCESSING APPARATUS - A semiconductor processing apparatus includes a wafer supporting unit for supporting a wafer and a wafer holder positioned outside of the wafer supporting unit. The wafer holder further includes a plurality of horizontal parts extending axially around the wafer supporting unit and a plurality of vertical parts vertically extending from the horizontal parts respectively. Topmost surfaces of the vertical parts and a topmost surface of the wafer supporting unit are non-coplanar. | 10-17-2013 |
Ee-Yian Toh, Singapore SG
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20120287415 | PICKUP DEVICE AND LITHOGRAPHY APPARATUS USING THE SAME - A pickup device disposed on a base includes a driving unit, a pickup arm, a control unit, a passive arm and a control line. The control unit is disposed on the pickup arm and electrically connects to the pickup arm for controlling that. The passive arm is connected with the pickup arm. The control line is electrically connected between the driving unit and the control unit and embedded in the passive arm. Therefore, the passive arm can protect the control line from damage by suffering external force. Further, the times of being bent to broken of the control line can be reduced to elongate the life thereof. A lithography apparatus using the pickup device is also provided. | 11-15-2012 |
20130038852 | RETICLE REMOVING APPARATUS AND RETICLE REMOVING METHOD USING THE SAME - A reticle removing apparatus adapted to remove a reticle in a reticle library of an exposure apparatus is provided. The reticle removing apparatus includes a bracket and a reticle removing module movably coupled to the bracket, wherein the reticle removing module is configured to be moved into the reticle library in a first direction to remove the reticle in the reticle library. A reticle removing method using the reticle removing apparatus is also provided. | 02-14-2013 |
Eng Huat Toh, Singapore SG
Patent application number | Description | Published |
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20100315884 | Non-volatile memory utilizing impact ionization and tunnelling and method of manufacturing thereof - A non-volatile memory device (and method of manufacture) is disclosed and structured to enable a write operation using an ionization impact process in a first portion of the device and a read operation using a tunneling process in a second portion of the device. The non-volatile memory device (1) increases hot carrier injection efficiency, (2) decreases power consumption, and (3) enables voltage and device scaling in the non-volatile memory devices. | 12-16-2010 |
20110049625 | ASYMMETRICAL TRANSISTOR DEVICE AND METHOD OF FABRICATION - Embodiments of the invention provide an asymmetrical transistor device comprising a semiconductor substrate, a source region, a drain region and a channel region. The channel region is provided between the source and drain regions, the source, drain and channel regions being provided in the substrate. The device has a layer of a buried insulating medium provided below the source region and not below the drain region thereby forming an asymmetrical structure. The layer of buried insulating medium is provided in abutment with a lower surface of the source region. | 03-03-2011 |
20110084319 | Method of fabricating a silicon tunneling field effect transistor (TFET) with high drive current - A method (and semiconductor device) of fabricating a TFET device provides a source region having at least a portion thereof positioned underneath a gate dielectric. In one embodiment, the TFET includes an N+ drain region and a P+ source region in a silicon substrate, where the N+ drain region is silicon and the P+ source region is silicon germanium (SiGe). The source region includes a first region of a first type (e.g., P+ SiGe) and a second region of a second type (undoped SiGe), where at least a portion of the source region is positioned below the gate dielectric. This structure decreases the tunneling barrier width and increases drive current (Id). | 04-14-2011 |
20120018815 | Semiconductor device with reduced contact resistance and method of manufacturing thereof - A method (and semiconductor device) of fabricating a semiconductor device provides a filed effect transistor (FET) with reduced contact resistance (and series resistance) for improved device performance. An impurity is implanted in the source/drain (S/D) regions after contact silicide formation and a spike anneal process is performed that lowers the schottky barrier height (SBH) of the interface between the silicide and the lower junction region of the S/D regions. This results in lower contact resistance and reduces the thickness (and Rs) of the region at the silicide-semiconductor interface. | 01-26-2012 |
20120038009 | Novel methods to reduce gate contact resistance for AC reff reduction - A method (and semiconductor device) of fabricating a semiconductor device provides a field effect transistor (FET) with reduced gate contact resistance (and series resistance) for improved device performance. An impurity is implanted or deposited in the gate stack in an impurity region between the metal gate electrode and the gate contact layer. An anneal process is performed that converts the impurity region into a segregation layer which lowers the schottky barrier height (SBH) of the interface between the metal gate electrode (e.g., silicide) and gate contact layer (e.g., amorphous silicon). This results in lower gate contact resistance and effectively lowers the device's AC Reff. | 02-16-2012 |
20120119281 | INTEGRATED CIRCUIT SYSTEM WITH BANDGAP MATERIAL AND METHOD OF MANUFACTURE THEREOF - A method of manufacturing an integrated circuit system includes: providing a substrate having a channel region; forming a gate stack over a portion of the channel region with the gate stack having a floating gate for storing an electrical charge; forming a source recess in the substrate adjacent to the gate stack; and forming a source by layering a first bandgap material in the source recess. | 05-17-2012 |
20120139046 | ASYMMETRICAL TRANSISTOR DEVICE AND METHOD OF FABRICATION - Embodiments of the invention provide an asymmetrical transistor device comprising a semiconductor substrate, a source region, a drain region and a channel region. The channel region is provided between the source and drain regions, the source, drain and channel regions being provided in the substrate. The device has a layer of a buried insulating medium provided below the source region and not below the drain region thereby forming an asymmetrical structure. The layer of buried insulating medium is provided in abutment with a lower surface of the source region. | 06-07-2012 |
20120168913 | FINFET - A fin type transistor includes a dielectric layer on a substrate surface which serves to isolate the gate of the transistor from the substrate. The dielectric layer includes a non-selectively etched surface to produce top portions of fin structures which have reduce height variations across the wafer. The fin type transistor may also include a counter doped region at least below the S/D regions to reduce parasitic capacitance to improve its performance. | 07-05-2012 |
20120171832 | FINFET WITH STRESSORS - A fin type transistor includes a dielectric layer on a substrate surface which serves to isolate the gate of the transistor from the substrate. The dielectric layer includes a non-selectively etched surface to produce top portions of fin structures which have reduced height variations across the wafer. The fin type transistor may also include a buried stressor and/or raised or embedded raised S/D stressors to cause a strain in the channel to improve carrier mobility. | 07-05-2012 |
20120217467 | BURIED CHANNEL FINFET SONOS WITH IMPROVED P/E CYCLING ENDURANCE - A Fin FET SONOS device is formed with a full buried channel. Embodiments include forming p-type silicon fins protruding from a first oxide layer, an n-type silicon layer over exposed surfaces of the fins, a second oxide layer, a nitride layer, and a third oxide layer sequentially on the n-type silicon layer, and a polysilicon layer on the third oxide layer. Embodiments include etching a silicon layer to form the fins and forming the oxide on the silicon layer. Different embodiments include: etching a silicon layer on a BOX layer to form the fins; forming the fins with a rounded top surface; and forming nano-wires surrounded by an n-type silicon layer, a first oxide layer, a nitride layer, a second oxide layer, and a polysilicon layer over a BOX layer. | 08-30-2012 |
20120223318 | P-CHANNEL FLASH WITH ENHANCED BAND-TO-BAND TUNNELING HOT ELECTRON INJECTION - A p-channel flash memory is formed with a charge storage stack embedded in a hetero-junction layer in which a raised source/drain is formed. Embodiments include forming a dummy gate stack on a substrate, forming a layer on the substrate by selective epitaxial growth, on each side of the dummy gate stack, forming spacers on the layer, forming raised source/drains, removing the dummy gate stack, forming a cavity between the spacers, and forming a memory gate stack in the cavity. Different embodiments include forming the layer of a narrow bandgap material, a narrow bandgap layer under the spacers and a wide bandgap layer adjacent thereto, or a wide bandgap layer under the spacers, a narrow bandgap layer adjacent thereto, and a wide bandgap layer on the narrow bandgap layer. | 09-06-2012 |
20120223394 | SELF-ALIGNED CONTACT FOR REPLACEMENT METAL GATE AND SILICIDE LAST PROCESSES - A high-K/metal gate semiconductor device is provided with larger self-aligned contacts having reduced resistance. Embodiments include forming a first high-k metal gate stack on a substrate between source/drain regions, a second high-k metal gate stack on an STI region, and a first ILD between the metal gate stacks, forming an etch stop layer and a second ILD sequentially over the substrate, with openings in the second ILD over the metal gate stacks, forming spacers on the edges of the openings, forming a third ILD over the second ILD and the spacers, removing the first ILD over the source/drain regions, removing the etch stop layer, the second ILD, and the third ILD over the source/drain regions, adjacent the spacers, and over a portion of the spacers, forming first trenches, removing the third ILD over the second high-k metal gate stack and over a portion of the spacers, forming second trenches, and forming contacts in the first and second trenches. | 09-06-2012 |
20120228676 | CHANNEL SURFACE TECHNIQUE FOR FABRICATION OF FinFET DEVICES - A FinFET (p-channel) device is formed having a fin structure with sloped or angled sidewalls (e.g., a pyramidal or trapezoidal shaped cross-section shape). When using conventional semiconductor substrates having a (100) surface orientation, the fin structure is formed in a way (groove etching) which results in sloped or angled sidewalls having a (111) surface orientation. This characteristic substantially increases hole mobility as compared to conventional fin structures having vertical sidewalls. | 09-13-2012 |
20120228695 | LDMOS WITH IMPROVED BREAKDOWN VOLTAGE - An LDMOS is formed with a field plate over the n | 09-13-2012 |
20120228705 | LDMOS WITH IMPROVED BREAKDOWN VOLTAGE - An LDMOS is formed with a second gate stack over the n | 09-13-2012 |
20120292707 | NANO-ELECTRO-MECHANICAL SYSTEM (NEMS) STRUCTURES ON BULK SUBSTRATES - Semiconductor devices are formed with a nano-electro-mechanical system (NEMS) logic or memory on a bulk substrate. Embodiments include forming source/drain regions directly on a bulk substrate, forming a fin connecting the source/drain regions, forming two gates, one on each side of the fin, the two gates being insulated from the bulk substrate, and forming a substrate gate in the bulk substrate. The fin is separated from each of the two gates and the substrate gate with an air gap. | 11-22-2012 |
20130020626 | MEMORY CELL WITH DECOUPLED CHANNELS - A device having a substrate prepared with a memory cell region having a memory cell is disclosed. The memory cell includes an access transistor and a storage transistor. The access transistor includes first and second source/drain (S/D) regions and the storage transistor includes first and second storage S/D regions. The access and storage transistors are coupled in series and the second S/D regions being a common S/D region. An erase gate is disposed over the common S/D region. A program gate is disposed over the first storage S/D region. Such an arrangement of the memory cell decouples a program channel and an erase channel. | 01-24-2013 |
20130026552 | SPLIT-GATE FLASH MEMORY EXHIBITING REDUCED INTERFERENCE - A split gate memory cell is fabricated with a dielectric spacer comprising a high-k material between the word gate and the memory gate stack. Embodiments include memory cells with a dielectric spacer comprising low-k and high-k layers. Other embodiments include memory cells with an air gap between the word gate and the memory gate stack. | 01-31-2013 |
20130032869 | SPLIT-GATE FLASH MEMORY WITH IMPROVED PROGRAM EFFICIENCY - A split gate memory cell is fabricated with a word gate extending below an upper surface of a substrate having the channel region. An embodiment includes providing a band engineered channel with the word gate extending there through. Another embodiment includes forming a buried channel with the word gate extending below the buried channel. | 02-07-2013 |
20130037877 | DOUBLE GATED FLASH MEMORY - A split gate memory cell is fabricated with a fin structure between a memory gate stack and a select gate. Embodiments include a first channel region under the memory gate stack and a second channel region under the select gate. | 02-14-2013 |
20130187242 | CHANNEL SURFACE TECHNIQUE FOR FABRICATION OF FinFET DEVICES - A FinFET (p-channel) device is formed having a fin structure with sloped or angled sidewalls (e.g., a pyramidal or trapezoidal shaped cross-section shape). When using conventional semiconductor substrates having a (100) surface orientation, the fin structure is formed in a way (groove etching) which results in sloped or angled sidewalls having a (111) surface orientation. This characteristic substantially increases hole mobility as compared to conventional fin structures having vertical sidewalls. | 07-25-2013 |
20130221308 | COMPACT RRAM DEVICE AND METHODS OF MAKING SAME - Disclosed herein is a compact RRAM (Resistance Random Access Memory) device structure and various methods of making such an RRAM device. In one example, a device disclosed herein includes a gate electrode, a conductive sidewall spacer and at least one variable resistance material layer positioned between the gate electrode and the conductive sidewall spacer. | 08-29-2013 |
20130234253 | SELF-ALIGNED CONTACT FOR REPLACEMENT METAL GATE AND SILICIDE LAST PROCESSES - A high-K/metal gate semiconductor device is provided with larger self-aligned contacts having reduced resistance. Embodiments include forming a first high-k metal gate stack on a substrate between source/drain regions, a second high-k metal gate stack on an STI region, and a first ILD between the metal gate stacks, forming an etch stop layer and a second ILD sequentially over the substrate, with openings in the second ILD over the metal gate stacks, forming spacers on the edges of the openings, forming a third ILD over the second ILD and the spacers, removing the first ILD over the source/drain regions, removing the etch stop layer, the second ILD, and the third ILD over the source/drain regions, adjacent the spacers, and over a portion of the spacers, forming first trenches, removing the third ILD over the second high-k metal gate stack and over a portion of the spacers, forming second trenches, and forming contacts in the first and second trenches. | 09-12-2013 |
20130240821 | THREE DIMENSIONAL RRAM DEVICE, AND METHODS OF MAKING SAME - Disclosed herein are various embodiments of novel three dimensional RRAM devices, and various methods of making such devices. In one example, a device disclosed herein includes a first electrode for a first bit line comprising a variable resistance material, a second electrode for a second bit line comprising a variable resistance material and a third electrode positioned between the variable resistance material of the first bit line and the variable resistance material of the second bit line. | 09-19-2013 |
20130270501 | RRAM DEVICE WITH AN EMBEDDED SELECTOR STRUCTURE AND METHODS OF MAKING SAME - One device disclosed herein includes first and second sidewall spacers positioned above a semiconducting substrate, wherein the first and second sidewall spacers are comprised of at least a conductive material, a conductive word line electrode positioned between the first and second sidewall spacers and first and second regions of variable resistance material positioned between the conductive word line electrode and the conductive material of the first and second sidewall spacers, respectively. This example also includes a base region of a bipolar transistor in the substrate below the word line electrode, an emitter region formed below the base region and first and second collector regions formed in the substrate within the base region, wherein the first collector region is positioned at least partially under the first region of variable resistance material and the second collector region is positioned at least partially under the second region of variable resistance material. | 10-17-2013 |
20130270654 | SEMICONDUCTOR DEVICE WITH REDUCED CONTACT RESISTANCE AND METHOD OF MANUFACTURING THEREOF - A method (and semiconductor device) of fabricating a semiconductor device provides a filed effect transistor (FET) with reduced contact resistance (and series resistance) for improved device performance. An impurity is implanted in the source/drain (S/D) regions after contact silicide formation and a spike anneal process is performed that lowers the schottky barrier height (SBH) of the interface between the silicide and the lower junction region of the S/D regions. This results in lower contact resistance and reduces the thickness (and Rs) of the region at the silicide-semiconductor interface. | 10-17-2013 |
20130299764 | LOCALIZED DEVICE - A device is disclosed. The device includes a gate disposed on a substrate in a device region, the gate having first and second sidewalls. The gate includes a gate electrode and a resistive layer disposed between the gate electrode and substrate. First doped regions of a first polarity type are disposed in the substrate adjacent to the first and second sidewalls of the gate. The gate overlaps the first doped regions by a first distance to form overlap portions. A portion of the resistive layer between the gate electrode and overlap portions form first and second storage elements of a multi-bit resistive memory cell. | 11-14-2013 |
20130307038 | FINFET WITH STRESSORS - A fin type transistor includes a dielectric layer on a substrate surface which serves to isolate the gate of the transistor from the substrate. The dielectric layer includes a non-selectively etched surface to produce top portions of fin structures which have reduced height variations across the wafer. The fin type transistor may also include a buried stressor and/or raised or embedded raised S/D stressors to cause a strain in the channel to improve carrier mobility. | 11-21-2013 |
20130341639 | DEEP DEPLETED CHANNEL MOSFET WITH MINIMIZED DOPANT FLUCTUATION AND DIFFUSION LEVELS - CMOS devices are fabricated with a channel layer having minimized dopant fluctuation and diffusion. Embodiments include forming a dummy gate, on a substrate, between a pair of spacers, forming, in the substrate, a source and drain separated by a ground plane layer, removing the dummy gate from the substrate, forming a cavity between the pair of spacers, forming, after removal of the dummy gate, a channel layer on the substrate, forming a high-k layer on the channel layer and on side surfaces of the cavity, and forming a replacement gate in the cavity. | 12-26-2013 |
20140034897 | METHOD FOR FORMING A PCRAM WITH LOW RESET CURRENT - Phase-change memory structures are formed with ultra-thin heater liners and ultra-thin phase-change layers, thereby increasing heating capacities and lowering reset currents. Embodiments include forming a first interlayer dielectric (ILD) over a bottom electrode, removing a portion of the first ILD, forming a cell area, forming a u-shaped heater liner within the cell area, forming an interlayer dielectric structure within the u-shaped heater liner, the interlayer dielectric structure including a protruding portion extending above a top surface of the first ILD, forming a phase-change layer on side surfaces of the protruding portion and/or on the first ILD surrounding the protruding portion, and forming a dielectric spacer surrounding the protruding portion. | 02-06-2014 |
20140048865 | NOVEL COMPACT CHARGE TRAP MULTI-TIME PROGRAMMABLE MEMORY - A method for enabling fabrication of memory devices requiring no or minimal additional mask for fabrication having a low cost, a small footprint, and multiple-time programming capability is disclosed. Embodiments include: forming a gate stack on a substrate; forming a source extension region in the substrate on one side of the gate stack, wherein no drain extension region is formed on the other side of the gate stack; forming a tunnel oxide liner on side surfaces of the gate stack and on the substrate on each side of the gate stack; forming a charge-trapping spacer on each tunnel oxide liner; and forming a source in the substrate on the one side of the gate stack and a drain in the substrate on the other side of the gate stack. | 02-20-2014 |
20140048867 | MULTI-TIME PROGRAMMABLE MEMORY - A device is disclosed. The device includes a substrate and a fin structure disposed on the substrate. The fin structure serves as a common body of n transistors. The transistors include separate charge storage layers and gate dielectric layers. The charge storage layers are disposed over a top surface of the fin structure and the gate dielectric layers are disposed on sidewalls of the fin structure. n=2 | 02-20-2014 |
20140061576 | FIN-TYPE MEMORY - Memory devices and methods for forming a device are disclosed. A substrate prepared with a lower electrode level with bottom electrodes is provided. Fin stack layers are formed on the lower electrode level. Spacers are formed on top of the fin stack layers. The spacers have a width which is less than a lithographic resolution. The fin stack layers are patterned using the spacers as a mask to form fin stacks. The fin stacks contact the bottom electrodes. An interlevel dielectric (ILD) layer is formed on the substrate. The ILD layer fills spaces around the fin stacks. An upper electrode level is formed on the ILD layer. The upper electrode level has top electrodes in contact with the fin stacks. The electrodes and fin stacks form fin-type memory cells. | 03-06-2014 |
20140070159 | NOVEL RRAM STRUCTURE AT STI WITH SI-BASED SELECTOR - An RRAM at an STI region is disclosed with a vertical BJT selector. Embodiments include defining an STI region in a substrate, implanting dopants in the substrate to form a well of a first polarity around and below an STI region bottom portion, a band of a second polarity over the well on opposite sides of the STI region, and an active area of the first polarity over each band of second polarity at the surface of the substrate, forming a hardmask on the active areas, removing an STI region top portion to form a cavity, forming an RRAM liner on cavity side and bottom surfaces, forming a top electrode in the cavity, removing a portion of the hardmask to form spacers on opposite sides of the cavity, and implanting a dopant of the second polarity in a portion of each active area remote from the cavity. | 03-13-2014 |
20140138603 | COMPACT RRAM STRUCTURE WITH CONTACT-LESS UNIT CELL - A RRAM device having a diode device structure coupled to a variable resistance layer is disclosed. The diode device structure can either be embedded into or fabricated over the substrate. A memory device having an array of said RRAM devices can be fabricated with multiple common bit lines and common word lines. | 05-22-2014 |
20140138605 | COMPACT LOCALIZED RRAM CELL STRUCTURE REALIZED BY SPACER TECHNOLOGY - An RRAM is disclosed with a vertical BJT selector. Embodiments include defining a STI region in a substrate, implanting dopants in the substrate to form a first polarity well around and below a bottom portion of the STI region, a second polarity channel over the well on opposite sides of the STI region, and a first polarity active area over each channel at the surface of the substrate, forming an RRAM liner on the active area and STI region, forming a sacrificial top electrode on the RRAM liner, forming spacers on opposite sides of the sacrificial top electrode, implanting a second polarity dopant in the active area on opposite sides of the sacrificial top electrode, forming a silicon oxide adjacent the spacers, removing at least a portion of the sacrificial top electrode forming a cavity, forming in the cavity inner spacers adjacent the spacers and a top electrode. | 05-22-2014 |
20140158970 | NOVEL RRAM STRUCTURE AT STI WITH SI-BASED SELECTOR - An RRAM at an STI region is disclosed with a vertical BJT selector. Embodiments include defining an STI region in a substrate, implanting dopants in the substrate to form a well of a first polarity around and below an STI region bottom portion, a band of a second polarity over the well on opposite sides of the STI region, and an active area of the first polarity over each band of second polarity at the surface of the substrate, forming a hardmask on the active areas, removing an STI region top portion to form a cavity, forming an RRAM liner on cavity side and bottom surfaces, forming a top electrode in the cavity, removing a portion of the hardmask to form spacers on opposite sides of the cavity, and implanting a dopant of the second polarity in a portion of each active area remote from the cavity. | 06-12-2014 |
20140159114 | VERTICAL NANOWIRE BASED HETERO-STRUCTURE SPLIT GATE MEMORY - A memory cell is disclosed. The memory cell includes a vertical base disposed on a substrate. The vertical base includes first and second channels between top and bottom terminals. The memory cell also includes a first gate surrounding the first channel and a second gate surrounding the second channel. The first and second gates form a gate-all-around transistor of the memory cell. | 06-12-2014 |
20140159168 | DEEP DEPLETED CHANNEL MOSFET WITH MINIMIZED DOPANT FLUCTUATION AND DIFFUSION LEVELS - CMOS devices are fabricated with a channel layer having minimized dopant fluctuation and diffusion. Embodiments include forming a dummy gate, on a substrate, between a pair of spacers, forming, in the substrate, a source and drain separated by a ground plane layer, removing the dummy gate from the substrate, forming a cavity between the pair of spacers, forming, after removal of the dummy gate, a channel layer on the substrate, forming a high-k layer on the channel layer and on side surfaces of the cavity, and forming a replacement gate in the cavity. | 06-12-2014 |
20140167161 | FLOATING BODY CELL - Methods of forming a floating body cell (FBC) with faster programming and lower refresh rate and the resulting devices are disclosed. Embodiments include forming a silicon on insulator (SOI) layer on a substrate; forming a band-engineered layer surrounding and/or on the SOI layer; forming a source region and a drain region with at least one of the source region and the drain region being on the band-engineered layer; and forming a gate on the SOI layer, between the source and drain regions. | 06-19-2014 |
20140175381 | TUNNELING TRANSISTOR - Devices and methods for forming a device are presented. The device includes a substrate and a fin type transistor disposed on the substrate. The transistor includes a fin structure which serves as a body of the transistor. The fin structure includes first and second end regions and an intermediate region in between the first and second end regions. A source region is disposed on the first end region, a drain region disposed in the second end region and a gate disposed on the intermediate region of the fin structure. The device includes a channel region disposed adjacent to the source region and a gate dielectric of the gate. A source tunneling junction is aligned to the gate with a controlled channel thickness T | 06-26-2014 |
20140239371 | FIELD EFFECT TRANSISTOR WITH SELF-ADJUSTING THRESHOLD VOLTAGE - Methods for forming field effect transistors (FETs) with improved ON/OFF current ratios in addition to short charging times and the resulting devices are disclosed. Embodiments include forming a gate oxide layer above a channel region in a substrate, forming a partial self-adjusting threshold voltage layer above a drain-side end of the gate oxide layer, and forming a gate above the partial self-adjusting threshold voltage layer and the gate oxide layer. | 08-28-2014 |
20140239391 | LDMOS WITH IMPROVED BREAKDOWN VOLTAGE - An LDMOS is formed with a field plate over the n | 08-28-2014 |
20140264228 | FIN SELECTOR WITH GATED RRAM - A method of fabricating a fin selector with a gated RRAM and the resulting device are disclosed. Embodiments include forming a bottom electrode layer and a hardmask on a semiconductor substrate; etching the hardmask, bottom electrode layer, and semiconductor substrate to form a fin-like structure; forming first and second dummy gate stacks on first and second side surfaces of the fin-like structure, respectively; forming spacers on vertical surfaces of the first and second dummy gate stacks; forming an ILD surrounding the spacers; removing the first and second dummy gate stacks, forming first and second cavities on first and second sides of the fin-like structure; forming an RRAM layer on the first and second side surfaces of the fin-like structure in the first and second cavities, respectively; and filling each of the first and second cavities with a top electrode. | 09-18-2014 |
20140264540 | SCALABLE AND RELIABLE NON-VOLATILE MEMORY CELL - Devices and methods for forming a device are disclosed. The method includes providing a substrate and forming a memory cell pair on the substrate. Each of a memory cell of the memory cell pair includes at least one transistor having first and second gates formed between first and second terminals and a third gate disposed over the second terminal. The first gate serves as an access gate (AG), the second gate serves as a storage gate and the third gate serves as an erase gate (EG). The first cell terminal serves as a bitline terminal and the second cell terminal serves as a source line terminal. The source line terminal is a raised source line terminal and is elevated with respect to the bit line terminal and the source line terminal is common to the memory cell pair. | 09-18-2014 |
20140319448 | METHOD FOR FORMING A PCRAM WITH LOW RESET CURRENT - Phase-change memory structures are formed with ultra-thin heater liners and ultra-thin phase-change layers, thereby increasing heating capacities and lowering reset currents. Embodiments include forming a first interlayer dielectric (ILD) over a bottom electrode, removing a portion of the first ILD, forming a cell area, forming a u-shaped heater liner within the cell area, forming an interlayer dielectric structure within the u-shaped heater liner, the interlayer dielectric structure including a protruding portion extending above a top surface of the first ILD, forming a phase-change layer on side surfaces of the protruding portion and/or on the first ILD surrounding the protruding portion, and forming a dielectric spacer surrounding the protruding portion. | 10-30-2014 |
20140346603 | TRANSISTOR DEVICES HAVING AN ANTI-FUSE CONFIGURATION AND METHODS OF FORMING THE SAME - Transistor devices having an anti-fuse configuration and methods of forming the transistor devices are provided. An exemplary transistor device includes a semiconductor substrate including a first fin. A first insulator layer overlies the semiconductor substrate and has a thickness less than a height of the first fin. The first fin extends through and protrudes beyond the first insulator layer to provide a buried fin portion and an exposed fin portion. A gate electrode structure overlies the exposed fin portion. A gate insulating structure is disposed between the first fin and the gate electrode structure. The gate insulating structure includes a first dielectric layer overlying a first surface of the first fin. The gate insulating structure further includes a second dielectric layer overlying a second surface of the first fin. A potential breakdown path is defined between the first fin and the gate electrode structure through the first dielectric layer. | 11-27-2014 |
20150054043 | SIMPLE AND COST-FREE MTP STRUCTURE - Non-volatile (NV) Multi-time programmable (MTP) memory cells are presented. The memory cell includes a substrate and first and second wells in the substrate. The memory cell includes first transistor having a select gate, second transistor having a floating gate adjacent to one another and on the second well, and third transistor having a control gate on the first well. The control gate is coupled to the floating gate and the control and floating gates include the same gate layer extending across the first and second wells. The transistors include first and second diffusion regions disposed adjacent to sides of the gates. The first and second diffusion regions include base lightly doped drain (LDD) and halo regions. One of the first and second diffusion regions of one of the second and third transistors includes second LDD and halo regions having higher dopant concentrations than the base LDD and halo regions. | 02-26-2015 |
20150069512 | FINFET - A fin type transistor includes a dielectric layer on a substrate surface which serves to isolate the gate of the transistor from the substrate. The dielectric layer includes a non-selectively etched surface to produce top portions of fin structures which have reduce height variations across the wafer. The fin type transistor may also include a counter doped region at least below the S/D regions to reduce parasitic capacitance to improve its performance. | 03-12-2015 |
20150104915 | MEMORY CELL WITH DECOUPLED CHANNELS - A device having a substrate prepared with a memory cell region having a memory cell is disclosed. The memory cell includes an access transistor and a storage transistor. The access transistor includes first and second source/drain (S/D) regions and the storage transistor includes first and second storage S/D regions. The access and storage transistors are coupled in series and the second S/D regions being a common S/D region. An erase gate is disposed over the common S/D region. A program gate is disposed over the first storage S/D region. Such an arrangement of the memory cell decouples a program channel and an erase channel. | 04-16-2015 |
20150108432 | HIGH ION AND LOW SUB-THRESHOLD SWING TUNNELING TRANSISTOR - Devices and manufacturing methods thereof are presented. The device includes a substrate and a fin-type transistor disposed on the substrate. The transistor includes a fin structure that protrudes from the substrate to serve as a source of the transistor. The fin structure is doped with dopants of a first polarity. The transistor also includes a gate layer formed over and around a first end of the fin structure to serve as a gate of the transistor. A drain layer is disposed over the fin structure and adjacent to the gate layer to serve as a drain of the transistor. The drain layer is doped with dopants of a second polarity opposite the first polarity. | 04-23-2015 |
20150123068 | FIN-TYPE MEMORY - Memory devices and methods for forming a device are disclosed. A substrate prepared with a lower electrode level with bottom electrodes is provided. Fin stack layers are formed on the lower electrode level. Spacers are formed on top of the fin stack layers. The spacers have a width which is less than a lithographic resolution. The fin stack layers are patterned using the spacers as a mask to form fin stacks. The fin stacks contact the bottom electrodes. An interlevel dielectric (ILD) layer is formed on the substrate. The ILD layer fills spaces around the fin stacks. An upper electrode level is formed on the ILD layer. The upper electrode level has top electrodes in contact with the fin stacks. The electrodes and fin stacks form fin-type memory cells. | 05-07-2015 |
20150129975 | MULTI-TIME PROGRAMMABLE DEVICE - Devices and methods for forming a device are presented. The device includes a substrate having a device region and first and second isolation regions surrounding the device region. The device includes a multi-time programmable (MTP) memory cell having a single transistor disposed on the device region. The transistor includes a gate having a gate electrode over a gate dielectric which includes a programmable resistive layer. The gate dielectric is disposed over a channel region having first and second sub-regions in the substrate. The gate dielectric disposed above the first and second sub-regions has different characteristics such that when the memory cell is programmed, a portion of the programmable resistive layer above one of the first or second sub-region is more susceptible for programming relative to portion of the programmable resistive above the other first or second sub-region. | 05-14-2015 |
20150137060 | HIGH RECTIFYING RATIO DIODE - Devices and methods for forming a device are disclosed. The device includes a substrate and a selector diode disposed over the substrate. The diode includes first and second terminals. The first terminal is disposed between the second terminal and the substrate. The diode includes a Schottky Barrier (SB) disposed at about an interface of the first and second terminals. The SB includes a tunable SB height defined by a SB region having segregated dopants. The device includes a memory element disposed over and coupled to the selector diode. | 05-21-2015 |
20150162436 | FINFET WITH ISOLATION - Devices and methods for forming a device are presented. The method includes providing a substrate prepared with a device region. A fin is formed in the device region. The fin includes top and bottom portions. An isolation layer is formed on the substrate. The isolation layer has a top isolation surface disposed below a top fin surface, leaving an upper fin portion exposed. At least one isolation buffer is formed in the bottom fin portion, leaving the top fin portion crystalline, the top fin portion serves as a body of a fin type transistor. Source/drain (S/D) regions are formed in the top portions of the fin and a gate wrapping around the fin is provided. | 06-11-2015 |
20150187784 | THREE-DIMENSIONAL NON-VOLATILE MEMORY - A three-dimensional one-transistor non-volatile memory device and a manufacturing method thereof are provided. The memory device includes a primary fin disposed on a substrate along a first direction, first and second secondary fins disposed on the substrate along a second direction, and a first gate of a first memory cell disposed on the substrate in a gate region thereof. The first gate includes a program gate, a floating gate and a control gate. | 07-02-2015 |
20150188047 | COMPACT LOCALIZED RRAM CELL STRUCTURE REALIZED BY SPACER TECHNOLOGY - An RRAM is disclosed with a vertical BJT selector. Embodiments include defining a STI region in a substrate, implanting dopants in the substrate to form a first polarity well around and below a bottom portion of the STI region, a second polarity channel over the well on opposite sides of the STI region, and a first polarity active area over each channel at the surface of the substrate, forming an RRAM liner on the active area and STI region, forming a sacrificial top electrode on the RRAM liner, forming spacers on opposite sides of the sacrificial top electrode, implanting a second polarity dopant in the active area on opposite sides of the sacrificial top electrode, forming a silicon oxide adjacent the spacers, removing at least a portion of the sacrificial top electrode forming a cavity, forming in the cavity inner spacers adjacent the spacers and a top electrode. | 07-02-2015 |
20150221651 | 1T SRAM/DRAM - One-transistor (1T) volatile memory devices and manufacturing methods thereof are provided. The device includes a substrate having top and bottom surfaces and an isolation buffer layer disposed below the top substrate surface. The isolation buffer layer is an amorphized portion of the substrate. An area of the substrate between the isolation buffer layer and the top substrate surface serves as a body region of a transistor. The device also includes a transistor disposed over the substrate. The transistor includes a gate disposed on the top substrate surface, and first and second diffusion regions disposed in the body region adjacent to first and second sides of the gate. | 08-06-2015 |
20150221652 | 1T SRAM/DRAM - One-transistor volatile memory devices and manufacturing methods thereof are provided. The device includes a substrate having top and bottom surfaces and an isolation well disposed below the top substrate surface. An area of the substrate between the isolation buffer layer and the top substrate surface serves as a body region of a transistor. The isolation well isolates the body region from the substrate. The device includes a band engineered (BE) floating body disposed over the isolation well and within the body region. The device also includes a transistor disposed over the substrate. The transistor includes a gate disposed on the top substrate surface, and first and second diffusion regions disposed in the body region adjacent to first and second sides of the gate. | 08-06-2015 |
20150221761 | DEVICE WITH ISOLATION BUFFER - Devices and methods for forming a device are presented. A substrate prepared with a device region is provided. A fin is formed in the device region. The fin includes top and bottom portions. An amorphous isolation buffer is formed at least in the bottom fin portion, leaving the top fin portion crystalline. The top fin portion serves as a body of a fin type transistor. | 08-06-2015 |
20150221867 | FIN SELECTOR WITH GATED RRAM - A method of fabricating a fin selector with a gated RRAM and the resulting device are disclosed. Embodiments include forming a bottom electrode layer and a hardmask on a semiconductor substrate; etching the hardmask, bottom electrode layer, and semiconductor substrate to form a fin-like structure; forming first and second dummy gate stacks on first and second side surfaces of the fin-like structure, respectively; forming spacers on vertical surfaces of the first and second dummy gate stacks; forming an ILD surrounding the spacers; removing the first and second dummy gate stacks, forming first and second cavities on first and second sides of the fin-like structure; forming an RRAM layer on the first and second side surfaces of the fin-like structure in the first and second cavities, respectively; and filling each of the first and second cavities with a top electrode. | 08-06-2015 |
20150236034 | NOVEL COMPACT CHARGE TRAP MULTI-TIME PROGRAMMABLE MEMORY - A memory device requiring no or minimal additional mask for fabrication having a low cost, a small footprint, and multiple-time programming capability is disclosed. Embodiments include: a substrate; a gate stack on the substrate; a source and drain in the substrate at opposite sides, respectively, of the gate stack; a source extension region in the substrate adjacent the source region, wherein no drain extension region is formed on the other side of the gate stack; a tunnel oxide liner on the substrate at each side of the gate stack and on side surfaces of the gate stack; and a charge-trapping (CT) spacer on each tunnel oxide liner. | 08-20-2015 |
20150255471 | SPLIT-GATE FLASH MEMORY EXHIBITING REDUCED INTERFERENCE - A split gate memory cell is fabricated with a dielectric spacer comprising a high-k material between the word gate and the memory gate stack. Embodiments include memory cells with a dielectric spacer comprising low-k and high-k layers. Other embodiments include memory cells with an air gap between the word gate and the memory gate stack. | 09-10-2015 |
20150325697 | LDMOS WITH IMPROVED BREAKDOWN VOLTAGE - An LDMOS is formed with a second gate stack over n | 11-12-2015 |
20150333068 | THYRISTOR RANDOM ACCESS MEMORY - Devices and methods for forming a device are presented. The device includes a substrate having a well of a first polarity type and a thyristor-based memory cell. The thyristor-based memory cell includes at least a first region of a second polarity type adjacent to the well, a gate which serves as a second word line disposed on the substrate, at least a first layer of the first polarity type disposed adjacent to the first region of the second polarity type and adjacent to the gate, and at least a heavily doped first layer of the second polarity type disposed on the first layer of the first polarity type and adjacent to the gate. At least the heavily doped first layer of the second polarity type is self-aligned with side of the gate. | 11-19-2015 |
20150333103 | VERTICAL RANDOM ACCESS MEMORY WITH SELECTORS - Devices and methods for manufacturing a device are presented. The device includes a substrate and a vertical structure disposed over the substrate. The vertical structure includes one or more memory cell stacks with a dielectric layer between every two adjacent cell stacks. Each of the one or more cell stacks includes first and second first type conductors on first and second sides of the cell stack, respectively; first and second electrodes, the first electrode adjacent the first first type conductor, the second electrode adjacent the second first type conductor; and first and second memory elements, the first memory element disposed between the first first type conductor and the first electrode, the second memory element disposed between the second first type conductor and the second electrode. The device also includes a selector element disposed over the substrate and vertically traversing through a middle portion of the vertical structure. The selector element includes respective first and second selector diodes for the first and second memory elements of each of the one or more cell stacks. | 11-19-2015 |
20150357561 | INTEGRATED CIRCUITS WITH HALL EFFECT SENSORS AND METHODS FOR PRODUCING SUCH INTEGRATED CIRCUITS - Integrated circuits with a Hall effect sensor and methods for fabricating such integrated circuits are provided. The method includes forming a buried plate layer within a substrate and overlying a substrate base, where the buried plate layer is doped with an “N” type dopant. A cover insulating layer if formed overlying the buried plate layer, and a plurality of contact points are formed adjacent to the cover insulating layer. | 12-10-2015 |
20160028009 | RESISTIVE MEMORY DEVICE - A non-volatile memory device and a manufacturing method thereof are provided. The memory device includes a substrate, a lower cell dielectric layer with gate conductors and a body unit conductor disposed on the lower cell dielectric layer and gates. Memory element conductors are disposed on the body unit and lower cell dielectric layer. An upper cell dielectric layer may be on the substrate and over the lower cell dielectric layer, body unit conductor and memory element conductors. The upper cell dielectric layer isolates the memory element conductors. | 01-28-2016 |
20160035873 | FINFET WITH STRESSORS - A fin type transistor includes a dielectric layer on a substrate surface which serves to isolate the gate of the transistor from the substrate. The dielectric layer includes a non-selectively etched surface to produce top portions of fin structures which have reduced height variations across the wafer. The fin type transistor may also include a buried stressor and/or raised or embedded raised S/D stressors to cause a strain in the channel to improve carrier mobility. | 02-04-2016 |
20160064398 | INTEGRATED CIRCUITS WITH FINFET NONVOLATILE MEMORY - Integrated circuits and methods for producing the same are provided. A method for producing an integrated circuit includes forming a first and second fin overlying a substrate, where the first and second fins intersect at a fin intersection. The first fin has a first fin left end. A tunnel dielectric and a floating gate are formed adjacent to the first fin with the tunnel dielectric between the floating gate and the first fin. An interpoly dielectric is formed adjacent to the floating gate, and a control gate is formed adjacent to the interpoly dielectric such that the interpoly dielectric is between the floating gate and the control gate. The control gate, interpoly dielectric, floating gate, and the tunnel dielectric are removed from over the first fin except for at a floating gate position between the first fin left end and the fin intersection. | 03-03-2016 |
20160079310 | SELECTOR-RESISTIVE RANDOM ACCESS MEMORY CELL - Memory devices and manufacturing methods thereof are presented. A memory device a substrate and a memory cell having at least one selector and a storage element. | 03-17-2016 |
20160087197 | NON-VOLATILE RESISTIVE RANDOM ACCESS MEMORY CROSSBAR DEVICES WITH MAXIMIZED MEMORY ELEMENT DENSITY AND METHODS OF FORMING THE SAME - Non-volatile resistive random access memory crossbar devices and methods of fabricating the same are provided herein. In an embodiment, a non-volatile resistive random access memory crossbar device includes a crossbar array including a bitline and a wordline. A hardmask that includes dielectric material is disposed over the bitline. The hardmask and the bitline include a first sidewall. A memory element layer and a selector layer are disposed in overlying relationship on the first sidewall of the bitline and hardmask. The memory element layer and a selector layer are further disposed between the bitline and the wordline, to form a first memory element and selector pair. | 03-24-2016 |
20160093630 | DOUBLE GATED FLASH MEMORY - A split gate memory cell is fabricated with a fin structure between a memory gate stack and a select gate. Embodiments include a first channel region under the memory gate stack and a second channel region under the select gate. | 03-31-2016 |
20160111629 | INTEGRATED CIRCUIT STRUCTURES WITH SPIN TORQUE TRANSFER MAGNETIC RANDOM ACCESS MEMORY AND METHODS FOR FABRICATING THE SAME - A method for fabricating an STT-MRAM integrated circuit includes forming a fixed layer over a bottom electrode layer, forming a silicon oxide layer a hardmask layer over the fixed, and forming a trench within the silicon oxide and hardmask layers, thereby exposing an upper surface of the fixed layer and sidewalls of the silicon oxide and hardmask layer. The method further includes forming a conformal barrier layer along the sidewalls of the silicon oxide and hardmask layers and over the upper surface of the fixed layer, such that the conformal barrier layer comprises sidewall portions adjacent the sidewalls of the silicon oxide and hardmask layers and a central portion in between the sidewall portions and adjacent the upper surface of the fixed layer. The method further includes forming a free layer between the sidewall portions of the barrier layer and over the central portion of the barrier layer. | 04-21-2016 |
Er-Yi Toh, Singapore SG
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20140195385 | APPARATUS AND A METHOD FOR SIMPLYING AND DISPLAYING INFORMATION - A method of generating a presentation comprising providing a collection of content where each unit of content has an identifier, providing a seed unit of content that contains references to the said identifiers, searching the existing collection of content for units of content with identifiers that are referenced by the seed unit of content, generating a presentation by gathering all units of content that were found in the said searching, whereby the presentation generated can contain more content than the seed content. Also a method of placing an order comprising providing an item with a plurality of pricing tiers, providing pricing rules for enforcing the said pricing tiers, providing a criterion, providing a method to identify inputs required from the user such that an order can be created that meets the requirements of the user while optimizing said criterion while conforming to the said pricing rules, requesting the said identified inputs from the user of the client system, whereby the user of the client system is not exposed to the pricing tiers and is not able to submit an order that violates the pricing rules. Also an apparatus. | 07-10-2014 |
Guek Geok Alicia Toh, Singapore SG
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20150137015 | CONNECTOR FOR MICROFLUIDIC DEVICE, A METHOD FOR INJECTING FLUID INTO MICROFLUIDIC DEVICE USING THE CONNECTOR AND A METHOD OF PROVIDING AND OPERATING A VALVE - A connector for being inserted into a first channel of a microfluidic device. The connector includes a first end and a second end, when seen in the direction of a longitudinal central axis of said connector, wherein the second end is arranged in a second end portion of the connector; an inner hollow space; a outer circumferential wall extending around said longitudinal central axis, such that said outer circumferential wall extends around said inner hollow space. The outer circumferential wall has at least two different outer diameters along said longitudinal central axis, which outer diameters differ in their value; and the outer surface of said circumferential wall is rotationally symmetrical with regard to said longitudinal central axis; an opening provided in said first end for receiving an insert and, being in fluid connection with said inner hollow space; and a membrane sealingly covering said inner hollow space towards said second end of the connector, wherein the insert is configured to provide pressure on said membrane. | 05-21-2015 |
Haikin Toh, Singapore SG
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20140105717 | PNP APPARATUS WITH PICK-UP TIP AND RELATED METHODS - A PNP apparatus may include a robotic arm, and a PNP tool head carried by the robotic arm. The PNP tool head may include a body configured to apply bonding pressure to a first area of an electronic device, and a pick-up tip movable between an extended position and a retracted position relative to the body as the pick-up tip rests against a second area of the electronic device. The pick-up tip may define a vacuum passageway therethrough to couple a vacuum source to the second area of the electronic device. | 04-17-2014 |
Hong Tat Toh, Singapore SG
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20100048209 | Wireless Communication Terminal Apparatus and Wireless Communication Method - A wireless communication terminal apparatus and a wireless communication method wherein a measurement operation, which is suitable for a long DRX/DTX interval, is controlled without providing any new signaling between a terminal and a base station. When a DRX threshold terminal status determining part ( | 02-25-2010 |
20100159950 | RADIO COMMUNICATION BASE STATION DEVICE, RADIO COMMUNICATION TERMINAL DEVICE, AND GAP GENERATION METHOD - It is possible to provide a radio communication base station device, a radio communication terminal device, and a radio communication method which reduce a signaling load and perform flexible gap allocation. A target gap length generation unit ( | 06-24-2010 |
20100190487 | GAP SUPPORT MEASURING METHOD - Disclosed is a gap support measuring method which performs autonomous gap allocation without lowering the data transfer rate or the throughput. ST | 07-29-2010 |
20100309803 | RADIO COMMUNICATION TERMINAL DEVICE AND GAP ALLOTTING METHOD - The invention provides a wireless communication terminal device and a gap allotting method capable of completing a measuring process at high speed and reducing the number of retransmissions. Upon determining that the average number of retransmissions exceeds the parameter for the average number of retransmissions in gap length change judging unit ( | 12-09-2010 |
20100330994 | BASE STATION, RADIO COMMUNICATION SYSTEM, AND HANDOVER METHOD - When a handover request for performing a handover of a terminal ( | 12-30-2010 |
20110141908 | WIRELESS TRANSMITTING DEVICE AND WIRELESS RECEIVING DEVICE - A wireless transmitting device ( | 06-16-2011 |
20120033595 | WIRELESS COMMUNICATION TERMINAL APPARATUS, WIRELESS COMMUNICATION BASE STATION APPARATUS, AND WIRELESS COMMUNICATION METHOD - A wireless communication terminal apparatus and wireless communication method, wherein the time necessary for implementation of handover is reduced without increasing the complexity of the configuration of the wireless communication terminal apparatus. A gap confirmation unit ( | 02-09-2012 |
20120057474 | METHOD AND APPARATUS FOR HANDOVER CONTROL IN A MOBILE COMMUNICATION SYSTEM WITH CSG - Due to the coverage size of the CSG cell, handover to macro-cell may occur frequently. These handovers are not desirable to both the user and operators. However, to disable or delay the handover of the CSG Cell would cause UE experiencing radio link failure and not able to re-establish connection to other cells. The present invention introduces a method for the UE to increase the stickiness to the CSG cells based on the user preferences and application requirements. When applied, it keeps the UE to the CSG cell as long as possible and reduces the possibility of connection re-establishment failure. The invention is also applicable to the corporate network deployment with multiple CSG cells. | 03-08-2012 |
20120088505 | BASE STATION CONTROLLER AND MOBILE TERMINAL - An HeNB-GW ( | 04-12-2012 |
20120100856 | MOBILE COMMUNICATION SYSTEM, TERMINAL DEVICE, AND BASE STATION - In a mobile communication system, a handover of a terminal device (MT) from a macrocell base station (eNB) to a small cell base station (HeNB) is controlled via a host device (MME or HeNB-GW). Physical cell ID deployment map information (PCI deployment map information), which includes at least information (PCI/CGI map information) indicating the correspondences between physical cell IDs and unique cell IDs of CSG cells for which access is granted, is generated in the host device (MME or HeNB-GW). When the terminal device measures the reception quality for surrounding CSG cells for handover control to any of the CSG cells, the terminal device uses the PCI deployment map information to generate a measurement result report. Thus, a service interruption caused by handover control to an inaccessible small cell can be avoided, and the wait time for handover control can be reduced. | 04-26-2012 |
20140087732 | BASE STATION, RADIO COMMUNICATION SYSTEM, AND HANDOVER METHOD - When a handover request for performing a handover of a terminal ( | 03-27-2014 |
Jerry Kah Chin Toh, Singapore SG
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20130202672 | FIBER-ASSEMBLED TISSUE CONSTRUCTS - The present invention relates to a fiber-assembled tissue construct comprising at least one sinusoid unit, the unit comprising at least two polymeric fibers arranged in a sinusoid structure and fused together, each of said fibers comprising a porous matrix supporting biological components encapsulated in the fiber, wherein the biological components are patterned in three-dimensions within the construct. | 08-08-2013 |
20130288287 | FIBROUS STRUCTURE - A fibrous structure comprising an assembly of hair follicle cells within a fibrous matrix. | 10-31-2013 |
20150050711 | DEVICE FOR MANUFACTURING POLYMER FIBERS AND USES THEREOF - There is provided a device, and related method and uses, for drawing a polymer fiber, the device comprising: a. at least two polymer compartments, wherein each polymer compartment is capable of retaining a polymer solution, and wherein adjacent compartments comprise different polymer solutions; and b. a slider comprising at least one prong, wherein the prong is capable of contacting the different polymer solutions, and wherein the slider is arranged in a retractable manner from the at least two polymer compartments. There is further provided a system and a related method for manufacturing a polymer fiber. | 02-19-2015 |
Joo Pheng Toh, Singapore SG
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20120319368 | PACKAGE INCLUDING A BOX-LIKE CONTAINER AND A USE OF THE PACKAGE - A package ( | 12-20-2012 |
Kah-Lun Toh, Singapore SG
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20100190272 | REWORK METHOD OF METAL HARD MASK - A rework method of a metal hard mask layer is provided. First, a material layer is provided. A dielectric layer, a first metal hard mask layer, and a patterned first dielectric hard mask layer have been sequentially formed on the material layer. There is a defect on a region of the first metal hard mask layer, and therefore the region of the first metal hard mask layer is not able to be patterned. After that, the patterned first dielectric hard mask layer and the first metal hard mask layer are removed. A planarization process is then performed on the dielectric layer. Next, a second metal hard mask layer and a second dielectric hard mask layer are sequentially formed on the dielectric layer. | 07-29-2010 |
Kok Meng Michael Toh, Singapore SG
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20140149939 | Apparatus And Method For Enabling Access To A Plurality of Activities - There is provided an apparatus and a method for enabling access to a plurality of activities. The apparatus includes a processor for controlling the apparatus; and a communications module coupled to the processor for connecting the apparatus to a data network. The communications module may connect to the data network wirelessly. The plurality of activities may include, for example, consuming media content, carrying out e-shopping, playing video games, carrying out communications and so forth. | 05-29-2014 |
Kok Onn Toh, Singapore SG
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20130272898 | Instrumenting High Reliability Electric Submersible Pumps - Instrumentation for high reliability electric submersible pumps (ESPs) is provided. Comprehensive sensors placed throughout ESP components enable monitoring, analysis, and intervention to improve performance of ESP components and provide high reliability and long life for components. Example ESP sensors used to protectively monitor an ESP string may include electrical current leakage detectors, temperature sensors at the pothead, fiber optics used as distributed temperature sensors in the motor stator and windings of the motor, water cut sensors to determine quality of hydrocarbon being produced, tachometer and torque sensors to detect the speed of rotating shafts of the motors and pumps, temperature and vibration sensors for rotor bearings and thrust members, and wye-point imbalance detectors for balancing electrical loads on the three phases in a wye system. Interpretation and control modules analyze the sensor input and apply actions that improve performance and lengthen lifespan of components. | 10-17-2013 |
Kok Swee Toh, Singapore SG
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20100162585 | HAIR DRYER - The present invention relates to hair dryer having a fan and a heater. The hair dryer has a PCB board having programmable integrated circuit (IC) components mounted thereon, wherein the fan and the heater are also connected to the PCB board; a plurality of presets defining operating levels of the fan and the heater, alone or in any combinations; a multi-mode switch connected to the PCB board for controlling the plurality of presets, the multi-mode switch is positioned at an one-hand operable location on the hair dryer, wherein user is able to operate the hair dryer with only a hand holding hair dryer and controlling the plurality of presets through the multi-mode switch. | 07-01-2010 |
20140075694 | Induction Heated Hair Styling Appliances And The Heating Unit Therefor - A heated hair-styling appliance for styling hair through heat is provided. The heated hair-styling appliance comprises a heating head having an outer shell covering at least part of the surface thereof, and an inner heat source core disposed within the inner part of the heating head, and a handle attached to a distal end of the heating head. The heated hair-styling appliance works in conjunction with an independent heating unit to heat up the inner heat source core, and the heat source core operationally supplies heat to heat up the outer shell for styling hair after it is being heated. A induction heating unit therefor is also provided. | 03-20-2014 |
20140076887 | Induction Heated Hair Styling Appliances And The Heating Unit Therefor - The present invention provides an induction heating unit for heating up a hair styling appliance. The induction heating unit comprises a container defining a well that is surrounded by an induction coil winding, a controller electrically connected to the induction coil winding to operationally control a heating power; and a sensor plug disposed at the bottom on the well, the sensor plug adapted for coupling with a sensor socket on the hair styling appliance to detect at least temperature of the hair styling appliance through a temperature sensor, wherein the controller operationally controls a heating power based at least on the temperature detected through the temperature sensor. A method of heating up a hair styling appliance is also provided. | 03-20-2014 |
Michael Jc Toh, Singapore SG
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20160034342 | OPERATIONAL VIBRATION COMPENSATION THROUGH MEDIA CACHE MANAGEMENT - Apparatus and method for managing a media cache through the monitoring of operational vibration of a data storage device. In some embodiments, a non-volatile media cache of the data storage device is partitioned into at least first and second zones having different data recording characteristics. Input data are received for storage in a non-volatile main memory of the data storage device. An amount of operational vibration associated with the data storage device is measured. The input data are stored in a selected one of the first or second zones of the media cache prior to transfer to the main memory responsive to a comparison of the measured amount of operational vibration to a predetermined operational vibration threshold. | 02-04-2016 |
Michael Kok Meng Toh, Singapore SG
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20150296245 | REMOTE CONTROLLER - A remote controller for an interactive system for a system delivering content to a display screen is provided. The system includes a set top box coupled between a central content server and a display screen. The remote controller has basic controller functionalities, such as a plurality of keys for controlling various functions to be carried out by the set top box, and an infrared transmitter in the remote controller for carrying out infrared communication. The remote controller includes wireless communications module for establishing a wireless connection between the remote controller and the set top box. | 10-15-2015 |
Mui Lian Jessica Toh, Singapore SG
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20090137142 | POSITIVE LOCK CONNECTOR - A connector assembly ( | 05-28-2009 |
20090186492 | ROTATABLE ELECTRICAL PLUG CONNECTOR - A rotatable electrical plug connector includes a main body and an auxiliary plug which is rotatably coupled to the main body. The main body is provided with fixed electrical terminals, the auxiliary plug is provided with electrical blades, and the rotatable electrical plug connector has electrical connection members connecting the electrical terminals and the electrical blades. The auxiliary plug is io rotatable relative to the main body, and may be fixed to the main body at any predetermined position. At each predetermined position and during rotation of the auxiliary plug, the electrical blades and the electrical terminals are electrically connected at all times. A rotatable electrical plug connector according to embodiments of the present invention is suitable to connect to power supply is sockets at convenient engagement positions. | 07-23-2009 |
20130078867 | DUCK HEAD CONNECTOR - Embodiments are directed to a duck head connector comprised of a connector for connecting to a power adapter and an electric plug that swivels about the face of the side of the plug, where flexible insulated wires connect the prongs of the electric plug with the contacts of the connector. The flexible insulated wires rotate together with the plug, with the length and shape of the wires enabling the wires to wrap around each other without becoming tangled. In an alternative embodiment, a pair of spring contacts connects the prongs of the electric plug with a pair of stationary half-ring contacts. The spring contacts swivel along the inner surface of the half-ring contacts when the plug rotates. Flexible insulated wires connect the stationary half-ring contacts to the contacts of the connector. | 03-28-2013 |
20130196548 | SLIM C5/C6 COUPLER - Embodiments relate to a C5/C6 coupler having a substantially equivalent shape and size as a C7/C8 coupler. Embodiments relate to a power supply cord that provides an earth connection to the cord. Still more particularly, embodiments relate to a slim inlet that provides a make-first-and-break-last earth connection and prevents incompatible cords, different type of connectors, from being connected to the slim inlet. | 08-01-2013 |
20150071590 | ROTATABLE CONNECTOR AND ASSEMBLY METHODS - A rotatable power/signal connector includes a fixing part and a rotating part. The fixing part comprises a housing portion in which a set of terminals is mounted for terminating conduits, an upper inner cover with recesses for receiving a first resilient member and a first gear, and a lower inner cover with recesses for receiving a second resilient member and a second gear. The rotating part comprises an upper outer cover with the first gear, a lower outer cover with the second gear, the first resilient member, and the second resilient member. The rotating part is rotatable relative to the fixing part and fixable to the fixing part at a number of predetermined positions. | 03-12-2015 |
20150104967 | POSITIVE LOCK CONNECTOR FOR SMALL POWER COUPLERS - A coupler including a housing is configured to affix individual lines of a multiline cable within the housing, the housing including a front portion for engaging an inlet, a rear portion, and an upper portion including a raised central area and at least one lowered side area. A sliding lock including a lock housing is configured to slide over the raised central area and the at least one lowered side area and at least one spring arm affixed to the lock housing; and an outer mold configured to engage the rear portion of the housing and constrain the sliding lock within a gap formed between the housing and the outer mold. The sliding lock is configured to slide forward within the gap to engage the inlet and lock the sliding lock in place, thereby locking the connector to the inlet, and slide backward within the gap and disengage the inlet. | 04-16-2015 |
20150135491 | INTERCHANGEABLE AND DETACHABLE FLANGE FOR CONNECTOR - An interchangeable and detachable flange for a connector is described. A flange with a circular opening can be secured to an electrical or other type of connector by a locking mechanism. The locking mechanism is engaged and disengaged by twisting the flange around the connector. The locking mechanism may consist of a tongue that slides into a slot when the flange is twisted around the connector, and may further consist of a raised knob that fits into a recess for the raised knob. | 05-21-2015 |
20150280365 | COLLAPSIBLE PLUG WITH EXTRACTION COMPONENT - An electrical plug having an extraction component that may be collapsed to decrease the profile of the plug and may be retracted to increase the profile of the plug. Increasing the profile of the plug increases the graspable area of the plug, making it easier to extract the plug from an outlet socket. The extraction component may be a slidable cover substantially surrounding a housing holding the pins and wiring of the plug within an overmold. The extraction component may also be a slidable cap connected to a pin bridge surrounded by an overmold. Openings formed within the pin bridge include a stopper that limits the retraction of the extraction component. The extraction components include a number of snap-fit pins that are each inserted into the openings beyond the stoppers, at which point the snap-fit ends of the pins expand and hold pins within the openings. | 10-01-2015 |
20160134070 | ELECTRICAL CONNECTOR WITH ROTATABLE PRONGS - An electrical connector for connecting to a power adapter or an electrical device that includes prongs that can move between a storage position and a working position. One of the prongs may be located a greater distance from the terminals of the electrical connector than the other. A recess in the connector may allow the prongs to be accessed by a human finger when the prongs are in the storage position. The electrical connector may be detached from a corresponding electrical device, and have a slot that meets a rail of the electrical device to guide alignment of the electrical connector with the electrical device. The electrical device may also have a second recess that meets the recess of the electrical connector when the terminal housing is mated to the inlet of the electrical device. | 05-12-2016 |
20160134071 | ELECTRICAL CONNECTOR WITH ROTATABLE PRONGS - An electrical connector that includes a connector for connecting to a power adapter or directly connecting to an electrical device, and an electrical plug for connecting to a main supply. The electrical plug can move between a storage position, a first working position, and a second working position. The electrical plug may have a mechanism that fixes the prongs of the plug in one of these positions unless greater than a threshold amount of force is exerted on the prongs in a particular direction. In the storage position, the electrical plug may be inaccessible to an electrical outlet and electrically disconnected from the terminals of the connector. The first working position, second working position, and storage position may all be substantially perpendicular to each other. The plug may be moved from the second working position to the storage position by passing through the first working position. | 05-12-2016 |
Rui Tze Toh, Singapore SG
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20150097240 | GROUNDING OF SILICON-ON-INSULATOR STRUCTURE - Devices and methods for forming a device are presented. The method includes providing a substrate having at least a first region and a second region prepared with isolation regions. The first region is referred to as a chip guarding area and the second region defines a chip region of which at least one transistor is to be formed. The substrate includes a top surface layer, a support substrate and an insulator layer in between them. A transistor is formed in the second region and a substrate contact structure is formed in the first region. The substrate contact structure passes through at least the top surface layer, insulator layer and isolation region and contacts a doped region in the support substrate. The substrate contact structure is connected to at least one conductive line with a desired potential to prevent charging of the support substrate at system level. | 04-09-2015 |
20160071758 | SILICON-ON-INSULATOR INTEGRATED CIRCUIT DEVICES WITH BODY CONTACT STRUCTURES AND METHODS FOR FABRICATING THE SAME - Silicon-on-insulator integrated circuits including body contact structures and methods for fabricating the same are disclosed. A method for fabricating a silicon-on-insulator integrated circuit includes filling a plurality of first and second shallow isolation trenches with an insulating material to form plurality of first and second shallow trench isolation (STI) structures, the plurality of second shallow isolation trenches having doped regions therebeneath, and forming a gate structure over the semiconductor layer that includes a first portion disposed over and parallel to at least two of the plurality of second STI structures and a second portion disposed in between the at least two of the plurality of second STI structures. The method further includes forming contact plugs to a body contact or gate region of the semiconductor layer. The body contact region includes a portion of the semiconductor layer between at least one of the plurality of first STI structures and at least one of the plurality of second STI structures. | 03-10-2016 |
Ser-Kiat Toh, Singapore SG
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20120225583 | CONNECTOR WITH TERMINAL RETENTION - A connector includes a shield that supports a housing. The housing includes a tongue that extends in a mating region defined by the shield. The tongue includes grooves (which may be on both sides of the shield) that support a plurality of terminals. The grooves each include a retention feature that secures the terminal in the groove while allowing a mating terminal to engage the terminals in the grooves without first engage the tongue. | 09-06-2012 |
Shi Wei Toh, Singapore SG
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20160133441 | ETCH ENHANCEMENT VIA CONTROLLED INTRODUCTION OF CHAMBER CONTAMINANTS - Embodiments of methods for removing materials from a substrate are provided herein. In some embodiments, a method of controlling contaminants in a process chamber may include flowing a first gas into the process chamber during an interval between completion of a process and start of a subsequent process in the process chamber to remove the contaminants from the process chamber; and flowing a second gas into the process chamber at a specific flow rate during the subsequent process to generate a same species as the contaminants. | 05-12-2016 |
Suey Li Toh, Singapore SG
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20100087061 | INTEGRATED CIRCUIT SYSTEM EMPLOYING BACKSIDE ENERGY SOURCE FOR ELECTRICAL CONTACT FORMATION - A method for manufacturing an integrated circuit system includes: providing a first material; forming a second material over a first side of the first material; and exposing a second side of the first material to an energy source to form an electrical contact at an interface of the first material and the second material. | 04-08-2010 |
Teck Kang Toh, Singapore SG
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20090037976 | System and Method for Securing a Network Session - A system comprises an end-user device including a browser and a security component capable of executing a security policy, the security policy to be downloaded from a website; and a website including a security policy downloadable to the security component. | 02-05-2009 |
20160142940 | INTELLIGENT MOBILE DATA OFFLOADING - A method for offloading mobile data may include determining a micro-cell performance parameter associated with a micro-cell of a mobile communication system. Further, the method may include determining whether to offload mobile data operations to a micro-cell access point that corresponds to the micro-cell based on the micro-cell performance parameter. | 05-19-2016 |
Tee Peng Toh, Singapore SG
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20080202403 | APPARATUS FOR ALTERING THE COURSE OF TRAVELLING OF A MOVING ARTICLE AND A METHOD THEREOF - The present invention relates to an apparatus for altering the course of a moving article and a method thereof comprising of a launching aircraft or surface craft to deploy said apparatus towards a moving article. The apparatus comprises of a driving mechanism ( | 08-28-2008 |
20090007832 | METHOD FOR CHANGING THE DIRECTION OF TRAVEL OF A WATERCRAFT AND APPARATUS THEREFORE - An apparatus for retarding and/or changing the direction of travel of a sailing vessel is disclosed. The apparatus includes a watercraft ( | 01-08-2009 |
20090013916 | Method of Intercepting and Yawing a Sailing Vessel With External Propulsion Means - A method for intercepting and yawing an errant sailing vessel is disclosed, wherein the vessel might have been hijacked or malfunctioned and in danger of colliding with an object. The method comprises dispatching a watercraft to approach the sailing vessel and secures itself to one side of the sailing vessel's hull. Preferably, a second watercraft is secured to the other side of the vessel's hull. At least one of the watercrafts is then operated to direct propulsion thrust to yaw the vessel in a desired direction. Preferably still, the first and second watercrafts are each secured respectively to the right and left sides of the vessel's hull proximate to the stem or bow end. The first (right side) watercraft then operates a fluid propulsion which thrust is directed away from the vessel's right side while the second (left side) watercraft's propulsion is on standby. As a result, the vessel is turned rightward or clockwise. Conversely, the first watercraft may be put on standby while the second watercraft's propulsion is operated such that the thrust is directed away from the vessel's left side, thereby causing the vessel to turn leftward or anti-clockwise. | 01-15-2009 |
20090020062 | Method of Intercepting and Yawing a Sailing Vessel - A method for intercepting and yawing an errant sailing vessel is disclosed, wherein the vessel might have been hijacked or malfunctioned and in danger of colliding with an object. The method comprises dispatching a pair of watercraft to approach said sailing vessel, providing a tow rope to be secured at one end to first watercraft and the other end to second watercraft. The tow rope is brought to extend between the first and second watercrafts over the hull of said sailing vessel. The first watercraft is then secured to one side of said sailing vessel's hull, while second watercraft pulls the tow rope away from the direction of sailing on the other side of said vessel's hull. In an alternative embodiment, the tow rope end held by the first watercraft may be secured directly to the vessel's hull, thus freeing the first watercraft to evacuate crew from the vessel to a safer distance. | 01-22-2009 |
Tiong Han Toh, Singapore SG
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20150065918 | PLACENTAL BLOOD EXTRACTION DEVICE - A placental blood extraction device comprises a receptacle for receiving a placenta with umbilical cord, the receptacle comprising a compartment arranged to receive the placenta; and a tube extending from the compartment for receiving the umbilical cord; wherein the receptacle is selectively removable from the device for receiving the placenta. The placental blood extraction device may comprise a pressure application device for applying pressure to a placenta, the pressure application device comprising a plurality of pressing members for applying pressure on a plurality of regions of the placenta. | 03-05-2015 |
20150231636 | Apparatuses, Systems and Methods for Providing Scalable Thermal Cyclers and Isolating Thermoelectric Devices - In one aspect, a thermal cycler system including a sample block and a thermoelectric device is disclosed. In various embodiments, the sample block has a first surface configured to receive a plurality of reaction vessels and an opposing second surface. In various embodiments the thermoelectric device is operably coupled to the second surface of the sample block. In various embodiments a thermal control unit is provided. In various embodiments the thermal control unit includes a computer processing unit. In various embodiments the thermal control unit includes an electrical current source. In various embodiments the thermal control unit also includes an electrical interface portion configured to connect the thermoelectric device with the electrical current source by way of an electrical cable. In various embodiments the thermal control unit is oriented in a different plane than the sample block and thermoelectric cooler. | 08-20-2015 |
Wee Kian Toh, Singapore SG
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20090309804 | Array Antenna for Wireless Communication and Method - A radiator for wireless communication applications is disclosed. The radiator comprises a first conductor formed along an axis, wherein the first conductor is substantially elongated. The radiator also has a second conductor and a third conductor extending substantially outwardly and centrally from the first conductor. The second conductor and the third conductor are substantially extended from opposite sides of the first conductor and substantially perpendicular to the first conductor The radiator further has a feeding point formed substantially at the centre of the first conductor and at least one radiating element connected to each of the second conductor and the third conductor More specifically, the second conductor, the third conductor and the at least one radiating element connected to each of the second conductor and the third conductor are substantially symmetrical about a plane, the axis being coincident with and extending along the plane. | 12-17-2009 |
Wei-De Toh, Singapore SG
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20140374949 | THREE-DIMENSIONAL PRINTING APPARATUS AND PRINGING METHOD THEREOF - A three-dimensional printing apparatus suitable for fabricating a three-dimensional object from a model of the three-dimensional object is provided. The three-dimensional printing apparatus includes a rotary base and a printing head. The rotary base has a carrying surface and is configured to rotate about a first axis and shift along the first axis. The printing head is disposed above the rotary base and configured to shift along a second axis perpendicular to the first axis for dispensing successive layers of building material onto the carrying surface. The successive layers of building material form the three-dimensional object. The shape of each layer of the building material is decided by the rotation of the rotary base about the first axis, the shifting of the rotary base along the first axis and the shifting of the printing head along the second axis. A printing method for the three-dimensional printing apparatus is also provided. | 12-25-2014 |
20150328837 | PRINTING HEAD MODULE - A printing head module includes a driving gear, a bi-directional motor, a first feeding module and a second feeding module. The bi-directional motor selectively drives the driving gear to rotate along a first direction and a second direction. The first feeding module disposed at a first side of the driving gear includes a first unidirectional gear and a first idler gear. The driving gear is engaged with the first unidirectional gear, and the first unidirectional gear unidirectionally drives the first idler gear to rotate. The second feeding module is disposed at a second side of the driving gear opposite to the first side, and includes a second unidirectional gear and a second idler gear, the driving gear is engaged with the second unidirectional gear to drive the second unidirectional gear to rotate, and the second unidirectional gear unidirectionally drive the second idler gear to rotate. | 11-19-2015 |
Weng Cheong Toh, Singapore SG
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20120222318 | EXTENDABLE UTENSIL AND METHOD OF MANUFACTURE - An extendable utensil comprises a base part and a body formed from sheet material having a first surface and a second and surface, wherein the body is arranged in a wrap around the base part in successive turns, and a point on the first surface at an end of a turn is fixed to a point on the second surface at a beginning of the turn. A method of manufacturing an extendable utensil is also disclosed. | 09-06-2012 |
Yeow T. Toh, Singapore SG
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20090091663 | RECEIVER FOR DIFFERENT TYPES OF RECEPTION SIGNALS - A receiver can handle different types of reception signals, such as, for example, TV and FM-radio signals. In the receiver, a mixer (MIX) mixes a reception signal with an oscillator signal (OOS) so as to obtain a mixer output signal (MOS), which comprises a frequency-shifted version of the reception signal. An intermediate frequency amplifier (IFAMP) applies an amplified mixer output signal (MOSA) to two different intermediate frequency filters: one for first type reception signals and another for second type reception signals. A switchable coupling section (DBTP, SWA) is coupled between the mixer (MIX) and the intermediate frequency amplifier (IFAMP). The switchable coupling section (DBTP, SWA) is switchable to a first state and a second state. In the first state, the mixer output signal (MOS) substantially reaches an input (IAD) of the intermediate frequency amplifier (IFAMP) via a first coupling path (DTBP). In the second state, the mixer output signal (MOS) substantially reaches the input (IAD) of the intermediate frequency amplifier (IFAMP) via a second coupling path (SWA). | 04-09-2009 |
20090215415 | SWITCH-ABLE BAND-TRACKING INPUT FILTER FOR COMBINATION TUNER - The present invention relates to a combination RF tuner capable of receiving signals from the FM radio band and from the TV band. Prior art combination tuners had to compromise in quality resulting in combination tuners that neither exhibited high-end FMnor TV-signal reception behavior. A combination RF tuner capable of optimal receiving an FM-radio signal type and a TV signal type, comprising a switch-able tuned input filter ( | 08-27-2009 |
Yeow Teng Toh, Singapore SG
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20090253456 | DUAL BAND RECEIVER WITH CONTROL MEANS FOR PREVENTING SIGNAL OVERLOADING - A portable dual band receiver (D), intended for equipping a mobile equipment, comprises a first antenna (AN | 10-08-2009 |
20100128453 | TUNER - A tuner is disclosed which overcomes a problem related to leakage currents within a tuner associated with increased miniaturization. The tuner includes an oscillator and a cover. The cover includes a barrier region, typically in the form of a slot or an air gap, which impedes the propagation of leakage currents, in the form of eddy currents induced from the oscillator, along the cover from the oscillator region to other components in the tuner, and in particular to the input or output connectors. | 05-27-2010 |
Yi Chin Toh, Singapore SG
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20080233607 | Cell Culture Device - The invention provides cell culture devices comprising a channel, the channel comprising one or more inlets and one or more outlets, and a cell retention chamber defined by an internal surface of the channel and a plurality of projections extending therefrom. The invention further provides methods of use relating to such cell culture devices. | 09-25-2008 |
20100136649 | Encapsulation of Cells in Biologic Compatible Scaffolds by Coacervation of Charged Polymers - This invention relates to a method for the encapsulation of cells in biologic compatible three dimensional scaffolds and the use of such cells encapsulated in a scaffold. The cells are embedded in a charged polymer that is complex coacervating with an oppositely charged polymer within biologic compatible scaffolds. The polymer complex embedding the cells is forming an ultra thin membrane on the surface of the three dimensional scaffold. | 06-03-2010 |
20150276711 | METHOD AND SYSTEM FOR IN VITRO DEVELOPMENTAL TOXICITY TESTING - A method and system of in vitro developmental toxicity testing comprising the steps of micropatterning an extracellular matrix; growing embryonic stem cells on the micropatterned extracellular matrix in the presence of mesoendermal induction and testing for change of the geometrical mesoendoderm structure in the presence or absence of a test compound wherein (1) a decrease in mesoendodermal differentiation and/or (2) a change in morphology of the geometrical mesoendoderm structure in the presence of the test compound compared to cells in the absence of the test compound indicates that the test compound is a developmental toxic agent. | 10-01-2015 |
20150284669 | METHODS OF CULTURING CELLS OR TISSUES AND DEVICES FOR CELL OR TISSUE CULTURE - A method of culturing cells or tissues is provided. The method comprises a) providing a support, wherein the support is an optical medium with a patterned surface; b) contacting the support with cells and a culture medium; and c) culturing the cells under suitable cultivation conditions. A device for cell or tissue culture comprising an optical medium, wherein a patterned surface of the optical medium forms a support upon which cells are cultivated, is also provided. | 10-08-2015 |
Yoke Khim Raymond Toh, Singapore SG
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20130227861 | NOVEL DAMPING ELEMENT IN SHOE SOLES - The present invention relates to a process for producing a shoe sole comprising a hybrid material made of a polyurethane foam as matrix material and of foamed particles of thermoplastic polyurethane by preparing an inlay of joined expanded particles (c′) of thermoplastic polyurethane and placing the joined expanded particles of thermoplastic polyurethane in a mould and embedding the inlay with a reaction mixture obtainable by mixing (a) polyisocyanates with (b) compounds having hydrogen atoms reactive toward isocyanates, and if appropriate, with (d) chain extenders and/or crosslinking agents, and with (e) catalysts, and with (f) blowing agents, and with (g) further additives and reacting the reaction mixture to give the shoe sole. The present invention further relates to shoe soles, obtainable by such a process. | 09-05-2013 |