Patent application number | Description | Published |
20080215923 | DESIGN STRUCTURE FOR TASK BASED DEBUGGER (TRANSACTION-EVENT -JOB-TRIGGER) - Disclosed is a design structure for an apparatus for a task based debugger (transaction-event-job-trigger). More specifically, an integrated event monitor for a SOC comprises functional cores each having a functional debug logic element. The cores are connected to an interconnect structure that links the functional debug logic elements. Each functional debug logic element is specifically dedicated to a function of its corresponding core, wherein the functional debug logic elements generate a table of function-specific system events. The system events are function-specific with respect to an associated core, wherein the system events include transaction events, controller events, processor events, interconnect structure arbiter events, interconnect interface core events, high speed serial link core events, and/or codec events. | 09-04-2008 |
20080282005 | METHOD AND PROCESSING UNIT FOR INTER-CHIP COMMUNICATION - The invention relates to an inter-chip communication protocol, based on a standard interface protocol, which is adapted to incorporate control, configuration and/or recovery information for computer chips, and the data encoded within communication packets of a communication layer above the physical layer of the interface protocol. | 11-13-2008 |
20080282072 | Executing Software Within Real-Time Hardware Constraints Using Functionally Programmable Branch Table - A computer system is disclosed which includes a CPU or microprocessor to drive tightly constrained hardware events. The system comprises a processor having a set of system inputs to drive a functionally programmable event, and a fast branch in the CPU including a state handler to execute instructions from the CPU to process the event. A queue in the CPU stores the events such that the non-pre-empted events are serviced in the order they are received. | 11-13-2008 |
20080285443 | METHOD FOR MONITORING CHANNEL EYE CHARACTERISTICS IN A HIGH-SPEED SERDES DATA LINK - A method is disclosed for tuning each channel of a high-speed SerDes cable link interface arranged in a configuration linking a local side physical layer to a remote side physical layer. The method includes initiating an operational state of high-speed SerDes cable link interface, identifying flow-control packet Op codes not cited for use by operational high-speed SerDes cable link interface, transmitting a flow control signal from the local side physical layer to the remote side physical layer to control the remote side physical layer to monitor the eye characteristics of the channels used by the local side physical layer to transfer data to the remote side physical layer, transferring eye characteristics acquired in the monitoring to the local side physical layer and processing the eye characteristics by the local side physical layer to generate equalization setting adjustments. | 11-20-2008 |
20080285453 | METHOD FOR MONITORING BER IN AN INFINIBAND ENVIRONMENT - A method is disclosed for tuning each channel of a high-speed SerDes cable link interface arranged in a configuration linking a local side physical layer to a remote side physical layer. The method includes initiating an operational state of high-speed SerDes cable link interface, identifying flow-control packet Op codes not cited for use by operational high-speed SerDes cable link interface, transmitting a flow control signal from the local side physical layer to the remote side physical layer to control the remote side physical layer to monitor the bit error rate (BER) of the channels used by the local side physical layer to transfer data to the remote side physical layer, monitoring the BER in the channels used for data transfer, transferring BER data acquired in the monitoring to the local side physical layer and processing the BER data by the local side physical layer to generate equalization setting adjustments. | 11-20-2008 |
20090021085 | DESIGN STRUCTURES, METHOD AND SYSTEMS OF POWERING ON INTEGRATED CIRCUIT - Design structures, method and systems of powering on an integrated circuit (IC) are disclosed. In one embodiment, the system includes a region in the IC including functional logic, a temperature sensor for sensing a temperature in the region when the IC is powered up and a heating element therefor; a processing unit including: a comparator for comparing the temperature against a predetermined temperature value, a controller, which in the case that the temperature is below the predetermined temperature value, delays functional operation of the IC and controls heating of the region of the IC, and a monitor for monitoring the temperature in the region; and wherein the controller, in the case that the temperature rises above the predetermined temperature value, ceases the heating and initiates functional operation of the IC. | 01-22-2009 |
20090022203 | METHOD AND SYSTEMS OF POWERING ON INTEGRATED CIRCUIT - Method and systems of powering on an integrated circuit (IC) are disclosed. In one embodiment, the system includes a region in the IC including functional logic, a temperature sensor for sensing a temperature in the region when the IC is powered up and a heating element therefor; a processing unit including: a comparator for comparing the temperature against a predetermined temperature value, a controller, which in the case that the temperature is below the predetermined temperature value, delays functional operation of the IC and controls heating of the region of the IC, and a monitor for monitoring the temperature in the region; and wherein the controller, in the case that the temperature rises above the predetermined temperature value, ceases the heating and initiates functional operation of the IC. | 01-22-2009 |
20090024972 | STRUCTURES OF POWERING ON INTEGRATED CIRCUIT - Design structures, method and systems of powering on an integrated circuit (IC) are disclosed. In one embodiment, the system includes a region in the IC including functional logic, a temperature sensor for sensing a temperature in the region when the IC is powered up and a heating element therefor; a processing unit including: a comparator for comparing the temperature against a predetermined temperature value, a controller, which in the case that the temperature is below the predetermined temperature value, delays functional operation of the IC and controls heating of the region of the IC, and a monitor for monitoring the temperature in the region; and wherein the controller, in the case that the temperature rises above the predetermined temperature value, ceases the heating and initiates functional operation of the IC. | 01-22-2009 |
20090044054 | DYNAMIC CRITICAL PATH DETECTOR FOR DIGITAL LOGIC CIRCUIT PATHS - Method for correcting timing failures in an integrated circuit and device for monitoring an integrated circuit. The method includes placing a first and second latch near a critical path. The first latch has an input comprising a data value on the critical path. The method further includes generating a delayed data value from the data value, latching the delayed data value in the second latch, comparing the data value with the delayed data value to determine whether the critical path comprises a timing failure condition, and executing a predetermined corrective measure for the critical path. | 02-12-2009 |
20090044160 | DYNAMIC CRITICAL PATH DETECTOR FOR DIGITAL LOGIC CIRCUIT PATHS - Method for correcting timing failures in an integrated circuit and device for monitoring an integrated circuit. The method includes placing a first and second latch near a critical path. The first latch has an input comprising a data value on the critical path. The method further includes generating a delayed data value from the data value, latching the delayed data value in the second latch, comparing the data value with the delayed data value to determine whether the critical path comprises a timing failure condition, and executing a predetermined corrective measure for the critical path. The invention is also directed to a design structure on which a circuit resides. | 02-12-2009 |
20090091351 | CHIP IDENTIFICATION SYSTEM AND METHOD - Disclosed are embodiments of on-chip identification circuitry. In one embodiment, pairs of conductors (e.g., metal pads, vias, lines) are formed within one or more metallization layers. The distance between the conductors in each pair is predetermined so that, given known across chip line variations, there is a random chance (i.e., an approximately 50/50 chance) of a short. In another embodiment different masks form first conductors (e.g., metal lines separated by varying distances and having different widths) and second conductors (e.g., metal vias separated by varying distances and having equal widths). The first and second conductors alternate across the chip. Due to the different separation distances and widths of the first conductors, the different separation distances of the second conductors and, random mask alignment variations, each first conductor can short to up to two second conductors. In each embodiment the resulting pattern of shorts and opens, can be used as an on-chip identifier or private key. | 04-09-2009 |
20090094566 | DESIGN STRUCTURE FOR CHIP IDENTIFICATION SYSTEM - Disclosed is a design structure for an on-chip identification circuitry. In one embodiment, pairs of conductors (e.g., metal pads, vias, lines) are formed within one or more metallization layers. The distance between the conductors in each pair is predetermined so that, given known across chip line variations, there is a random chance (i.e., an approximately 50/50 chance) of a short. In another embodiment different masks form first conductors (e.g., metal lines separated by varying distances and having different widths) and second conductors (e.g., metal vias separated by varying distances and having equal widths). The first and second conductors alternate across the chip. Due to the different separation distances and widths of the first conductors, the different separation distances of the second conductors and, random mask alignment variations, each first conductor can short to up to two second conductors. In each embodiment the resulting pattern of shorts and opens, can be used as an on-chip identifier or private key. | 04-09-2009 |
20090132732 | UNIVERSAL PERIPHERAL PROCESSOR SYSTEM FOR SOC ENVIRONMENTS ON AN INTEGRATED CIRCUIT - A universal peripheral processor architecture on an integrated circuit (IC) includes first and second data buses coupled to interface logic devices for enabling communication between the first and second data buses including enabling interface of multiple signaling protocols. One or more processors communicate with the first and second data buses to manage control functions on the IC. A data path enables transfer of data between the first and second data buses, and communicates with data storage devices. A data control path enables communication between the data storage devices and the processors. | 05-21-2009 |
20090132747 | STRUCTURE FOR UNIVERSAL PERIPHERAL PROCESSOR SYSTEM FOR SOC ENVIRONMENTS ON AN INTEGRATED CIRCUIT - A design structure including universal peripheral processor architecture on an integrated circuit (IC) includes first and second data buses coupled to interface logic devices for enabling communication between the first and second data buses including enabling interface of multiple signaling protocols. One or more processors communicate with the first and second data buses to manage control functions on the IC. A data path enables transfer of data between the first and second data buses, and communicates with data storage devices. A data control path enables communication between the data storage devices and the processors. | 05-21-2009 |
20090164865 | APPARATUS FOR PIPELINED CYCLIC REDUNDANCY CHECK CIRCUIT WITH MULTIPLE INTERMEDIATE OUTPUTS - A CRC redundancy calculation circuit and a design structure including the circuit embodied in a machine readable medium are presented. The CRC redundancy calculation circuit is pipelined to run at high frequencies and configured to operate on an arbitrary multiple of the base granularity of the data packet. Additionally, the CRC redundancy calculation circuit provides the same multiple of outputs that provide intermediary output remainder values. Thus, for example, a circuit which processes 24 bytes of packet data per cycle and which the packets have a 4 byte granularity, the CRC redundancy calculation circuit provides 6 output remainder values, one for each 4 byte slice of data. | 06-25-2009 |
20090245110 | SYSTEM AND METHOD FOR IMPROVING EQUALIZATION IN A HIGH SPEED SERDES ENVIRONMENT - A method and accompanying system are disclosed for tuning each channel of a high-speed SerDes link interface arranged in a configuration linking a local side to a remote side. The method includes transmitting a flow control packets from the local side to the remote side to change remote side transmission characteristics in a link channel; monitoring signal eye characteristics in the link channel; transferring additional flow control packets to adjust the remote side transmission characteristics; and processing the signal eye characteristics at the local side to generate the remote side transmission characteristics for the link channel. | 10-01-2009 |
20090257514 | SYSTEM AND METHOD FOR IMPROVING EQUALIZATION IN A HIGH SPEED SERDES ENVIRONMENT - A method and accompanying system are disclosed for tuning each channel of a high-speed SerDes link interface arranged in a configuration linking a local side to a remote side. The method includes transmitting a flow control packets from the local side to the remote side to change remote side transmission characteristics in a link channel; monitoring the bit error rate (BER) in the link channel; transferring additional flow control packets to adjust the remote side transmission characteristics; and processing the BER data at the local side to generate the remote side transmission characteristics for the link channel. | 10-15-2009 |
20090276178 | WARRANTY MONITORING AND ENFORCEMENT FOR INTEGRATED CIRCUIT AND RELATED DESIGN STRUCTURE - An integrated circuit (IC) including a warranty and enforcement system, and a related design structure and HDL design structure are disclosed. In one embodiment, an IC includes a parameter obtainer for obtaining a value of a parameter of the IC; a warranty data storage system for storing warranty limit data regarding the IC; a comparator for determining whether a warranty limit has been exceeded by comparing the value of the parameter to a corresponding warranty limit; and an action taker for taking a prescribed action in response to the warranty limit being exceeded. | 11-05-2009 |
20090276232 | WARRANTY MONITORING AND ENFORCEMENT FOR INTEGRATED CIRCUIT - An integrated circuit (IC) including a warranty and enforcement system and a method are disclosed. In one embodiment, an IC includes a parameter obtainer for obtaining a value of a parameter of the IC; a warranty data storage system for storing warranty limit data regarding the IC; a comparator for determining whether a warranty limit has been exceeded by comparing the value of the parameter to a corresponding warranty limit; and an action taker for taking a prescribed action in response to the warranty limit being exceeded. | 11-05-2009 |
20090291533 | System-On-Chip (SOC), Design Structure and Method - Disclosed is a system-on-chip (SOC) structure that allows for automated integration of multiple intellectual cores. The SOC structure incorporates a plurality of cells connected to a common bus on a chip. Each cell incorporates a functional core and an automated integration unit (AIU) connected to the functional core. Each AIU communicates integration information for its functional core over the common bus to the AIUs in the other cells. The exchange of information between the AIUs is controlled either by the integration units themselves or by a controller. Based on received integration information, each AIU can automatically make any required configuration adjustments for integration. Furthermore, based on this exchange of information, the functional cores can interact, as necessary, during SOC operation. Also disclosed are an associated method of forming such a SOC structure and a design structure for such an SOC structure. | 11-26-2009 |
20090292828 | System-On-Chip (SOC), Design Structure and Method - Disclosed is a system-on-chip (SOC) structure that allows for automated integration of multiple intellectual cores. The SOC structure incorporates a plurality of cells connected to a common bus on a chip. Each cell incorporates a functional core and an automated integration unit (AIU) connected to the functional core. Each AIU communicates integration information for its functional core over the common bus to the AIUs in the other cells. The exchange of information between the AIUs is controlled either by the integration units themselves or by a controller. Based on received integration information, each AIU can automatically make any required configuration adjustments for integration. Furthermore, based on this exchange of information, the functional cores can interact, as necessary, during SOC operation. Also disclosed are an associated method of forming such a SOC structure and a design structure for such an SOC structure. | 11-26-2009 |
20100201377 | Critical Path Redundant Logic for Mitigation of Hardware Across Chip Variation - Cross-die connection structure and method for a die or chip includes buffer elements having a buffer driver and bypass, and control lines coupled to the buffer elements in order to select one of the buffer driver and bypass for each respective buffer element. A logic network is arranged with the buffer elements to form functional paths, a test unit is structured and arranged to test the functional paths and to be coupled to the control lines, and a configuration storage register to set the selected one of the buffer driver and bypass for each passing functional path. | 08-12-2010 |
20130335120 | SOURCE SERIES TERMINATED DRIVER CIRCUIT WITH PROGRAMMABLE OUTPUT RESISTANCE, AMPLITUDE REDUCTION, AND EQUALIZATION - A source-series terminated (‘SST’) driver circuit that includes: one or more data signal inputs; one or more control signal inputs; a driver output; and a plurality of driver cells, the driver cells coupled in parallel to one another, outputs of the driver cells coupled together to form the driver output of the SST driver circuit, where output resistance of the SST driver circuit varies in dependence upon activation of one or more of the parallel driver cells, activation of each driver cell controlled by control signals received at the control signal inputs. | 12-19-2013 |
20140166461 | THREE-DIMENSIONAL INTER-CHIP CONTACT THROUGH VERTICAL DISPLACEMENT MEMS - An electrically conducting, vertically displacing microelectromechanical system (MEMS) is formed on a first integrated circuit chip. The first integrated circuit chip is physically connected to a three-dimensional packaging structure. The three-dimensional packaging structure maintains a fixed distance between the first integrated circuit chip and a second integrated circuit chip. A control circuit is operatively connected to the MEMS. The control circuit directs movement of the MEMS between a first position and a second position. The MEMS makes contact with a contact pad on the second integrated circuit chip when it is in the second position forming a conductive path and providing electrical communication between the first integrated circuit chip and the second integrated circuit chip. The MEMS avoids making contact with the contact pad on the second integrated circuit chip when it is in the first position. | 06-19-2014 |
20140254650 | ADAPTABLE RECEIVER DETECTION - Methods and apparatuses for adaptable receiver detection are provided. Embodiments include providing, by receiver detection circuitry at a transmitter coupled to a communication link, a voltage to the communication link; determining, by the receiver detection circuitry, a rise time corresponding to a rising edge change of the voltage on the communication link; determining, by the receiver detection circuitry, a fall time corresponding to a falling edge change of the voltage on the communication link; and determining, by the receiver detection circuitry, whether the rise time and the fall time are consistent with the transmitter being coupled through the communication link to a remote receiver. | 09-11-2014 |
20150077173 | THREE-DIMENSIONAL CHIP STACK FOR SELF-POWERED INTEGRATED CIRCUIT - Structures and methods for self-powered devices are disclosed herein. Specifically, disclosed herein is a stacked, three-dimensional integrated circuit including a power generation die including a power source. The integrated circuit also includes a functional system die including one or more functional components that are powered by power generated by the power source. The power generation die and the functional system die are stacked in a three-dimensional structure. | 03-19-2015 |