Tobias Gemmeke
Tobias Gemmeke, Stutensee DE
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20080276140 | SEMICONDUCTOR CHIP WITH A PLURALITY OF SCANNABLE STORAGE ELEMENTS AND A METHOD FOR SCANNING STORAGE ELEMENTS ON A SEMICONDUCTOR CHIP - A semiconductor chip subdivided into power domains, at least one of the power domains is separately activated or deactivated and at least a part of the scannable storage elements are interconnected to one or more scan chains. At least one scan chain is serially subdivided into scan chain portions and the scan chain portion is arranged within one of the power domains. For at least one scan chain portion a bypass line is provided for passing by scan data and at least one select unit is provided for selecting between the bypass line and the corresponding scan chain portion in dependence of the activated or deactivated state of the corresponding power domains. | 11-06-2008 |
20080288901 | Formally deriving a minimal clock-gating scheme - The present invention provides a fully automatic method for obtaining a circuit having minimized power consumption due to clock-gating. A circuit design to be optimized is modified to a reduced power modified design and associated with a clock gating scheme. Verification tools compare the modified design with the original design to a predetermined trigger-events to determine if the modified design can be used. Further modifications may be made iteratively until an optimal design is achieved. | 11-20-2008 |
20090115504 | CIRCUIT DESIGN METHODOLOGY TO REDUCE LEAKAGE POWER - A three stage circuit according to the invention comprises a data input, a data output, a control input, two voltage supply inputs. The first stage is electrically connected to the data input and control input and is defined by a combinatorial circuitry with two outputs. The second stage is defined by at least two transistors connected in series between the two voltage supply inputs with their inputs electrically connected to the respective outputs of the first stage and with a common output such that in connection with the first stage they operate as a tri-state gate. The third stage of that three stage circuit is electrically connected to the control input and the common output of the second stage. The three stage circuit is switched to a low leakage state by a control signal feed via the control input and setting the two transistors in their off state resulting in a second stage with a floating common output filtered by the third stage via the control signal actively driven the data output to a specific logic value. | 05-07-2009 |
20090135961 | System and Method for Scanning Sequential Logic Elements - System and Method for Scanning Sequential Logic Elements A digital system and method for scanning sequential logic elements are disclosed. The digital system may comprise a plurality of sequential logic elements subdivided into power domains, wherein at least one of the power domains is power gated; a scan chain configured for processing a scan data sequence; a scan enable switch configured for controlling a scan mode; and at least one shadow engine, wherein the at least one shadow engine comprises a control circuit. At least some of the power domains may be interconnected to the scan chain with the scan enable switch, and the scan enable switch may control the scan mode by asserting a scan enable signal. The at least one power gated power domain with one or more sequential logic elements to be power gated may be bypassed via the at least one shadow engine. | 05-28-2009 |
20100199074 | INSTRUCTION SET ARCHITECTURE WITH DECOMPOSING OPERANDS - Instead of having a processor with an instruction set architecture (ISA) that includes fixed architected operands, an improved processor supports additional characteristic bits for computing instructions (e.g., a multiply-add, load/store instructions). Such additional bits for the certain instructions influence the processing of these instructions by the processor. Also, a new instruction is introduced for further usage of the proposed method. Typically these additional characteristic bits as well as the instruction can be automatically generated by compilers to provide relatively well-suited instruction sequences for the processor. | 08-05-2010 |
Tobias Gemmeke, Santa Clara, CA US
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20090249035 | MULTI-CYCLE REGISTER FILE BYPASS - A method of reducing latency in instruction processing in a system, includes calculating a result of a first execution unit, storing the result of the first execution unit in a register file, forwarding the result of the first execution unit, through the bypass unit, to a second execution unit, the second execution unit conducting an instruction dependent on the result, forwarding the result of the first execution unit, from the bypass unit, to a third execution unit, without accessing the register file, the third execution unit conducting an instruction dependent on the result, wherein the execution units can extract the result of the first execution unit through the bypass unit until the new result is calculated, wherein after the new result is calculated, the execution units can access the result of the first execution unit through the register file. | 10-01-2009 |
20100057825 | METHOD AND ELECTRONIC COMPUTING CIRCUIT FOR OPERAND WIDTH REDUCTION FOR A MODULO ADDER FOLLOWED BY SATURATION CONCURRENT MESSAGE PROCESSING - A method for operand width reduction is described, wherein two N-bit input operands (A, B) of a bit width of N are processed and two M-bit output operands (A′, B′) of a reduced bit width of M are generated in a way, that a post-processing comprising an M-bit adder function followed by saturation to M bits performed on said two M-bit output operands (A′, B′) provides an M-bit result equal to an M-bit result of an N-bit modulo adder function of the two N-bit input operands (A, B), followed by a saturation to M bits. Further an electronic computing circuit ( | 03-04-2010 |
Tobias Gemmeke, Boeblingen DE
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20080209287 | Method and Apparatus for Performing Equivalence Checking on Circuit Designs Having Differing Clocking and Latching Schemes - A method for performing equivalence checking on logic circuit designs is disclosed. Within a composite netlist of an original version and a modified version of a logic circuit design, all level-sensitive sequential elements sensitized by a clock=0 are converted into buffers, and all level-sensitive sequential elements sensitized by a clock=1 are converted into level-sensitive registers. A subset of edge-sensitive sequential elements are selectively transformed into level-sensitive sequential elements by removing edge detection logic from the subset of the edge-sensitive sequential elements. A clock to the resulting sequential elements is then set to a logical “1” to verify the sequential equivalence of the transformed netlist. | 08-28-2008 |
20130181743 | Binary Logic Unit and Method to Operate a Binary Logic Unit - A binary logic unit to apply any Boolean operation on two input signals (v | 07-18-2013 |
Tobias Gemmeke, Leuven BE
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20130300463 | Method and Apparatus for Monitoring Timing of Critical Paths - An apparatus for monitoring timing of a plurality of critical paths of a functional circuit includes a plurality of canary circuits, each configured to be coupled to a critical path of a functional circuit for detecting and outputting critical timing events. Each canary circuit includes an adjustable delay element and an analyser circuit for receiving a count of the critical timing event output from at least one of the plurality of canary circuits for a predetermined time interval for a plurality of delay values of the adjustable delay elements and for determining a probability distribution of critical timing events of the at least one of the plurality of critical paths for the predetermined time interval for the plurality of delay values. | 11-14-2013 |
Tobias Gemmeke, Straelen DE
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20150309753 | Memory Control System for a Non-Volatile Memory and Control Method - A memory control system for controlling read and write operations of a non-volatile memory, wherein the memory control system comprises a memory controller that is adapted to implement a write operation for writing at least one block of data to the memory as a sequence of memory write and validation cycles for part of all of the data. In one example, the number of cycles is a function of the amount of successfully written data per cycle and is thus variable in dependence on the success of the data writing. The system also includes a power management unit, which is adapted to authorize or prevent the memory controller from conducting the write operation at the level of the write cycles thereby to control the timing of power consumption resulting from the cycles of the write operation. | 10-29-2015 |