Patent application number | Description | Published |
20100106875 | Technique for communicating interrupts in a computer system - A technique to enable efficient interrupt communication within a computer system. In one embodiment, an advanced programmable interrupt controller (APIC) is interfaced via a set of of bits within an APIC interface register using various interface instructions or operations, without using memory-mapped input/output (MMIO). | 04-29-2010 |
20100241825 | Opportunistic Transmission Of Software State Information Within A Link Based Computing System - A method is described that involves determining that software state information of program code is to be made visible to a monitoring system. The method also involves initiating the writing of the software state information into a register. The method also involves waiting for the software state information to be placed onto a link within a link based computing system. | 09-23-2010 |
20120124264 | TECHNIQUE FOR COMMUNICATING INTERRUPTS IN A COMPUTER SYSTEM - A technique to enable efficient interrupt communication within a computer system. In one embodiment, an advanced programmable interrupt controller (APlC) is interfaced via a set of bits within an APIC interface register using various interface instructions or operations, without using memory-mapped input/output (MMIO). | 05-17-2012 |
20140136746 | TECHNIQUE FOR COMMUNICATING INTERRUPTS IN A COMPUTER SYSTEM - A technique to enable efficient interrupt communication within a computer system. In one embodiment, an advanced programmable interrupt controller (APIC) is interfaced via a set of bits within an APIC interface register using various interface instructions or operations, without using memory-mapped input/output (MMIO). | 05-15-2014 |
Patent application number | Description | Published |
20090070510 | PROCESSOR SELECTION FOR AN INTERRUPT BASED ON WILLINGNESS TO ACCEPT THE INTERRUPT AND ON PRIORITY - In some embodiments, an apparatus includes processors, signal storage circuitry, and processor selection logic. The signal storage circuitry is to hold willingness indication signals each indicative of a willingness level of an associated one of the processors to receive an interrupt and to hold priority indication signals each indicative of a processor priority level of an associated one of the processors, wherein there are multiple possible willingness levels and multiple possible processor priority levels. The processor selection logic is to select one of the processors to receive an interrupt based at least on the willingness indication signals. Other embodiments are described. | 03-12-2009 |
20090070511 | PROCESSOR SELECTION FOR AN INTERRUPT IDENTIFYING A PROCESSOR CLUSTER - In some embodiments, an apparatus includes processor selection logic to receive logical destination identification numbers that are associated with interrupts each having a processor cluster identification number to identify a cluster of processors to which the interrupts are directed. The logical destination identification numbers are each to identify which processors within the identified cluster of processors are available to receive the corresponding one of interrupts. The processor selection logic is to select one of the available processors to receive the interrupt, and the selected one of the available processors is identified through a relative position of a corresponding bit in the logical destination identification numbers. Other embodiments are described. | 03-12-2009 |
20090070551 | CREATION OF LOGICAL APIC ID WITH CLUSTER ID AND INTRA-CLUSTER ID - In some embodiments, an apparatus includes logical interrupt identification number creation logic to receive physical processor identification numbers and create logical processor identification numbers through using the physical processor identification numbers. Each of the logical processor identification numbers corresponds to one of the physical processor identification numbers, and the logical processor identification numbers each include a processor cluster identification number and an intra-cluster identification number. The processor cluster identification numbers are each formed to include a group of bits from the corresponding physical processor identification number shifted in position, and the intra-cluster identification numbers are each formed in response to values of others of the bits of the corresponding physical processor identification number. Other embodiments are described. | 03-12-2009 |
20100017458 | TECHNIQUES FOR BROADCASTING MESSAGES ON A POINT-TO-POINT INTERCONNECT - Techniques to broadcast a message across a point-to-point network are described. More particularly, some embodiments of the invention relate to broadcasting messages between electronics components within a point-to-point interconnect. Other embodiments are also disclosed. | 01-21-2010 |
20120166882 | METHODS AND TOOLS TO DEBUG COMPLEX MULTI-CORE, MULTI-SOCKET QPI BASED SYSTEM - Methods and apparatus relating to debugging complex multi-core and/or multi-socket systems are described. In one embodiment, a debug controller detects an event corresponding to a failure in a computing system and transmits data corresponding to the event to one of the other debug controllers in the system. Other embodiments are also disclosed and claimed. | 06-28-2012 |