Patent application number | Description | Published |
20080277745 | FIN FILLED EFFECT TRANSISTOR AND METHOD OF FORMING THE SAME - A fin field effect transistor and method of forming the same. The fin field effect transistor comprises a semiconductor substrate having a fin structure and between two trenches with top portions and bottom portions. The fin field effect transistor further comprises shallow trench isolations formed in the bottom portions of the trenches and a gate electrode over the fin structure and the shallow trench isolation, wherein the gate electrode is substantially perpendicular to the fin structure. The fin field effect transistor further comprises a gate dielectric layer along sidewalls of the fin structure and source/drain electrode formed in the fin structure. | 11-13-2008 |
20100055897 | WET CLEANING STRIPPING OF ETCH RESIDUE AFTER TRENCH AND VIA OPENING FORMATION IN DUAL DAMASCENE PROCESS - After trench line pattern openings and via pattern openings are formed in a inter-metal dielectric insulation layer of a semiconductor wafer using trench-first dual damascene process, the wafer is wet cleaned in a single step wet clean process using a novel wet clean solvent composition. The wet clean solvent effectively cleans the dry etch residue from the plasma etching of the dual damascene openings, etches back the TiN hard mask layer along the dual damascene openings and forms a recessed surface at the conductor metal from layer below exposed at the bottom of the via openings of the dual damascene openings. | 03-04-2010 |
20130157462 | METHOD OF FORMING PATTERN FOR SEMICONDUCTOR DEVICE - The present disclosure provides a method including providing a semiconductor substrate and forming a first layer and a second layer on the semiconductor substrate. The first layer is patterned to provide a first element, a second element, and a space interposing the first and second elements. Spacer elements are then formed on the sidewalls on the first and second elements of the first layer. Subsequently, the second layer is etched using the spacer elements and the first and second elements as a masking element. | 06-20-2013 |
20130196481 | METHOD OF PATTERNING FOR A SEMICONDUCTOR DEVICE - A method that includes forming a masking element on a semiconductor substrate and overlying a defined space. A first feature and a second feature are each formed on the semiconductor substrate. The space interposes the first and second features and extends from a first end of the first feature to a first end of the second feature. A third feature is then formed adjacent and substantially parallel the first and second features. The third feature extends at least from the first end of the first feature to the first end of the second feature. | 08-01-2013 |
20140203445 | MITIGATING PATTERN COLLAPSE - One or more techniques or systems for mitigating pattern collapse are provided herein. For example, a semiconductor structure for mitigating pattern collapse is formed. In some embodiments, the semiconductor structure includes an extreme low-k (ELK) dielectric region associated with a via or a metal line. For example, a first metal line portion and a second metal line portion are associated with a first lateral location and a second lateral location, respectively. In some embodiments, the first portion is formed based on a first stage of patterning and the second portion is formed based on a second stage of patterning. In this manner, pattern collapse associated with the semiconductor structure is mitigated, for example. | 07-24-2014 |
20140252625 | Method of Preventing a Pattern Collapse - A device includes a substrate and at least three conducting features embedded into the substrate. Each conducting feature includes a top width x and a bottom width y, such that a top and bottom width (x1, y1) of a first conducting feature has a dimension of (x1y2), and a top and bottom width (x3, y3) of a third conducting feature has a dimension of (x3>y3). The device also includes a gap structure isolating the first and second conducting features. The gap structure can include such things as air or dielectric. | 09-11-2014 |
20140252636 | INTERCONNECT STRUCTURE AND METHOD OF FORMING THE SAME - An interconnect structure and a method of forming an interconnect structure are disclosed. The interconnect structure includes a lower etch stop layer (ESL); a middle low-k (LK) dielectric layer over the lower ESL; a supporting layer over the middle LK dielectric layer; an upper LK dielectric layer over the supporting layer; an upper conductive feature in the upper LK dielectric layer, wherein the upper conductive feature is through the supporting layer; a gap along an interface of the upper conductive feature and the upper LK dielectric layer; and an upper ESL over the upper LK dielectric layer, the upper conductive feature, and the gap. | 09-11-2014 |
20140252648 | INTERCONNECT STRUCTURE AND METHOD OF FORMING THE SAME - An interconnect structure and a method of forming an interconnect structure are disclosed. The interconnect structure includes a first metal line and a second metal line over a substrate; a portion of a first low-k (LK) dielectric layer between the first metal line and the second metal line; and a second LK dielectric layer over the portion of the first LK dielectric layer. A top surface of the second LK dielectric layer is substantially coplanar with a top surface of the first metal line or the second metal line, and a thickness of the second LK dielectric layer is less than a thickness of the first metal line or a thickness of the second metal line. | 09-11-2014 |
20140256155 | Cleaning Solution for Preventing Pattern Collapse - A chemical solution for use in cleaning a patterned substrate includes water, from approximate 0.01 to 99.98 percent by weight; hydrogen peroxide, from 0 to 30 percent by weight; a pH buffering agent, from approximate 0.01 to 50 percent by weight; a metal chelating agent, from approximate 0 to 10 percent by weight; and a compound for lowering a surface tension of the combination of water, hydrogen peroxide, pH buffering agent, and metal chelating agent. Examples of the compound include an organic solvent, from approximate 0 to 95 percent by weight, or a non-ionic surfactant agent, from approximate 0 to 2 percent by weight. | 09-11-2014 |
20140264873 | Interconnection Structure And Method For Semiconductor Device - A semiconductor device is disclosed. The device includes a substrate, a first dielectric layer disposed over the substrate and a metal structure disposed in the first dielectric layer and below a surface of the first dielectric layer. The metal structure has a such shape that having an upper portion with a first width and a lower portion with a second width. The second width is substantially larger than the first width. The semiconductor device also includes a sub-structure of a second dielectric positioned between the upper portion of the metal structure and the first dielectric layer. | 09-18-2014 |
20140264902 | Novel Patterning Approach for Improved Via Landing Profile - The present disclosure is directed to a semiconductor structure and a method of manufacturing a semiconductor structure in which a spacer element is formed adjacent to a metal body embedded in a first dielectric layer of a first interconnect layer. A via which is misaligned relative to an edge of the metal body is formed in a second dielectric material in second interconnect layer disposed over the first interconnect layer and filled with a conductive material which is electrically coupled to the metal body. The method allows for formation of an interconnect structure without encountering the various problems presented by via substructure defects in the dielectric material of the first interconnect layer, as well as eliminating conventional gap-fill metallization issues. | 09-18-2014 |
20140264903 | INTERCONNECT STRUCTURE AND METHOD OF FORMING THE SAME - An interconnect structure and a method of forming an interconnect structure are disclosed. The interconnect structure includes a lower etch stop layer (ESL); an upper low-k (LK) dielectric layer over the lower ESL; a first conductive feature in the upper LK dielectric layer, wherein the first conductive feature has a first metal line and a dummy via contiguous with the first metal line, the dummy via extending through the lower ESL; a first gap along an interface of the first conductive feature and the upper LK dielectric layer; and an upper ESL over the upper LK dielectric layer, the first conductive feature, and the first gap. | 09-18-2014 |
20140264926 | Method and Apparatus for Back End of Line Semiconductor Device Processing - A via opening comprising an etch stop layer (ESL) opening and methods of forming the same are provided which can be used in the back end of line (BEOL) process of IC fabrication. A metal feature is provided with a first part within a dielectric layer and with a top surface. An ESL is formed with a bottom surface of the ESL above and in contact with the dielectric layer, and a top surface of the ESL above the bottom surface of the ESL. An opening at the ESL is formed exposing the top surface of the metal feature; wherein the opening at the ESL has a bottom edge of the opening above the bottom surface of the ESL, a first sidewall of the opening at a first side of the metal feature, and a second sidewall of the opening at a second side of the metal feature. | 09-18-2014 |
20140264932 | Patterning Approach to Reduce Via to Via Minimum Spacing - A method for patterning vias in a chip comprises forming a photomask layer including a gap on a patterned hardmask layer including a plurality of trenches and in contact with a uniform layer on a substrate, wherein the gap overlaps with two or more of the trenches. The method further comprises exposing a portion of the uniform layer under the gap using a photo exposure process, etching the exposed portion of the uniform layer with the photomask layer to obtain a plurality of vias extended partially through the substrate, and further etching the vias to obtain corresponding through-substrate vias. Another method comprises patterning a plurality of vias in a plurality of trenches of a hardmask layer on a substrate using a single photo exposure step and a photomask comprising a single gap that overlaps with the trenches. | 09-18-2014 |
20150137265 | FIN FIELD EFFECT TRANSISTOR AND METHOD OF FORMING THE SAME - A fin field effect transistor and method of forming the same. The fin field effect transistor includes a semiconductor substrate having a fin structure and between two trenches with top portions and bottom portions. The fin field effect transistor further includes shallow trench isolations formed in the bottom portions of the trenches and a gate electrode over the fin structure and the shallow trench isolation, wherein the gate electrode is substantially perpendicular to the fin structure. The fin field effect transistor further includes a gate dielectric layer along sidewalls of the fin structure and source/drain electrode formed in the fin structure. | 05-21-2015 |
20150162262 | Interconnect Structure for Semiconductor Devices - An interconnect and a method of forming an interconnect for a semiconductor device is provided. Conductive lines having different widths are formed. Wider conductive lines are used where the design includes an overlying via, and narrower lines are used in which an overlying via is not included. An overlying dielectric layer is formed and trenches and vias are formed extending through the overlying dielectric layer to the wider conductive lines. Voids or air gaps may be formed adjacent select conductive lines, such as the narrower lines. | 06-11-2015 |
20150187591 | METHOD OF FORMING PATTERN FOR SEMICONDUCTOR DEVICE - The present disclosure provides a method including providing a semiconductor substrate and forming a first layer and a second layer on the semiconductor substrate. The first layer is patterned to provide a first element, a second element, and a space interposing the first and second elements. Spacer elements are then formed on the sidewalls on the first and second elements of the first layer. Subsequently, the second layer is etched using the spacer elements and the first and second elements as a masking element. | 07-02-2015 |
Patent application number | Description | Published |
20110193089 | PIXEL STRUCTURE, METHOD OF FABRICATING THE SAME, AND METHOD OF FABRICATING ELECTRONIC DEVICE - A pixel structure including a substrate, a gate, an insulation layer, a metal oxide semiconductor (MOS) layer, a source and a drain, at least one film layer, and a first electrode layer is provided. The gate is disposed on the substrate. The insulation layer covers the gate. The MOS layer is disposed on the insulation layer above the gate. The source and the drain are disposed on the MOS layer. The film layer covers the MOS layer and includes a transparent photocatalytic material, wherein the transparent photocatalytic material blocks ultraviolet light from reaching the MOS layer. The first electrode layer is electrically connected to the source or the drain. | 08-11-2011 |
20120168743 | THIN FILM TRANSISTOR AND FABRICATING METHOD THEREOF - A thin film transistor (TFT) including a gate, a gate insulator, an oxide semiconductor channel layer, a source, and a drain is provided. The gate insulator covers the gate, while the oxide semiconductor channel layer is configured on the gate insulator and located above the gate. The oxide semiconductor channel layer includes a first sub-layer and a second sub-layer located on the first sub-layer. An oxygen content of the first sub-layer is lower than an oxygen content of the second sub-layer. The source and the drain are configured on a portion of the second sub-layer. In addition, a fabricating method of the above-mentioned TFT is also provided. | 07-05-2012 |
20130026472 | TFT STRUCTURE AND PIXEL STRUCTURE - A pixel structure including a substrate, a gate, an insulation layer, a metal oxide semiconductor (MOS) layer, a source and a drain, at least one film layer, and a first electrode layer is provided. The gate is disposed on the substrate. The insulation layer covers the gate. The MOS layer is disposed on the insulation layer above the gate. The source and the drain are disposed on the MOS layer. The film layer covers the MOS layer and includes a transparent photocatalytic material, wherein the transparent photocatalytic material blocks ultraviolet light from reaching the MOS layer. The first electrode layer is electrically connected to the source or the drain. | 01-31-2013 |
20150123111 | PIXEL STRUCTURE AND FABRICATION METHOD THEREOF - A fabrication method of a pixel structure includes the following steps. A first metal layer is patterned to form a source electrode and a drain electrode. A semiconductor material layer is patterned to form a channel layer and a pixel pattern. A first insulation layer is formed to cover the channel layer, the source electrode, the drain electrode and the pixel pattern. A gate electrode is formed on the first insulation layer located above the channel layer. A second insulation layer is formed to cover the gate electrode and the first insulation layer. A pixel opening is formed in the first insulation layer and the second insulation layer to expose a partial region of the pixel pattern. The partial region of the pixel pattern exposed by the pixel opening is modified so as to form a pixel electrode electrically connected to the drain electrode. | 05-07-2015 |
Patent application number | Description | Published |
20090039055 | Method For Making An Aligned Carbon Nanotube - A method for making an aligned carbon nanotube includes the steps of a) applying a layer of a ferrosilicon alloy film onto a substrate, b) etching the layer of the ferrosilicon film to form a plurality of fine ferrosilicon alloy particles that are distributed properly on the substrate, and c) placing the substrate of step (b) into a microwave plasma enhanced chemical vapor deposition system, and supplying a mixture of a carbon-containing reaction gas and a balance gas at a predetermined flow ratio so as to grow carbon nanotubes on the fine ferrosilicon alloy particles, wherein said ferrosilicon alloy of step (a) comprises silicon ranging from 15 wt % to 25 wt %; and step (c) is conducted at a temperature ranging from 300 to 380° C. | 02-12-2009 |
20100279097 | SEMI-CONTINUOUS VAPOR GROWN CARBON FIBER MAT AND THE PRODUCING METHOD THEREOF - A method for fabricating a semi-continuous vapor grown carbon fiber mat, comprising: (a) providing a substrate which has a catalyst on its surface; (b) placing said substrate in a furnace; (c) introducing hydrogen, ammonia, or combinations thereof into said furnace; (d) adjusting a temperature of said furnace to 400° C. to 900° C. to proceed heat treatment for 15 to 90 minutes; (e) adding a carbon-containing compound into said furnace and adjusting the ratio of said carbon-containing compound and said hydrogen, ammonia, or combinations thereof; (f) adjusting the temperature of said furnace to 600° C. to 1200° C. to crack said carbon-containing compound, and thereby forming a carbon fiber mat, wherein time for reaction is 1 to 3 hours. The present invention also provides a semi-continuous vapor grown carbon fiber mat and a graphitized carbon fiber mat. | 11-04-2010 |
20140011920 | CONTINUOUS VAPOR GROWN CARBON FIBER MAT AND THE PRODUCING METHOD THEREOF - A method for fabricating a continuous vapor grown carbon fiber mat including: (a) providing a substrate which has a catalyst on its surface; (b) placing the substrate in a furnace; (c) introducing hydrogen, ammonia, or combinations thereof into the furnace; (d) adjusting a temperature of the furnace to 400° C. to 900° C. to proceed heat treatment for 15 to 90 minutes; (e) adding a carbon-containing compound into the furnace and adjusting the ratio of the carbon-containing compound and the hydrogen, ammonia, or combinations thereof; (f) adjusting the temperature of the furnace to 600° C. to 1200° C. to crack the carbon-containing compound, and thereby forming a carbon fiber mat, where time for reaction is 1 to 3 hours. A continuous vapor grown carbon fiber mat and a graphitized carbon fiber mat are also provided. | 01-09-2014 |
Patent application number | Description | Published |
20140325434 | ELECTRONIC APPARATUS CONTROLLING METHOD - An electronic apparatus controlling method, applied to an electronic apparatus displaying a first window and second window thereon. The electronic apparatus controlling method comprises: (a) determining one of the first window and the second window as a target window; and (b) displaying an input window on the electronic apparatus if the electronic apparatus receives an input triggering signal; wherein the input window does not substantially overlap any part of the target window. | 10-30-2014 |
20150138142 | METHOD FOR PERFORMING TOUCH COMMUNICATIONS CONTROL OF AN ELECTRONIC DEVICE BY USING LOCATION DETECTION WITH AID OF TOUCH PANEL, AND AN ASSOCIATED APPARATUS - A method for performing touch communications control and an associated apparatus are provided, where the method includes the steps of: detecting whether another touch communications device is close to or in contact with a first region of a touch panel of the touch communications device with aid of at least one of the touch panel of the touch communications device and a touch panel of the other touch communications device to obtain a detection result; and running a first application associated with the first region based on the detection result. | 05-21-2015 |
20150145792 | DEVICES AND METHODS OF TOUCH COMMUNICATIONS - A touch communications device includes a first touch panel and a processor. When a second touch panel of another touch communications device is close to or in contact with the first touch panel of the touch communications device, the processor obtains relative movement information about a relative movement between the touch communications device and the other touch communications device. The processor executes a corresponding action according to the relative movement information. | 05-28-2015 |
20150213782 | TOUCH ELECTRONIC DEVICE AND DATA TRANSMISSION METHOD - The present invention provides a touch electronic device and a data transmission method including a touch panel, a touch link module, a wireless transmission module and a control module. The touch link module is utilized to establish a first communication channel with at least one first touch electronic device through the touch panel, and receive at least one information from the at least one first touch electronic device through the first communication channel. The wireless transmission module is utilized to establish a second communication channel. The control module is utilized to receive the at least one information from the touch link module, divide an initial data into a plurality of sub-data according to the at least one information, and determine to transmit which sub-data of the plurality of sub-data to the at least one first touch electronic device through the first communication channel or the second communication channel. | 07-30-2015 |
Patent application number | Description | Published |
20090189251 | CAPACITOR FORMATION FOR A PUMPING CIRCUIT - A capacitor structure for a pumping circuit includes a substrate, a U-shaped bottom electrode in the substrate, a T-shaped top electrode in the substrate and a dielectric layer disposed between the U-shaped bottom and T-shaped top electrode. The contact area of the capacitor structure between the U-shaped bottom and T-shaped top electrode is extended by means of the cubic engagement of the U-shaped bottom electrode and the T-shaped top electrode. | 07-30-2009 |
20130001658 | CORNER TRANSISTOR AND METHOD OF FABRICATING THE SAME - A method of fabricating a corner transistor is described. An isolation structure is formed in a substrate to define an active region. A treating process is performed to make the substrate in the active region have sharp corners at top edges thereof. The substrate in the active region is covered by a gate dielectric layer. A gate conductor is formed over the gate dielectric layer. A source region and a drain region are formed in the substrate beside the gate conductor. | 01-03-2013 |
20130092989 | Embedded Transistor - An embedded transistor for an electrical device, such as a DRAM memory cell, and a method of manufacture thereof is provided. A trench is formed in a substrate and a gate dielectric and a gate electrode formed in the trench of the substrate. Source/drain regions are formed in the substrate on opposing sides of the trench. In an embodiment, one of the source/drain regions is coupled to a storage node and the other source/drain region is coupled to a bit line. In this embodiment, the gate electrode may be coupled to a word line to form a DRAM memory cell. | 04-18-2013 |
20130334486 | STRUCTURE AND METHOD FOR A COMPLIMENTARY RESISTIVE SWITCHING RANDOM ACCESS MEMORY FOR HIGH DENSITY APPLICATION - The present disclosure provides a resistive random access memory (RRAM) structure. The RRAM structure includes a bottom electrode on a substrate; a resistive material layer on the bottom electrode, the resistive material layer including a defect engineering film; and a top electrode on the resistive material layer. | 12-19-2013 |
20130336041 | Structure and Method for a Forming Free Resistive Random Access Memory with Multi-Level Cell - The present disclosure provides one embodiment of a method for operating a multi-level resistive random access memory (RRAM) cell having a current-controlling device and a RRAM device connected together. The method is free of a “forming” step and includes setting the RRAM device to one of resistance levels by controlling the current-controlling device to one of current levels. The setting the RRAM device includes applying a first voltage to a top electrode of the RRAM device and applying a second voltage to a bottom electrode of the RRAM device. The second voltage is higher than the first voltage. | 12-19-2013 |
20140035020 | Method of Forming an Embedded Memory Device - The present disclosure describes a method of forming a memory device. The method includes receiving a wafer substrate, forming a poly stack pattern on the wafer substrate, performing an ion implantation process to form a source and a drain in the wafer substrate, forming a memory gate and a control gate in the defined poly stack pattern, and forming a control gate in the control poly stack pattern. Forming the memory gate further includes performing a memory gate recess to bury the memory gate in an oxide layer. | 02-06-2014 |
20140131794 | Innovative Approach of 4F Driver Formation for High-Density RRAM and MRAM - Some embodiments of the present disclosure relate to a vertical MOSFET selection transistor that is configured to suppress leakage voltage in the memory cell without limiting the size of the memory cell. The memory selection transistor has a semiconductor body with first and second trenches that define a raised semiconductor structure having a source region, a channel region, and a drain region. A gate structure has a first gate electrode in the first trench, which extends vertically along a first side of the raised semiconductor structure, and a second gate electrode in the second trench, which extends vertically along an opposite, second side of the raised semiconductor structure. The first and second gate electrodes collectively control the flow of current between the source and drain region in the raised semiconductor structure. An electrical contact couples the drain region to a data storage element configured to store data. | 05-15-2014 |
20140146593 | Method And Structure For Resistive Switching Random Access Memory With High Reliable And High Density - The present disclosure provides a resistive random access memory (RRAM) structure. The RRAM structure includes a bottom electrode on a substrate; a resistive material layer on the bottom electrode, the resistive material layer having filament features with a filament ratio greater than about 0.5; and a top electrode on the resistive material layer. | 05-29-2014 |
20140177318 | Hybrid Memory - A two-switch hybrid memory cell device includes a storage node connected between one terminal of a first switch and a gate of a second switch. The device also includes a resistive switching device connected to the storage node. The resistive switching device is to act as a capacitance by being set to a high resistive state when the memory cell is in a dynamic mode. | 06-26-2014 |
20140177330 | VERTICAL BJT FOR HIGH DENSITY MEMORY - Some aspects of this disclosure relate to a memory device. The memory device includes a collector region having a first conductivity type and which is coupled to a source line of the memory device. A base region is formed over the collector region and has a second conductivity type. A gate structure is coupled to the base region and acts as a shared word line for first and second neighboring memory cells of the memory device. First and second emitter regions are formed over the base region and have the first conductivity type. The first and second emitter regions are arranged on opposite sides of the gate structure. First and second contacts extend upwardly from the first and second emitter regions, respectively, and couple the first and second emitter regions to first and second data storage elements, respectively, of the first and second neighboring memory cells, respectively. | 06-26-2014 |
20140233294 | Memory Cell with Decoupled Read/Write Path - A memory cell with a decoupled read/write path includes a switch comprising a first terminal connected to a first line and a second terminal connected to a second line, a resistive switching device connected between a gate of the switch and a third line, and a conductive path between the gate of the switch and the second line. | 08-21-2014 |
20140241034 | Resistive Switching Random Access Memory Structure and Method To Recreate Filament and Recover Resistance Window - The present disclosure provides one embodiment of a method for operating a resistive random access memory (RRAM) cell. The method includes performing a forming operation to the RRAM cell with a forming voltage; performing a number of set/reset operation cycles to the RRAM cell; and performing a recreating process to the RRAM cell to recover RRAM resistance by applying a recreating voltage. Each of the number of set/reset operation cycles includes a set operation with a set voltage. The recreating voltage is greater than the set voltage. | 08-28-2014 |
20140339631 | Innovative Approach of 4F2 Driver Formation for High-Density RRAM and MRAM - Some embodiments of the present disclosure relate to a memory array comprising memory cells having vertical gate-all-around (GAA) selection transistors. In some embodiments, the memory array has a source region disposed within an upper surface of a semiconductor body, and a semiconductor pillar of semiconductor material extending outward from the upper surface of the semiconductor body and having a channel region and an overlying drain region. A gate region vertically overlies the source region at a position laterally separated from sidewalls of the channel region by a gate dielectric layer. A first metal contact couples the drain region to a data storage element that stores data. The vertical GAA selection transistors provide for good performance, while decreasing the size of the selection transistor relative to a planar MOSFET, so that the selection transistors do not negatively impact the size of the memory array. | 11-20-2014 |
20140361354 | Embedded Transistor - An embedded transistor for an electrical device, such as a DRAM memory cell, and a method of manufacture thereof is provided. A trench is formed in a substrate and a gate dielectric and a gate electrode formed in the trench of the substrate. Source/drain regions are formed in the substrate on opposing sides of the trench. In an embodiment, one of the source/drain regions is coupled to a storage node and the other source/drain region is coupled to a bit line. In this embodiment, the gate electrode may be coupled to a word line to form a DRAM memory cell. A dielectric growth modifier may be implanted into sidewalls of the trench in order to tune the thickness of the gate dielectric. | 12-11-2014 |
20150021677 | Embedded Transistor - An embedded transistor for an electrical device, such as a DRAM memory cell, and a method of manufacture thereof is provided. A trench is formed in a substrate and a gate dielectric and a gate electrode formed in the trench of the substrate. Source/drain regions are formed in the substrate on opposing sides of the trench. In an embodiment, one of the source/drain regions is coupled to a storage node and the other source/drain region is coupled to a bit line. In this embodiment, the gate electrode may be coupled to a word line to form a DRAM memory cell. | 01-22-2015 |
20150187418 | Metal Line Connection for Improved RRAM Reliability, Semiconductor Arrangement Comprising the Same, and Manufacture Thereof - An integrated circuit device includes an array of RRAM cells, an array of bit lines for the array of RRAM cells, and an array of source lines for the array of RRAM cells. Both the source lines and the bit lines are in metal interconnect layers above the RRAM cells. The source line are thereby provided with a higher than conventional wire size, which increases the reset speed by approximately one order of magnitude. The lifetime of the RRAM transistors and the durability of the RRAM device are consequentially improved to a similar degree. | 07-02-2015 |
20150235698 | Method And Structure For Resistive Switching Random Access Memory With High Reliable And High Density - The present disclosure provides a resistive random access memory (RRAM) structure. The RRAM structure includes a bottom electrode on a substrate; a resistive material layer on the bottom electrode, the resistive material layer having filament features with a filament ratio greater than about 0.5; and a top electrode on the resistive material layer. | 08-20-2015 |