| Patent application number | Description | Published |
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| 20080313431 | Method and System for Altering Processor Execution of a Group of Instructions - An embodiment of the invention is a processor for detecting one or more groups of instructions and initiating a processor action upon detecting one or more groups of instructions. The processor includes an instruction unit for fetching and decoding a group of instructions. An instruction register receives the group of instruction having at least one instruction opcode. A control register includes a control word including a control opcode and an action field defining a processor action. An execution unit includes compare logic for comparing the instruction opcode and the control opcode. The execution unit initiates the processor action upon the compare logic detecting a hit between the instruction opcode and the control opcode. | 12-18-2008 |
| 20090157967 | Pre-Fetch Data and Pre-Fetch Data Relative - A prefetch data machine instruction having an M field performs a function on a cache line of data specifying an address of an operand. The operation comprises either prefetching a cache line of data from memory to a cache or reducing the access ownership of store and fetch or fetch only of the cache line in the cache or a combination thereof. The address of the operand is either based on a register value or the program counter value pointing to the prefetch data machine instruction. | 06-18-2009 |
| 20090182942 | Extract Cache Attribute Facility and Instruction Therefore - A facility and cache machine instruction of a computer architecture for specifying a target cache cache-level and a target cache attribute of interest for obtaining a cache attribute of one or more target caches. The requested cache attribute of the target cache(s) is saved in a register. | 07-16-2009 |
| 20090182964 | DYNAMIC ADDRESS TRANSLATION WITH FORMAT CONTROL - What is provided is an enhanced dynamic address translation facility. In one embodiment, a virtual address to be translated and an initial origin address of a translation table of the hierarchy of translation tables are obtained. An index portion of the virtual address is used to reference an entry in the translation table. If the format control field is enabled, a frame address of a large block of data in main storage is obtained from the translation table entry. The large block of data is a block of at least 1M byte in size. The frame address is then combined with an offset portion of the virtual address to form the translated address of a desired block of data within the large block of data in main storage. The desired large block of data addressed by the translated address is then accessed. | 07-16-2009 |
| 20090182966 | DYNAMIC ADDRESS TRANSLATION WITH FRAME MANAGEMENT - What is disclosed is a frame management function defined for a machine architecture of a computer system. In one embodiment, a frame management instruction is obtained which identifies a first and second general register. The first general register contains a frame management field having a key field with access-protection bits and a block-size indication. If the block-size indication indicates a large block then an operand address of a large block of data is obtained from the second general register. The large block of data has a plurality of small blocks each of which is associated with a corresponding storage key having a plurality of storage key access-protection bits. If the block size indication indicates a large block, the storage key access-protection bits of each corresponding storage key of each small block within the large block is set with the access-protection bits of the key field. | 07-16-2009 |
| 20090182971 | DYNAMIC ADDRESS TRANSLATION WITH FETCH PROTECTION - What is provided is an enhanced dynamic address translation facility. In one embodiment, a virtual address to be translated is first obtained and an initial origin address of a translation table of the hierarchy of translation tables is obtained. Based on the obtained initial origin, a segment table entry is obtained. The segment table entry is configured to contain a format control and access validity fields. If the format control and access validity fields are enabled, the segment table entry further contains an access control field, a fetch protection field, and a segment-frame absolute address. Store operations are permitted only if the access control field matches a program access key provided by any one of a Program Status Word or an operand of a program instruction being executed. Fetch operations are permitted if the program access key associated with the virtual address is equal to the segment access control field. | 07-16-2009 |
| 20090182972 | DYNAMIC ADDRESS TRANSLATION WITH FORMAT CONTROL - What is provided is an enhanced dynamic address translation facility. In one embodiment, a virtual address to be translated and an initial origin address of a translation table of the hierarchy of translation tables are obtained. An index portion of the virtual address is used to reference an entry in the translation table. If a format control field contained in the translation table entry is enabled, the table entry contains a frame address of a large block of data of at least 1M byte in size. The frame address is then combined with an offset portion of the virtual address to form the translated address of a small 4K byte block of data in main storage or memory. | 07-16-2009 |
| 20090182983 | Compare and Branch Facility and Instruction Therefore - An atomic compare and branch instruction is executed that combines the function of a compare instruction having an option field with a conditional branch or jump instruction such that condition codes are preserved rather than setting condition codes to a value representative of the compare results. One comparand is obtained from any one of a memory location or an immediate field and the other comparand is obtained from a register field. | 07-16-2009 |
| 20090182984 | Execute Relative Long Facility and Instructions Therefore - A method, system and program product for an execute relative instruction, which when executed fetches and executes a target instruction at a relative address and then returns processing to the next instruction following the execute relative instruction. The relative address is formed by adding the value of the program counter to a sign extended immediate field. The fetched target instruction is optionally modified before execution by OR'ing bits into predetermined bits of the target instruction. | 07-16-2009 |
| 20090182985 | Move Facility and Instructions Therefore - A move instruction, having a signed immediate field, copies a sign extended signed immediate field value to an operand location in memory. The size of the operand is determined by the opcode of the instruction. Preferably, the address of the operand is determined by adding a displacement field of the instruction to a value associated with a register field of the instruction. | 07-16-2009 |
| 20090182988 | Compare Relative Long Facility and Instructions Therefore - A method, system and program product for comparing two operands wherein one operand is obtained from memory wherein the address of the memory operand is based an offset of the program counter rather than an explicitly defined address location. The offset is defined by an immediate field of the instruction which is sign extended and is aligned as a halfword address when added to the value of the program counter. | 07-16-2009 |
| 20090182992 | Load Relative and Store Relative Facility and Instructions Therefore - A method, system and program product for loading or storing memory data wherein the address of the memory operand is based an offset of the program counter rather than an explicitly defined address location. The offset is defined by an immediate field of the instruction which is sign extended and is aligned as a halfword address when added to the value of the program counter. | 07-16-2009 |
| 20090187724 | DYNAMIC ADDRESS TRANSLATION WITH FRAME MANAGEMENT - What is disclosed is a set key and clear frame management function defined for a machine architecture of a computer system. In one embodiment, a machine instruction is obtained which identifies a first and second general register. Obtained from the first general register is a frame size field indicating whether a storage frame is one of a small block or a large block of data. Obtained from the second general register is an operand address of a storage frame upon which the instruction is to be performed. If the storage frame is a small block, the instruction is performed only on the small block. If the indicated storage frame is a large block of data, an operand address of an initial first block of data within the large block of data is obtained from the second general register. The frame management instruction is performed on all blocks starting from the initial first block. | 07-23-2009 |
| 20090187728 | DYNAMIC ADDRESS TRANSLATION WITH CHANGE RECORDING OVERRIDE - What is provided is an enhanced dynamic address translation facility. In one embodiment, a virtual address to be translated and an initial origin address of a translation table of the hierarchy of translation tables are obtained. A segment table entry obtained from a segment table contains a format control field. If the format control field is enabled, a segment-frame absolute address of a large block of data in main storage is obtained from the segment table entry. Each 4K byte block of data within the large block has an associated storage key. Store operations associated with the virtual address are performed to the desired block of data. If the change recording override field is disabled, the change bit of the storage key associated with the desired 4K byte block is set to 1. An indication is then provided that the desired 4K byte block has been modified. | 07-23-2009 |
| 20090187732 | DYNAMIC ADDRESS TRANSLATION WITH DAT PROTECTION - What is provided is an enhanced dynamic address translation facility. In one embodiment, a virtual address to be translated and an initial origin address of any one of a region first table, a region second table, a region third table, or a segment table are obtained. Based on the obtained initial origin address, a segment table entry is obtained which contains a format control and DAT protection fields. If the format control field is enabled, obtaining from the translation table entry a segment-frame absolute address of a large block of data in main storage. The segment-frame absolute address is combined with a page index portion and a byte index portion of the virtual address to form a translated address of the desired block of data. If the DAT protection field is not enabled, fetches and stores are permitted to the desired block of data addressed by the translated virtual address. | 07-23-2009 |
| 20090193214 | DYNAMIC ADDRESS TRANSLATION WITH FRAME MANAGEMENT - What is disclosed is a frame management function defined for a machine architecture of a computer system. In one embodiment, a machine instruction is obtained containing an opcode for a frame management instruction identifying a first and second general register. Clear frame information is obtained from the first general register having a frame size field indicating whether a storage frame is a small or large block of data. The second general register contains an operand address of a storage frame. If the storage frame is a small block, all bytes of the small block of data are set to zero. If the storage frame is a large block of data, an operand address of an initial first block of data within the large block is obtained from the second general register. All data of all blocks within the large block are cleared starting from the initial first block. | 07-30-2009 |
| 20090198980 | FACILITATING PROCESSING IN A COMPUTING ENVIRONMENT USING AN EXTENDED DRAIN INSTRUCTION - An extended DRAIN instruction is used to stall processing within a computing environment. The instruction includes an indication of the one or more processing stages at which processing is to be stalled. It also includes a control that allows processing to be stalled for additional cycles, as desired. | 08-06-2009 |
| 20090204924 | METHOD, SYSTEM AND COMPUTER PROGRAM PRODUCT FOR FAILURE ANALYSIS IMPLEMENTING AUTOMATED COMPARISON OF MULTIPLE REFERENCE MODELS - System, method and computer program products for failure analysis implementing automated comparison of multiple reference models. An exemplary embodiment includes a method for failure analysis for an instruction set implementation in a computer system, the method including running a test-case in a first and a second model, determining if the test case failed in the first model and determining if the test case failed in the second model. | 08-13-2009 |
| 20090216929 | SYSTEM, METHOD AND COMPUTER PROGRAM PRODUCT FOR PROVIDING A PROGRAMMABLE QUIESCE FILTERING REGISTER - A system, method and computer program product for providing a programmable quiesce filtering register. The method includes receiving a quiesce interruption request at the processor. The processor is executing in a mode. A filtering zone associated with the mode is identified. It is determined if the quiesce interruption request can be filtered by the processor. The determining is responsive to the filtering zone and to contents of a programmable filtering register for indicating exceptions to filtering performed by the receiving processor. The quiesce interruption request is filtered in response to determining that the request can be filtered. | 08-27-2009 |
| 20090240908 | FILTERING PROCESSOR REQUESTS BASED ON IDENTIFIERS - Processing within a computing environment is facilitated by filtering requests of the computing environment. A processing unit that receives a request determines whether it is to perform the request. This determination is made by, for instance, comparing an identifier of the request with an identifier of the processing unit making the determination. If there is a mismatch, then the request is blocked. Other processing within the computing environment is also facilitated by selectively using buffer entries. The selection criteria is based, for instance, on identifier information. | 09-24-2009 |
| 20090240922 | METHOD, SYSTEM, COMPUTER PROGRAM PRODUCT, AND HARDWARE PRODUCT FOR IMPLEMENTING RESULT FORWARDING BETWEEN DIFFERENTLY SIZED OPERANDS IN A SUPERSCALAR PROCESSOR - Result and operand forwarding is provided between differently sized operands in a superscalar processor by grouping a first set of instructions for operand forwarding, and grouping a second set of instructions for result forwarding, the first set of instructions comprising a first source instruction having a first operand and a first dependent instruction having a second operand, the first dependent instruction depending from the first source instruction; the second set of instructions comprising a second source instruction having a third operand and a second dependent instruction having a fourth operand, the second dependent instruction depending from the second source instruction, performing operand forwarding by forwarding the first operand, either whole or in part, as it is being read to the first dependent instruction prior to execution; performing result forwarding by forwarding a result of the second source instruction, either whole or in part, to the second dependent instruction, after execution; wherein the operand forwarding is performed by executing the first source instruction together with the first dependent instruction; and wherein the result forwarding is performed by executing the second source instruction together with the second dependent instruction. | 09-24-2009 |
| 20100100692 | Exploiting Register High-Words - A method of utilizing registers in a processor device is provided. The method includes: determining a first operand based on an operand notation indicating a subset of high-order bits of a first register, the first register having a total of sixty-four bits; determining a second operand based on an operand notation indicating at least one of a subset of high-order bits of a second register and a subset of low-order bits of the second register, the second register having a total of sixty-four bits; performing an operation based on the first operand and the second operand; and updating at least one of the first register and the second register based on a result of the operation, and wherein the high-order bits include bits that are greater than thirty-two, and wherein the low-order bits include bits that are less than or equal to thirty-two. | 04-22-2010 |
| 20100299506 | ROTATE THEN OPERATE ON SELECTED BITS FACILITY AND INSTRUCTIONS THEREFORE - A rotate then operate instruction having a T bit is fetched and executed wherein a first operand in a first register is rotated by an amount and a Boolean operation is performed on a selected portion of the rotated first operand and a second operand in of a second register. If the T bit is ‘0’ the selected portion of the result of the Boolean operation is inserted into corresponding bits of a second operand of a second register. If the T bit is ‘1’, in addition to the inserted bits, the bits other than the selected portion of the rotated first operand are saved in the second register. | 11-25-2010 |
| 20110119466 | Clearing Selected Storage Translation Buffer Entries Bases On Table Origin Address - An instruction is provided to perform clearing of selected address translation buffer entries (TLB entries) associated with a particular address space, such as segments of storage or regions of storage. The buffer entries related to segment table entries or region table entries or ASCE addresses. The instruction can be implemented by software emulation, hardware, firmware or some combination thereof. | 05-19-2011 |
| 20110145550 | NON-QUIESCING KEY SETTING FACILITY - A non-quiescing key setting facility is provided that enables manipulation of storage keys to be performed without quiescing operations of other processors of a multiprocessor system. With this facility, a storage key, which is accessible by a plurality of processors of the multiprocessor system, is updated absent a quiesce of operations of the plurality of processors. Since the storage key is updated absent quiescing of other operations, the storage key may be observed by a processor as having one value at the start of an operation performed by the processor and a second value at the end of the operation. A mechanism is provided to enable the operation to continue, avoiding a fatal exception. | 06-16-2011 |
| 20110202748 | LOAD PAIR DISJOINT FACILITY AND INSTRUCTION THEREFORE - A Load/Store Disjoint instruction, when executed by a CPU, accesses operands from two disjoint memory locations and sets condition code indicators to indicate whether or not the two operands appeared to be accessed atomically by means of block-concurrent interlocked fetch with no intervening stores to the operands from other CPUs. In a Load Pair Disjoint form of the instruction, the accesses are loads and the disjoint data is stored in general registers. | 08-18-2011 |
| 20110296114 | ATOMIC EXECUTION OVER ACCESSES TO MULTIPLE MEMORY LOCATIONS IN A MULTIPROCESSOR SYSTEM - A method and central processing unit supporting atomic access of shared data by a sequence of memory access operations. A processor status flag is reset. A processor executes, subsequent to the setting of the processor status flag, a sequence of program instructions with instructions accessing a subset of shared data contained within its local cache. During execution of the sequence of program instructions and in response to a modification by another processor of the subset of shared data, the processor status flag is set. Subsequent to the executing the sequence of program instructions and based upon the state of the processor status flag, either a first program processing or a second program processing is executed. In some examples the first program processing includes storing results data into the local cache and the second program processing includes discarding the results data. | 12-01-2011 |
| 20110314260 | HIGH-WORD FACILITY FOR EXTENDING THE NUMBER OF GENERAL PURPOSE REGISTERS AVAILABLE TO INSTRUCTIONS - A computer employs a set of General Purpose Registers (GPRs). Each GPR comprises a plurality of portions. Programs such as an Operating System and Applications operating in a Large GPR mode, access the full GPR, however programs such as Applications operating in Small GPR mode, only have access to a portion at a time. Instruction Opcodes, in Small GPR mode, may determine which portion is accessed. | 12-22-2011 |
| 20110314263 | INSTRUCTIONS FOR PERFORMING AN OPERATION ON TWO OPERANDS AND SUBSEQUENTLY STORING AN ORIGINAL VALUE OF OPERAND - An arithmetic/logical instruction is executed having interlocked memory operands. when executed obtains a second operand from a location in memory, and saves a temporary copy of the second operand, the execution performs an arithmetic or logical operation based on the second operand and a third operand and stores the result in the memory location of the second operand, and subsequently stores the temporary copy in a first register. | 12-22-2011 |
| 20110320773 | FUNCTION VIRTUALIZATION FACILITY FOR BLOCKING INSTRUCTION FUNCTION OF A MULTI-FUNCTION INSTRUCTION OF A VIRTUAL PROCESSOR - In a processor supporting execution of a plurality of functions of an instruction, an instruction blocking value is set for blocking one or more of the plurality of functions, such that an attempt to execute one of the blocked functions, will result in a program exception and the instruction will not execute, however the same instruction will be able to execute any of the functions that are not blocked functions. | 12-29-2011 |
| 20110320783 | VERIFICATION USING OPCODE COMPARE - A verification method is provided and includes randomly choosing a hardware executed instruction in a predefined program to force Opcode Compare on, determining an identity of a corresponding opcode from the chosen instruction and initializing Opcode Compare logic to trap the chosen instruction to firmware and creating firmware to initiate performance of hardware verification in the firmware and re-initiating performance of the hardware verification in hardware. | 12-29-2011 |
| 20110320825 | FUNCTION VIRTUALIZATION FACILITY FOR FUNCTION QUERY OF A PROCESSOR - Selected installed function of a multi-function instruction is hidden such that even though a processor is capable of performing the hidden installed function, the availability of the hidden function is hidden such that responsive to the multi-function instruction querying the availability of functions, only functions not hidden are reported as installed. | 12-29-2011 |
| 20120011341 | Load Page Table Entry Address Instruction Execution Based on an Address Translation Format Control Field - What is provided is a load page table entry address function defined for a machine architecture of a computer system. In one embodiment, a machine instruction is obtained which contains an opcode indicating that a load page table entry address function is to be performed. The machine instruction contains an M field, a first field identifying a first general register, and a second field identifying a second general register. Based on the contents of the M field, an initial origin address of a hierarchy of address translation tables having at least one segment table is obtained. Based on the obtained initial origin address, dynamic address translation is performed until a page table entry is obtained. The page table entry address is saved in the identified first general register. | 01-12-2012 |
| 20120036338 | FACILITATING PROCESSING IN A COMPUTING ENVIRONMENT USING AN EXTENDED DRAIN INSTRUCTION - An extended DRAIN instruction is used to stall processing within a computing environment. The instruction includes an indication of the one or more processing stages at which processing is to be stalled. It also includes a control that allows processing to be stalled for additional cycles, as desired. | 02-09-2012 |
| 20120117356 | Invalidating a Range of Two ro More Translation Table Entries and Instruction Therefore - An instruction is provided to perform invalidation of an instruction specified range of segment table entries or region table entries. The instruction can be implemented by software emulation, hardware, firmware or some combination thereof. | 05-10-2012 |
| 20120137073 | Extract Cache Attribute Facility and Instruction Therefore - A facility and cache machine instruction of a computer architecture for specifying a target cache cache-level and a target cache attribute of interest for obtaining a cache attribute of one or more target caches. The requested cache attribute of the target cache(s) is saved in a register. | 05-31-2012 |
| 20120137106 | Dynamic Address Translation With Translation Table Entry Format Control for Identifying Format of the Translation Table Entry - What is provided is an enhanced dynamic address translation facility. In one embodiment, a virtual address to be translated and an initial origin address of a translation table of the hierarchy of translation tables are obtained. An index portion of the virtual address is used to reference an entry in the translation table. If a format control field contained in the translation table entry is enabled, the table entry contains a frame address of a large block of data of at least 1M byte in size. The frame address is then combined with an offset portion of the virtual address to form the translated address of a small 4K byte block of data in main storage or memory. | 05-31-2012 |
| 20120144125 | Instruction for Pre-Fetching Data and Releasing Cache Lines - A prefetch data machine instruction having an M field performs a function on a cache line of data specifying an address of an operand. The operation comprises either prefetching a cache line of data from memory to a cache or reducing the access ownership of store and fetch or fetch only of the cache line in the cache or a combination thereof. The address of the operand is either based on a register value or the program counter value pointing to the prefetch data machine instruction. | 06-07-2012 |
| 20120144153 | Dynamic Address Translation With Change Record Override - A translation table entry contains a change recording override field for controlling whether a change bit is to be set on a store or not. Each 4K byte block of main storage has an associated storage key comprising a change bit. The change recording override field controls whether the change bit of the storage key associated with the desired 4K byte block of main storage is set to 1 for a store operation. | 06-07-2012 |
| 20120144154 | SYSTEM, METHOD AND COMPUTER PROGRAM PRODUCT FOR PROVIDING A PROGRAMMABLE QUIESCE FILTERING REGISTER - Storing translation lookaside buffer (TLB) entries are in a TLB | 06-07-2012 |
| 20120166758 | Executing a Perform Frame Management Instruction - What is disclosed is a frame management function defined for a machine architecture of a computer system. In one embodiment, a frame management instruction is obtained which identifies a first and second general register. The first general register contains a frame management field having a key field with access-protection bits and a block-size indication. If the block-size indication indicates a large block then an operand address of a large block of data is obtained from the second general register. The large block of data has a plurality of small blocks each of which is associated with a corresponding storage key having a plurality of storage key access-protection bits. If the block size indication indicates a large block, the storage key access-protection bits of each corresponding storage key of each small block within the large block is set with the access-protection bits of the key field. | 06-28-2012 |
| 20120204010 | NON-QUIESCING KEY SETTING FACILITY - A non-quiescing key setting facility is provided that enables manipulation of storage keys to be performed without quiescing operations of other processors of a multiprocessor system. With this facility, a storage key, which is accessible by a plurality of processors of the multiprocessor system, is updated absent a quiesce of operations of the plurality of processors. Since the storage key is updated absent quiescing of other operations, the storage key may be observed by a processor as having one value at the start of an operation performed by the processor and a second value at the end of the operation. A mechanism is provided to enable the operation to continue, avoiding a fatal exception. | 08-09-2012 |
| 20130117545 | High-Word Facility for Extending the Number of General Purpose Registers Available to Instructions - A computer employs a set of General Purpose Registers (GPRs). Each GPR comprises a plurality of portions. Programs such as an Operating System and Applications operating in a Large GPR mode, access the full GPR, however programs such as Applications operating in Small GPR mode, only have access to a portion at a time. Instruction Opcodes, in Small GPR mode, may determine which portion is accessed. | 05-09-2013 |
| 20130117546 | Load Pair Disjoint Facility and Instruction Therefore - A Load/Store Disjoint instruction, when executed by a CPU, accesses operands from two disjoint memory locations and sets condition code indicators to indicate whether or not the two operands appeared to be accessed atomically by means of block-concurrent interlocked fetch with no intervening stores to the operands from other CPUs. In a Load Pair Disjoint form of the instruction, the accesses are loads and the disjoint data is stored in general registers. | 05-09-2013 |
| 20130173891 | CONVERT FROM ZONED FORMAT TO DECIMAL FLOATING POINT FORMAT - Machine instructions, referred to herein as a long Convert from Zoned instruction (CDZT) and extended Convert from Zoned instruction (CXZT), are provided that read EBCDIC or ASCII data from memory, convert it to the appropriate decimal floating point format, and write it to a target floating point register or floating point register pair. Further, machine instructions, referred to herein as a long Convert to Zoned instruction (CZDT) and extended Convert to Zoned instruction (CZXT), are provided that convert a decimal floating point (DFP) operand in a source floating point register or floating point register pair to EBCDIC or ASCII data and store it to a target memory location. | 07-04-2013 |
| 20130173892 | CONVERT TO ZONED FORMAT FROM DECIMAL FLOATING POINT FORMAT - Machine instructions, referred to herein as a long Convert from Zoned instruction (CDZT) and extended Convert from Zoned instruction (CXZT), are provided that read EBCDIC or ASCII data from memory, convert it to the appropriate decimal floating point format, and write it to a target floating point register or floating point register pair. Further, machine instructions, referred to herein as a long Convert to Zoned instruction (CZDT) and extended Convert to Zoned instruction (CZXT), are provided that convert a decimal floating point (DFP) operand in a source floating point register or floating point register pair to EBCDIC or ASCII data and store it to a target memory location. | 07-04-2013 |
| 20130243325 | COMPARING SETS OF CHARACTER DATA HAVING TERMINATION CHARACTERS - Multiple sets of character data having termination characters are compared using parallel processing and without causing unwarranted exceptions. Each set of character data to be compared is loaded within one or more vector registers. In particular, in one embodiment, for each set of character data to be compared, an instruction is used that loads data in a vector register to a specified boundary, and provides a way to determine the number of characters loaded. Further, an instruction is used to find the index of the first delimiter character, i.e., the first zero or null character, or the index of unequal characters. Using these instructions, a location of the end of one of the sets of data or a location of an unequal character is efficiently provided. | 09-19-2013 |
| 20130246699 | FINDING THE LENGTH OF A SET OF CHARACTER DATA HAVING A TERMINATION CHARACTER - The length of character data having a termination character is determined. The character data for which the length is to be determined is loaded, in parallel, within one or more vector registers. An instruction is used that loads data in a vector register to a specified boundary, and provides a way to determine the number of characters loaded, using, for instance, another instruction. Further, an instruction is used to find the index of the first termination character, e.g., the first zero or null character. This instruction searches the data in parallel for the termination character. By using these instructions, the length of the character data is determined using only one branch instruction. | 09-19-2013 |
| 20130246738 | INSTRUCTION TO LOAD DATA UP TO A SPECIFIED MEMORY BOUNDARY INDICATED BY THE INSTRUCTION - A Load to Block Boundary instruction is provided that loads a variable number of bytes of data into a register while ensuring that a specified memory boundary is not crossed. The boundary may be specified a number of ways, including, but not limited to, a variable value in the instruction text, a fixed instruction text value encoded in the opcode, or a register based boundary. | 09-19-2013 |
| 20130246739 | COPYING CHARACTER DATA HAVING A TERMINATION CHARACTER FROM ONE MEMORY LOCATION TO ANOTHER - Copying characters of a set of terminated character data from one memory location to another memory location using parallel processing and without causing unwarranted exceptions. The character data to be copied is loaded within one or more vector registers. In particular, in one embodiment, an instruction (e.g., a Vector Load to block Boundary instruction) is used that loads data in parallel in a vector register to a specified boundary, and provides a way to determine the number of characters loaded. To determine the number of characters loaded (a count), another instruction (e.g., a Load Count to Block Boundary instruction) is used. Further, an instruction (e.g., a Vector Find Element Not Equal instruction) is used to find the index of the first delimiter character, i.e., the first termination character, such as a zero or null character within the character data. This instruction checks a plurality of bytes of data in parallel. | 09-19-2013 |
| 20130246740 | INSTRUCTION TO LOAD DATA UP TO A DYNAMICALLY DETERMINED MEMORY BOUNDARY - A Load to Block Boundary instruction is provided that loads a variable number of bytes of data into a register while ensuring that a specified memory boundary is not crossed. The boundary is dynamically determined based on a specified type of boundary and one or more characteristics of the processor executing the instruction, such as cache line size or page size used by the processor. | 09-19-2013 |
| 20130246744 | MODIFYING RUN-TIME-INSTRUMENTATION CONTROLS FROM A LESSER-PRIVILEGED STATE - Embodiments of the invention relate to modifying run-time-instrumentation controls (MRIC) from a lesser-privileged state. The MRIC instruction is fetched. The MRIC instruction includes the address of a run-time-instrumentation control block (RICCB). The RICCB is fetched based on the address included in the MRIC instruction. The RICCB includes values for modifying a subset of the processor's run-time-instrumentation controls. The subset of run-time-instrumentation controls includes a runtime instrumentation program buffer current address (RCA) of a runtime instrumentation program buffer (RIB) location. The RIB holds run-time-instrumentation information of the events recognized by the processor during program execution. The values of the RICCB are loaded into the run-time-instrumentation controls. Event information is provided to the RIB based on the values that were loaded in the run-time-instrumentation control. | 09-19-2013 |
| 20130246751 | VECTOR FIND ELEMENT NOT EQUAL INSTRUCTION - Processing of character data is facilitated. A Find Element Not Equal instruction is provided that compares data of multiple vectors for inequality and provides an indication of inequality, if inequality exists. An index associated with the unequal element is stored in a target vector register. Further, the same instruction, the Find Element Not Equal instruction, also searches a selected vector for null elements, also referred to as zero elements. A result of the instruction is dependent on whether the null search is provided, or just the compare. | 09-19-2013 |
| 20130246752 | VECTOR FIND ELEMENT EQUAL INSTRUCTION - Processing of character data is facilitated. A Find Element Equal instruction is provided that compares data of multiple vectors for equality and provides an indication of equality, if equality exists. An index associated with the equal element is stored in a target vector register. Further, the same instruction, the Find Element Equal instruction, also searches a selected vector for null elements, also referred to as zero elements. A result of the instruction is dependent on whether the null search is provided, or just the compare. | 09-19-2013 |
| 20130246753 | VECTOR STRING RANGE COMPARE - Processing of character data is facilitated. A Vector String Range Compare instruction is provided that compares each element of a vector with a range of values based on a set of controls to determine if there is a match. An index associated with the matched element or a mask representing the matched element is stored in a target vector register. Further, the same instruction, the Vector String Range Compare instruction, also searches a selected vector for null elements, also referred to as zero elements. | 09-19-2013 |
| 20130246757 | VECTOR FIND ELEMENT EQUAL INSTRUCTION - Processing of character data is facilitated. A Find Element Equal instruction is provided that compares data of multiple vectors for equality and provides an indication of equality, if equality exists. An index associated with the equal element is stored in a target vector register. Further, the same instruction, the Find Element Equal instruction, also searches a selected vector for null elements, also referred to as zero elements. A result of the instruction is dependent on whether the null search is provided, or just the compare. | 09-19-2013 |
| 20130246758 | VECTOR STRING RANGE COMPARE - Processing of character data is facilitated. A Vector String Range Compare instruction is provided that compares each element of a vector with a range of values based on a set of controls to determine if there is a match. An index associated with the matched element or a mask representing the matched element is stored in a target vector register. Further, the same instruction, the Vector String Range Compare instruction, also searches a selected vector for null elements, also referred to as zero elements. | 09-19-2013 |
| 20130246759 | VECTOR FIND ELEMENT NOT EQUAL INSTRUCTION - Processing of character data is facilitated. A Find Element Not Equal instruction is provided that compares data of multiple vectors for inequality and provides an indication of inequality, if inequality exists. An index associated with the unequal element is stored in a target vector register. Further, the same instruction, the Find Element Not Equal instruction, also searches a selected vector for null elements, also referred to as zero elements. A result of the instruction is dependent on whether the null search is provided, or just the compare. | 09-19-2013 |
| 20130246762 | INSTRUCTION TO LOAD DATA UP TO A DYNAMICALLY DETERMINED MEMORY BOUNDARY - A Load to Block Boundary instruction is provided that loads a variable number of bytes of data into a register while ensuring that a specified memory boundary is not crossed. The boundary is dynamically determined based on a specified type of boundary and one or more characteristics of the processor executing the instruction, such as cache line size or page size used by the processor. | 09-19-2013 |
| 20130246763 | INSTRUCTION TO COMPUTE THE DISTANCE TO A SPECIFIED MEMORY BOUNDARY - A Load Count to Block Boundary instruction is provided that provides a distance from a specified memory address to a specified memory boundary. The memory boundary is a boundary that is not to be crossed in loading data. The boundary may be specified a number of ways, including, but not limited to, a variable value in the instruction text, a fixed instruction text value encoded in the opcode, or a register based boundary; or it may be dynamically determined. | 09-19-2013 |
| 20130246764 | INSTRUCTION TO LOAD DATA UP TO A SPECIFIED MEMORY BOUNDARY INDICATED BY THE INSTRUCTION - A Load to Block Boundary instruction is provided that loads a variable number of bytes of data into a register while ensuring that a specified memory boundary is not crossed. The boundary may be specified a number of ways, including, but not limited to, a variable value in the instruction text, a fixed instruction text value encoded in the opcode, or a register based boundary. | 09-19-2013 |
| 20130246767 | INSTRUCTION TO COMPUTE THE DISTANCE TO A SPECIFIED MEMORY BOUNDARY - A Load Count to Block Boundary instruction is provided that provides a distance from a specified memory address to a specified memory boundary. The memory boundary is a boundary that is not to be crossed in loading data. The boundary may be specified a number of ways, including, but not limited to, a variable value in the instruction text, a fixed instruction text value encoded in the opcode, or a register based boundary; or it may be dynamically determined. | 09-19-2013 |
| 20130246769 | RUN-TIME INSTRUMENTATION MONITORING FOR PROCESSOR CHARACTERISTIC CHANGES - Embodiments of the invention relate to monitoring processor characteristic information of a processor using run-time-instrumentation. An aspect of the invention includes executing an instruction stream on the processor and detecting a run-time instrumentation sample point of the executing instruction stream on the processor. A reporting group is stored in a run-time instrumentation program buffer based on the run-time instrumentation sample point. The reporting group includes processor characteristic information associated with the processor. | 09-19-2013 |
| 20130246770 | CONTROLLING OPERATION OF A RUN-TIME INSTRUMENTATION FACILITY FROM A LESSER-PRIVILEGED STATE - Embodiments of the invention relate to enabling and disabling execution of a run-time instrumentation facility. An instruction for execution by the processor in a lesser privileged state is fetched by the processor. It is determined, by the processor, that the run-time instrumentation facility permits execution of the instruction in the lesser-privileged state and that controls associated with the run-time instrumentation facility are valid. The run-time instrumentation facility is disabled based on the instruction being a run-time instrumentation facility off (RIOFF) instruction. The disabling includes updating a bit in a program status word (PSW) of the processor to indicate that run-time instrumentation data should not be captured by the processor. The run-time instrumentation facility is enabled based on the instruction being a run-time instrumentation facility on (RION) instruction. The enabling includes updating the bit in the PSW to indicate that run-time instrumentation data should be captured by the processor. | 09-19-2013 |
| 20130246771 | RUN-TIME INSTRUMENTATION MONITORING OF PROCESSOR CHARACTERISTICS - Embodiments of the invention relate to monitoring processor characteristic information of a processor using run-time-instrumentation. An aspect of the invention includes executing an instruction stream on the processor and detecting a run-time instrumentation sample point of the executing instruction stream on the processor. A reporting group is stored in a run-time instrumentation program buffer based on the run-time instrumentation sample point. The reporting group includes processor characteristic information associated with the processor. | 09-19-2013 |
| 20130247013 | CONTROLLING OPERATION OF A RUN-TIME INSTRUMENTATION FACILITY FROM A LESSER-PRIVILEGED STATE - Embodiments of the invention relate to enabling and disabling execution of a run-time instrumentation facility. An instruction for execution by the processor in a lesser privileged state is fetched by the processor. It is determined, by the processor, that the run-time instrumentation facility permits execution of the instruction in the lesser-privileged state and that controls associated with the run-time instrumentation facility are valid. The run-time instrumentation facility is disabled based on the instruction being a run-time instrumentation facility off (RIOFF) instruction. The disabling includes updating a bit in a program status word (PSW) of the processor to indicate that run-time instrumentation data should not be captured by the processor. The run-time instrumentation facility is enabled based on the instruction being a run-time instrumentation facility on (RION) instruction. The enabling includes updating the bit in the PSW to indicate that run-time instrumentation data should be captured by the processor. | 09-19-2013 |
| 20130247014 | MODIFYING RUN-TIME-INSTRUMENTATION CONTROLS FROM A LESSER-PRIVILEGED STATE - Embodiments of the invention relate to modifying run-time-instrumentation controls (MRIC) from a lesser-privileged state. The MRIC instruction is fetched. The MRIC instruction includes the address of a run-time-instrumentation control block (RICCB). The RICCB is fetched based on the address included in the MRIC instruction. The RICCB includes values for modifying a subset of the processor's run-time-instrumentation controls. The subset of run-time-instrumentation controls includes a runtime instrumentation program buffer current address (RCA) of a runtime instrumentation program buffer (RIB) location. The RIB holds run-time-instrumentation information of the events recognized by the processor during program execution. The values of the RICCB are loaded into the run-time-instrumentation controls. Event information is provided to the RIB based on the values that were loaded in the run-time-instrumentation control. | 09-19-2013 |
| 20130290671 | Emulating Execution of a Perform Frame Management Instruction - What is disclosed is a frame management function defined for a machine architecture of a computer system. In one embodiment, a frame management instruction is obtained which identifies a first and second general register. The first general register contains a frame management field having a key field with access-protection bits and a block-size indication. If the block-size indication indicates a large block then an operand address of a large block of data is obtained from the second general register. The large block of data has a plurality of small blocks each of which is associated with a corresponding storage key having a plurality of storage key access-protection bits. If the block size indication indicates a large block, the storage key access-protection bits of each corresponding storage key of each small block within the large block is set with the access-protection bits of the key field. | 10-31-2013 |
| 20130326256 | GENERATING MONOTONICALLY INCREASING TOD VALUES IN A MULTIPROCESSOR SYSTEM - Generating monotonically increasing time-of-day values in a multiprocessor system is provided. Synchronization impulses are received by a processor of the multiprocessor system, and an execution of a read instruction of a time-of-day value within a processor of the processors is refused, if the execution of the read instruction of the time-of-day value is requested after a predefined time after a synchronization impulse of the synchronization impulses, and if a trigger signal, indicative of new data received by a related memory system, has been received after the predefined time, wherein the memory system is external to the processor. | 12-05-2013 |
| 20130339325 | CONSTRAINED TRANSACTION EXECUTION - Constrained transactional processing is provided. A constrained transaction is initiated by execution of a Transaction Begin constrained instruction. The constrained transaction has a number of restrictions associated therewith. Absent violation of a restriction, the constrained transaction is to complete. If an abort condition is encountered, the transaction is re-executed starting at the Transaction Begin instruction. Violation of a restriction may cause an interrupt. | 12-19-2013 |
| 20130339326 | TRANSACTION BEGIN/END INSTRUCTIONS - A TRANSACTION BEGIN instruction and a TRANSACTION END instruction are provided. The TRANSACTION BEGIN instruction causes either a constrained or nonconstrained transaction to be initiated, depending on a field of the instruction. A constrained transaction has one or more restrictions associated therewith, while a nonconstrained transaction is not limited in the manner of a constrained transaction. The TRANSACTION END instruction ends the transaction started by the TRANSACTION BEGIN instruction. | 12-19-2013 |
| 20130339327 | FACILITATING TRANSACTION COMPLETION SUBSEQUENT TO REPEATED ABORTS OF THE TRANSACTION - Processing of transactions within a computing environment is facilitated by taking actions to increase the chances of successfully executing a transaction. A counter is maintained that provides a count of how often a transaction has aborted. The counter increments the count each time the transaction is aborted, and it is reset to zero upon successful completion of the transaction or an interruption leading to no more re-executions of the transaction. If the count reaches a threshold value, then an interrupt is presented and transaction execution is unsuccessful. However, before the count reaches the threshold, a number of actions may be taken to increase the chances of successfully executing the transaction. These actions include actions to be performed within the processor executing the transaction, and/or actions to be performed against conflicting processors. | 12-19-2013 |
| 20130339328 | SELECTIVELY CONTROLLING INSTRUCTION EXECUTION IN TRANSACTIONAL PROCESSING - Execution of instructions in a transactional environment is selectively controlled. A TRANSACTION BEGIN instruction initiates a transaction and includes controls that selectively indicate whether certain types of instructions are permitted to execute within the transaction. The controls include one or more of an allow access register modification control and an allow floating point operation control. | 12-19-2013 |
| 20130339329 | TRANSACTIONAL PROCESSING - A transaction is initiated via a transaction begin instruction. During execution of the transaction, the transaction may abort. If the transaction aborts, a determination is made as to the type of transaction. Based on the transaction being a first type of transaction, resuming execution at the transaction begin instruction, and based on the transaction being a second type, resuming execution at an instruction following the transaction begin instruction. Regardless of transaction type, resuming execution includes restoring one or more registers specified in the transaction begin instruction and discarding transactional stores. For one type of transaction, the nonconstrained transaction, the resuming includes storing information in a transaction diagnostic block. | 12-19-2013 |
| 20130339330 | FACILITATING TRANSACTION COMPLETION SUBSEQUENT TO REPEATED ABORTS OF THE TRANSACTION - Processing of transactions within a computing environment is facilitated by taking actions to increase the chances of successfully executing a transaction. A counter is maintained that provides a count of how often a transaction has aborted. The counter increments the count each time the transaction is aborted, and it is reset to zero upon successful completion of the transaction or an interruption leading to no more re-executions of the transaction. If the count reaches a threshold value, then an interrupt is presented and transaction execution is unsuccessful. However, before the count reaches the threshold, a number of actions may be taken to increase the chances of successfully executing the transaction. These actions include actions to be performed within the processor executing the transaction, and/or actions to be performed against conflicting processors. | 12-19-2013 |
| 20130339561 | PROGRAM EVENT RECORDING WITHIN A TRANSACTIONAL ENVIRONMENT - A transaction is initiated within a computing environment, and based on detecting a program event recording event, an interrupt is presented for the transaction. Subsequent to the interrupt, one or more controls are set to inhibit presentation of another interrupt based on detecting another PER event. Thereafter, the transaction is re-executed and PER events detected during execution of the transaction are ignored. | 12-19-2013 |
| 20130339562 | PROGRAM EVENT RECORDING WITHIN A TRANSACTIONAL ENVIRONMENT - A transaction is initiated within a computing environment, and based on detecting a program event recording event, an interrupt is presented for the transaction. Subsequent to the interrupt, one or more controls are set to inhibit presentation of another interrupt based on detecting another PER event. Thereafter, the transaction is re-executed and PER events detected during execution of the transaction are ignored. | 12-19-2013 |
| 20130339627 | MONITORING A VALUE IN STORAGE WITHOUT REPEATED STORAGE ACCESS - A technique is provided for monitoring a value without repeated storage access. A processing circuit processes an instruction of a program that specifies a memory address of a memory location to be monitored. The processing circuit configures a monitor station for monitoring the memory location. The memory location includes a state descriptor for the program. The processing circuit receives a cross-invalidate request from a memory controller. The cross-invalidate request indicates to the monitor station that content of the memory location has been changed by another processing circuit. | 12-19-2013 |
| 20130339630 | MONITORING A VALUE IN STORAGE WITHOUT REPEATED STORAGE ACCESS - A technique is provided for monitoring a value without repeated storage access. A processing circuit processes an instruction of a program that specifies a memory address of a memory location to be monitored. The processing circuit configures a monitor station for monitoring the memory location. The memory location includes a state descriptor for the program. The processing circuit receives a cross-invalidate request from a memory controller. The cross-invalidate request indicates to the monitor station that content of the memory location has been changed by another processing circuit. | 12-19-2013 |
| 20130339642 | SAVING/RESTORING SELECTED REGISTERS IN TRANSACTIONAL PROCESSING - A TRANSACTION BEGIN instruction begins execution of a transaction and includes a general register save mask having bits, that when set, indicate registers to be saved in the event the transaction is aborted. At the beginning of the transaction, contents of the registers are saved in memory not accessible to the program, and if the transaction is aborted, the saved contents are copied to the registers. | 12-19-2013 |
| 20130339669 | NONTRANSACTIONAL STORE INSTRUCTION - A NONTRANSACTIONAL STORE instruction, executed in transactional execution mode, performs stores that are retained, even if a transaction associated with the instruction aborts. The stores include user-specified information that may facilitate debugging of an aborted transaction. | 12-19-2013 |
| 20130339672 | Next Instruction Access Intent Instruction - Executing a Next Instruction Access Intent instruction by a computer. The processor obtains an access intent instruction indicating an access intent. The access intent is associated with an operand of a next sequential instruction. The access intent indicates usage of the operand by one or more instructions subsequent to the next sequential instruction. The computer executes the access intent instruction. The computer obtains the next sequential instruction. The computer executes the next sequential instruction, which comprises based on the access intent, adjusting one or more cache behaviors for the operand of the next sequential instruction. | 12-19-2013 |
| 20130339673 | INTRA-INSTRUCTIONAL TRANSACTION ABORT HANDLING - Embodiments relate to intra-instructional transaction abort handling. An aspect includes using an emulation routine to execute an instruction within a transaction. The instruction includes at least one unit of operation. The transaction effectively delays committing stores to memory until the transaction has completed successfully. After receiving an abort indication, emulation of the instruction is terminated prior to completing the execution of the instruction. The instruction is terminated after the emulation routine completes any previously initiated unit of operation of the instruction. | 12-19-2013 |
| 20130339674 | RESTRICTED INSTRUCTIONS IN TRANSACTIONAL EXECUTION - Restricted instructions are prohibited from execution within a transaction. There are classes of instructions that are restricted regardless of type of transaction: constrained or nonconstrained. There are instructions only restricted in constrained transactions, and there are instructions that are selectively restricted for given transactions based on controls specified on instructions used to initiate the transactions. | 12-19-2013 |
| 20130339675 | RANDOMIZED TESTING WITHIN TRANSACTIONAL EXECUTION - Task specific diagnostic controls are provided to facilitate the debugging of certain types of abort conditions. The diagnostic controls may be set to cause transactions to be selectively aborted, allowing a transaction to drive its abort handler routine for testing purposes. The controls include, for instance, a transaction diagnostic scope and a transaction diagnostic control. The transaction diagnostic scope indicates when the transaction diagnostic control is to be applied, and the transaction diagnostic control indicates whether transactions are to selectively aborted. | 12-19-2013 |
| 20130339676 | TRANSACTION ABORT INSTRUCTION - A TRANSACTION ABORT instruction is used to abort a transaction that is executing in a computing environment. The TRANSACTION ABORT instruction includes at least one field used to specify a user-defined abort code that indicates the specific reason for aborting the transaction. Based on executing the TRANSACTION ABORT instruction, a condition code is provided that indicates whether re-execution of the transaction is recommended. | 12-19-2013 |
| 20130339680 | NONTRANSACTIONAL STORE INSTRUCTION - A NONTRANSACTIONAL STORE instruction, executed in transactional execution mode, performs stores that are retained, even if a transaction associated with the instruction aborts. The stores include user-specified information that may facilitate debugging of an aborted transaction. | 12-19-2013 |
| 20130339684 | RESTRICTING PROCESSING WITHIN A PROCESSOR TO FACILITATE TRANSACTION COMPLETION - Processing of transactions within a computing environment is facilitated by taking actions to increase the chances of successfully executing a transaction. A counter is maintained that provides a count of how often a transaction has aborted. The counter increments the count each time the transaction is aborted, and it is reset to zero upon successful completion of the transaction or an interruption leading to no more re-executions of the transaction. If the count reaches a threshold value, then an interrupt is presented and transaction execution is unsuccessful. However, before the count reaches the threshold, a number of actions may be taken to increase the chances of successfully executing the transaction. These actions include actions to be performed within the processor executing the transaction, and/or actions to be performed against conflicting processors. | 12-19-2013 |
| 20130339685 | RESTRICTED INSTRUCTIONS IN TRANSACTIONAL EXECUTION - Restricted instructions are prohibited from execution within a transaction. There are classes of instructions that are restricted regardless of type of transaction: constrained or nonconstrained. There are instructions only restricted in constrained transactions, and there are instructions that are selectively restricted for given transactions based on controls specified on instructions used to initiate the transactions. | 12-19-2013 |
| 20130339687 | PROCESSOR ASSIST FACILITY - An operation is provided to signal a processor that action is to be taken to facilitate execution of a transaction that has aborted one or more times. The operation is specified within an instruction or is itself an instruction. The instruction is executed based on detecting an abort of the transactions, and includes a field indicating how many times the transaction has aborted. The processor uses this information to determine what action is to be taken. | 12-19-2013 |
| 20130339690 | TRANSACTIONAL EXECUTION BRANCH INDICATIONS - Transactional execution branch indications are placed into one or more transaction diagnostic blocks when a transaction is aborted. Each branch indication specifies whether a branch was taken, as a result of executing a branch instruction within the transaction. As the transaction executes and a branch instruction is encountered, a branch indication is set in a vector indicating whether the branch was taken. Then, if the transaction aborts, the indicators are stored in one or more transaction diagnostic blocks providing a branch history usable in diagnosing the failure. | 12-19-2013 |
| 20130339691 | BRANCH PREDICTION PRELOADING - Embodiments relate to branch prediction preloading. An aspect includes a system for branch prediction preloading. The system includes an instruction cache and branch target buffer (BTB) coupled to a processing circuit, the processing circuit configured to perform a method. The method includes fetching a plurality of instructions in an instruction stream from the instruction cache, and decoding a branch prediction preload instruction in the instruction stream. An address of a predicted branch instruction is determined based on the branch prediction preload instruction. A predicted target address is determined based on the branch prediction preload instruction. A mask field is identified in the branch prediction preload instruction, and a branch instruction length is determined based on the mask field. Based on executing the branch prediction preload instruction, the BTB is preloaded with the address of the predicted branch instruction, the branch instruction length, the branch type, and the predicted target address. | 12-19-2013 |
| 20130339696 | SELECTIVELY BLOCKING BRANCH INSTRUCTION PREDICTION - Embodiments relate to selectively blocking branch instruction predictions. An aspect includes a computer system for performing selective branch prediction. The system includes memory and a processor, and the system is configured to perform a method. The method includes detecting a branch-prediction blocking instruction in a stream of instructions and blocking branch prediction of a predetermined number of branch instructions following the branch-prediction blocking instruction based on the detecting the branch-prediction blocking instruction. | 12-19-2013 |
| 20130339697 | BRANCH PREDICTION PRELOADING - Embodiments relate to branch prediction preloading. A method for branch prediction preloading includes fetching a plurality of instructions in an instruction stream, and decoding a branch prediction preload instruction in the instruction stream. The method also includes determining, by a processing circuit, an address of a predicted branch instruction based on the branch prediction preload instruction, and determining, by the processing circuit, a predicted target address of the predicted branch instruction based on the branch prediction preload instruction. The method further includes identifying a mask field in the branch prediction preload instruction, and determining, by the processing circuit, a branch instruction length of the predicted branch instruction based on the mask field. Based on executing the branch prediction preload instruction, a branch target buffer is preloaded with the address of the predicted branch instruction, the branch instruction length, and the predicted target address associated with the predicted branch instruction. | 12-19-2013 |
| 20130339702 | PROGRAM INTERRUPTION FILTERING IN TRANSACTIONAL EXECUTION - Program exception conditions cause a transaction to abort and typically result in an interruption in which the operating system obtains control. A program interruption filtering control is provided to selectively present the interrupt. That is, the interrupt from the program exception condition may or may not be presented depending at least on the program interruption filtering control and a transaction class associated with the program exception condition. The program interruption filtering control is provided by a TRANSACTION BEGIN instruction. | 12-19-2013 |
| 20130339703 | RESTRICTING PROCESSING WITHIN A PROCESSOR TO FACILITATE TRANSACTION COMPLETION - Processing of transactions within a computing environment is facilitated by taking actions to increase the chances of successfully executing a transaction. A counter is maintained that provides a count of how often a transaction has aborted. The counter increments the count each time the transaction is aborted, and it is reset to zero upon successful completion of the transaction or an interruption leading to no more re-executions of the transaction. If the count reaches a threshold value, then an interrupt is presented and transaction execution is unsuccessful. However, before the count reaches the threshold, a number of actions may be taken to increase the chances of successfully executing the transaction. These actions include actions to be performed within the processor executing the transaction, and/or actions to be performed against conflicting processors. | 12-19-2013 |
| 20130339704 | SAVING/RESTORING SELECTED REGISTERS IN TRANSACTIONAL PROCESSING - A TRANSACTION BEGIN instruction begins execution of a transaction and includes a general register save mask having bits, that when set, indicate registers to be saved in the event the transaction is aborted. At the beginning of the transaction, contents of the registers are saved in memory not accessible to the program, and if the transaction is aborted, the saved contents are copied to the registers. | 12-19-2013 |
| 20130339705 | RANDOMIZED TESTING WITHIN TRANSACTIONAL EXECUTION - Task specific diagnostic controls are provided to facilitate the debugging of certain types of abort conditions. The diagnostic controls may be set to cause transactions to be selectively aborted, allowing a transaction to drive its abort handler routine for testing purposes. The controls include, for instance, a transaction diagnostic scope and a transaction diagnostic control. The transaction diagnostic scope indicates when the transaction diagnostic control is to be applied, and the transaction diagnostic control indicates whether transactions are to selectively aborted. | 12-19-2013 |
| 20130339706 | PROCESSOR ASSIST FACILITY - An operation is provided to signal a processor that action is to be taken to facilitate execution of a transaction that has aborted one or more times. The operation is specified within an instruction or is itself an instruction. The instruction is executed based on detecting an abort of the transactions, and includes a field indicating how many times the transaction has aborted. The processor uses this information to determine what action is to be taken. | 12-19-2013 |
| 20130339707 | SELECTIVELY CONTROLLING INSTRUCTION EXECUTION IN TRANSACTIONAL PROCESSING - Execution of instructions in a transactional environment is selectively controlled. A TRANSACTION BEGIN instruction initiates a transaction and includes controls that selectively indicate whether certain types of instructions are permitted to execute within the transaction. The controls include one or more of an allow access register modification control and an allow floating point operation control. | 12-19-2013 |
| 20130339708 | PROGRAM INTERRUPTION FILTERING IN TRANSACTIONAL EXECUTION - Program exception conditions cause a transaction to abort and typically result in an interruption in which the operating system obtains control. A program interruption filtering control is provided to selectively present the interrupt. That is, the interrupt from the program exception condition may or may not be presented depending at least on the program interruption filtering control and a transaction class associated with the program exception condition. The program interruption filtering control is provided by a TRANSACTION BEGIN instruction. | 12-19-2013 |
| 20130339709 | TRANSACTION ABORT INSTRUCTION - A TRANSACTION ABORT instruction is used to abort a transaction that is executing in a computing environment. The TRANSACTION ABORT instruction includes at least one field used to specify a user-defined abort code that indicates the specific reason for aborting the transaction. Based on executing the TRANSACTION ABORT instruction, a condition code is provided that indicates whether re-execution of the transaction is recommended. | 12-19-2013 |
| 20130339796 | TRANSACTIONAL EXECUTION BRANCH INDICATIONS - Transactional execution branch indications are placed into one or more transaction diagnostic blocks when a transaction is aborted. Each branch indication specifies whether a branch was taken, as a result of executing a branch instruction within the transaction. As the transaction executes and a branch instruction is encountered, a branch indication is set in a vector indicating whether the branch was taken. Then, if the transaction aborts, the indicators are stored in one or more transaction diagnostic blocks providing a branch history usable in diagnosing the failure. | 12-19-2013 |
| 20130339804 | TRANSACTION DIAGNOSTIC BLOCK - When an abort of a transaction occurs, a determination is made as to whether diagnostic information is to be stored in one or more transaction diagnostic blocks (TDBs). There are different types of transaction diagnostic blocks to accept diagnostic information depending on the type of abort and other considerations. As examples, there are a program-specified TDB in which information is stored if a valid TDB address is provided in a transaction begin instruction; a program interruption TDB, which is stored into when the program is aborted due to an interruption; and a program interception TDB, which is stored into when an abort results in an interception. | 12-19-2013 |
| 20130339806 | TRANSACTION DIAGNOSTIC BLOCK - When an abort of a transaction occurs, a determination is made as to whether diagnostic information is to be stored in one or more transaction diagnostic blocks (TDBs). There are different types of transaction diagnostic blocks to accept diagnostic information depending on the type of abort and other considerations. As examples, there are a program-specified TDB in which information is stored if a valid TDB address is provided in a transaction begin instruction; a program interruption TDB, which is stored into when the program is aborted due to an interruption; and a program interception TDB, which is stored into when an abort results in an interception. | 12-19-2013 |
| 20130339960 | TRANSACTION BEGIN/END INSTRUCTIONS - A TRANSACTION BEGIN instruction and a TRANSACTION END instruction are provided. The TRANSACTION BEGIN instruction causes either a constrained or nonconstrained transaction to be initiated, depending on a field of the instruction. The TRANSACTION END instruction ends the transaction started by the TRANSACTION BEGIN instruction. | 12-19-2013 |
| 20130339961 | TRANSACTIONAL PROCESSING - A transaction is initiated via a transaction begin instruction. During execution of the transaction, the transaction may abort. If the transaction aborts, a determination is made as to the type of transaction. Based on the transaction being a first type of transaction, resuming execution at the transaction begin instruction, and based on the transaction being a second type, resuming execution at an instruction following the transaction begin instruction. Regardless of transaction type, resuming execution includes restoring one or more registers specified in the transaction begin instruction and discarding transactional stores. For one type of transaction, the nonconstrained transaction, the resuming includes storing information in a transaction diagnostic block. | 12-19-2013 |
| 20130339962 | TRANSACTION ABORT PROCESSING - A transaction executing within a computing environment ends prior to completion; i.e., execution is aborted. Pursuant to aborting execution, a hardware transactional execution CPU mode is exited, and one or more of the following is performed: restoring selected registers; committing nontransactional stores on abort; branching to a transaction abort program status word specified location; setting a condition code and/or abort code; and/or preserving diagnostic information. | 12-19-2013 |
| 20130339963 | TRANSACTION ABORT PROCESSING - A transaction executing within a computing environment ends prior to completion; i.e., execution is aborted. Pursuant to aborting execution, a hardware transactional execution CPU mode is exited, and one or more of the following is performed: restoring selected registers; committing nontransactional stores on abort; branching to a transaction abort program status word specified location; setting a condition code and/or abort code; and/or preserving diagnostic information. | 12-19-2013 |
| 20130339967 | CONSTRAINED TRANSACTION EXECUTION - Constrained transactional processing is provided. A constrained transaction is initiated by execution of a Transaction Begin constrained instruction. The constrained transaction has a number of restrictions associated therewith. Absent violation of a restriction, the constrained transaction is to complete. If an abort condition is encountered, the transaction is re-executed starting at the Transaction Begin instruction. Violation of a restriction may cause an interrupt. | 12-19-2013 |
| 20130346697 | MULTILEVEL CACHE SYSTEM - Fetching a cache line into a plurality of caches of a multilevel cache system. The multilevel cache system includes at least a first cache, a second cache on a next higher level and a memory, the first cache being arranged to hold a subset of information of the second cache, the second cache being arranged to hold a subset of information of a next higher level cache or memory if no higher level cache exists. A fetch request is sent from one cache to the next cache in the multilevel cache system. The cache line is fetched in a particular state into one of the caches, and in another state into at least one of the other caches. | 12-26-2013 |
| 20140059321 | Load Page Table Entry Address Instruction Execution Based on an Address Tralsnation Format Control Field - What is provided is a load page table entry address function defined for a machine architecture of a computer system. In one embodiment, a machine instruction is obtained which contains an opcode indicating that a load page table entry address function is to be performed. The machine instruction contains an M field, a first field identifying a first general register, and a second field identifying a second general register. Based on the contents of the M field, an initial origin address of a hierarchy of address translation tables having at least one segment table is obtained. Based on the obtained initial origin address, dynamic address translation is performed until a page table entry is obtained. The page table entry address is saved in the identified first general register. | 02-27-2014 |
| 20140082293 | Store Buffer for Transactional Memory - Provided are techniques for handling a store buffer in conjunction with a processor, the store buffer comprising a free list; a merge window; and an evict list; and logic, for, upon receipt of a T_STORE operation, comparing a first address associated with the T_STORE operation with a plurality of addresses associated with previous T_STORE operations, wherein the previous T_STORE operations are part of the same transaction as the T_STORE operation and the entries corresponding to the previous T_STORE operations are stored in the merge window; in response to a match between the first address and a second address, associated with a second T_STORE operation, of the plurality of addresses, merging a first entry corresponding to the first T_STORE operation with a second entry corresponding to the second T_STORE operation; and consolidating results associated with the first T_STORE operation with results associated with the second T_STORE operation. | 03-20-2014 |
| 20140115295 | DYNAMIC ADDRESS TRANSLATION WITH FETCH PROTECTION IN AN EMULATED ENVIRONMENT - What is provided is an enhanced dynamic address translation facility. In one embodiment, a virtual address to be translated is first obtained and an initial origin address of a translation table of the hierarchy of translation tables is obtained. Based on the obtained initial origin, a segment table entry is obtained. The segment table entry is configured to contain a format control and access validity fields. If the format control and access validity fields are enabled, the segment table entry further contains an access control field, a fetch protection field, and a segment-frame absolute address. Store operations are permitted only if the access control field matches a program access key provided by any one of a Program Status Word or an operand of a program instruction being emulated. Fetch operations are permitted if the program access key associated with the virtual address is equal to the segment access control field or the fetch protection field is not enabled. | 04-24-2014 |
| 20140115306 | Next Instruction Access Intent Instruction - Executing a Next Instruction Access Intent instruction by a computer. The processor obtains an access intent instruction indicating an access intent. The access intent is associated with an operand of a next sequential instruction. The access intent indicates usage of the operand by one or more instructions subsequent to the next sequential instruction. The computer executes the access intent instruction. The computer obtains the next sequential instruction. The computer executes the next sequential instruction, which comprises based on the access intent, adjusting one or more cache behaviors for the operand of the next sequential instruction. | 04-24-2014 |
| 20140181463 | Dynamic Address Translation with Translation Table Entry Format Control for Identifying Format of the Translation Table Entry - An enhanced dynamic address translation facility is provided. In one embodiment, a virtual address to be translated and an initial origin address of a translation table of the hierarchy of translation tables are obtained. An index portion of the virtual address is used to reference an entry in the translation table. If a format control field contained in the translation table entry is enabled, the table entry contains a frame address of a large block of data of at least 1M byte in size. The frame address is then combined with an offset portion of the virtual address to form the translated address of a small 4K byte block of data in main storage or memory. | 06-26-2014 |
| 20140188452 | Emulation of a Dynamic Address Translation With Change Record Override on a Machine of Another Architecture - A translation table entry contains a change recording override field for controlling whether a change bit is to be set on a store or not. Each 4K byte block of main storage has an associated storage key comprising a change bit. The change recording override field controls whether change bit of the storage key associated with the desired 4K byte block of main storage is set to 1 for a store operation. | 07-03-2014 |
| 20140208040 | Creating a Program Product or System for Executing an Instruction for Pre-Fetching Data and Releasing Cache Lines - Systems and Program Products are created to execute a prefetch data machine instruction having an M field performs a function on a cache line of data specifying an address of an operand. The operation comprises either prefetching a cache line of data from memory to a cache or reducing the access ownership of store and fetch or fetch only of the cache line in the cache or a combination thereof. The address of the operand is either based on a register value or the program counter value pointing to the prefetch data machine instruction. | 07-24-2014 |
| 20140208066 | VECTOR GENERATE MASK INSTRUCTION - A Vector Generate Mask instruction. For each element in the first operand, a bit mask is generated. The mask includes bits set to a selected value starting at a position specified by a first field of the instruction and ending at a position specified by a second field of the instruction. | 07-24-2014 |
| 20140208067 | VECTOR ELEMENT ROTATE AND INSERT UNDER MASK INSTRUCTION - A Vector Element Rotate and Insert Under Mask instruction. Each element of a second operand of the instruction is rotated in a specified direction by a specified number of bits. For each bit in a third operand of the instruction that is set to one, the corresponding bit of the rotated elements in the second operand replaces the corresponding bit in a first operand of the instruction. | 07-24-2014 |
| 20140208086 | VECTOR EXCEPTION CODE - Vector exception handling is facilitated. A vector instruction is executed that operates on one or more elements of a vector register. When an exception is encountered during execution of the instruction, a vector exception code is provided that indicates a position within the vector register that caused the exception. The vector exception code also includes a reason for the exception. | 07-24-2014 |
| 20140223137 | STORING A SYSTEM-ABSOLUTE ADDRESS (SAA) IN A FIRST LEVEL TRANSLATION LOOK-ASIDE BUFFER (TLB) - Embodiments relate to a method, system and computer program product for storing a system-absolute address (SAA) in a first level look-aside buffer (TLB). In one embodiment, the system includes a central processor including the TLB and general purpose registers (GPRS). The TLB is configured for storing the SAA. The central processor is configured for issuing a load system-absolute address (LSAA) instruction. The system includes a translation unit that is in communication with the TLB of the central processor. The system is configured to perform a method including determining, based on the LSAA instruction being issued, whether the SAA is stored in the TLB. The method includes sending a translation request to the translation unit from the central processor based on the SAA not being stored in the TLB. The method includes determining the SAA by the translation unit based on receiving the translation request. | 08-07-2014 |
| 20140310475 | ATOMIC EXECUTION OVER ACCESSES TO MULTIPLE MEMORY LOCATIONS IN A MULTIPROCESSOR SYSTEM - A method and central processing unit supporting atomic access of shared data by a sequence of memory access operations. A processor status flag is reset. A processor executes, subsequent to the setting of the processor status flag, a sequence of program instructions with instructions accessing a subset of shared data contained within its local cache. During execution of the sequence of program instructions and in response to a modification by another processor of the subset of shared data, the processor status flag is set. Subsequent to the executing the sequence of program instructions and based upon the state of the processor status flag, either a first program processing or a second program processing is executed. In some examples the first program processing includes storing results data into the local cache and the second program processing includes discarding the results data. | 10-16-2014 |
| 20140325167 | Invalidating a Range of Two or More Translation Table Entries and Instruction Therefore - An instruction is provided to perform invalidation of an instruction specified range of segment table entries or region table entries. The instruction can be implemented by software emulation, hardware, firmware or some combination thereof. | 10-30-2014 |
| 20150019814 | Extract Target Cache Attribute Facility and Instruction Therefore - A facility and cache machine instruction of a computer architecture for specifying a target cache cache-level and a target cache attribute of interest for obtaining a cache attribute of one or more target caches. The requested cache attribute of the target cache(s) is saved in a register. | 01-15-2015 |
| 20150039868 | INTRA-INSTRUCTIONAL TRANSACTION ABORT HANDLING - Embodiments relate to intra-instructional transaction abort handling. An aspect includes using an emulation routine to execute an instruction within a transaction. The instruction includes at least one unit of operation. The transaction effectively delays committing stores to memory until the transaction has completed successfully. After receiving an abort indication, emulation of the instruction is terminated prior to completing the execution of the instruction. The instruction is terminated after the emulation routine completes any previously initiated unit of operation of the instruction. | 02-05-2015 |
| 20150052336 | SELECTIVELY CONTROLLING INSTRUCTION EXECUTION IN TRANSACTIONAL PROCESSING - Execution of instructions in a transactional environment is selectively controlled. A TRANSACTION BEGIN instruction initiates a transaction and includes controls that selectively indicate whether certain types of instructions are permitted to execute within the transaction. The controls include one or more of an allow access register modification control and an allow floating point operation control. | 02-19-2015 |
| 20150052337 | SELECTIVELY CONTROLLING INSTRUCTION EXECUTION IN TRANSACTIONAL PROCESSING - Execution of instructions in a transactional environment is selectively controlled. A TRANSACTION BEGIN instruction initiates a transaction and includes controls that selectively indicate whether certain types of instructions are permitted to execute within the transaction. The controls include one or more of an allow access register modification control and an allow floating point operation control. | 02-19-2015 |
| 20150088929 | COMPARING SETS OF CHARACTER DATA HAVING TERMINATION CHARACTERS - Multiple sets of character data having termination characters are compared using parallel processing and without causing unwarranted exceptions. Each set of character data to be compared is loaded within one or more vector registers. In particular, in one embodiment, for each set of character data to be compared, an instruction is used that loads data in a vector register to a specified boundary, and provides a way to determine the number of characters loaded. Further, an instruction is used to find the index of the first delimiter character, i.e., the first zero or null character, or the index of unequal characters. Using these instructions, a location of the end of one of the sets of data or a location of an unequal character is efficiently provided. | 03-26-2015 |
| 20150089205 | CONVERT FROM ZONED FORMAT TO DECIMAL FLOATING POINT FORMAT - Machine instructions, referred to herein as a long Convert from Zoned instruction (CDZT) and extended Convert from Zoned instruction (CXZT), are provided that read EBCDIC or ASCII data from memory, convert it to the appropriate decimal floating point format, and write it to a target floating point register or floating point register pair. Further, machine instructions, referred to herein as a long Convert to Zoned instruction (CZDT) and extended Convert to Zoned instruction (CZXT), are provided that convert a decimal floating point (DFP) operand in a source floating point register or floating point register pair to EBCDIC or ASCII data and store it to a target memory location. | 03-26-2015 |
| 20150089206 | CONVERT TO ZONED FORMAT FROM DECIMAL FLOATING POINT FORMAT - Machine instructions, referred to herein as a long Convert from Zoned instruction (CDZT) and extended Convert from Zoned instruction (CXZT), are provided that read EBCDIC or ASCII data from memory, convert it to the appropriate decimal floating point format, and write it to a target floating point register or floating point register pair. Further, machine instructions, referred to herein as a long Convert to Zoned instruction (CZDT) and extended Convert to Zoned instruction (CZXT), are provided that convert a decimal floating point (DFP) operand in a source floating point register or floating point register pair to EBCDIC or ASCII data and store it to a target memory location. | 03-26-2015 |
