Patent application number | Description | Published |
20150036414 | SHARED-GATE VERTICAL-TFT FOR VERTICAL BIT LINE ARRAY - A non-volatile storage device comprises: a substrate; a monolithic three dimensional array of memory cells; word lines connected to the memory cells; global bit lines; vertical bit lines connected to the memory cells; and a plurality of double gated vertically oriented select devices. The double gated vertically oriented select devices are connected to the vertical bit lines and the global bit lines so that when the double gated vertically oriented select devices are activated the vertical bit lines are in communication with the global bit lines. Each double gated vertically oriented select device has two gates that are offset from each other with respect to distance to the substrate. Both gates for the double gated vertically oriented select device need be in an “on” condition for the double gated vertically oriented select devices to be activated. | 02-05-2015 |
20150179254 | MITIGATING DISTURB EFFECTS FOR NON-VOLATILE MEMORY - A method includes adjusting a counter value to indicate an access operation to a first portion of a non-volatile memory. The access operation is an erase operation or a write operation. The adjusted counter value indicates that a number of access operations to the first portion have been performed since an access operation to a second portion of the non-volatile memory has been performed. The method also includes selectively initiating a remedial action to the second portion in response to a comparison of the number of access operations to a threshold. | 06-25-2015 |
20150179260 | SYSTEMS AND METHODS OF SHAPING DATA - A method of shaping data includes receiving data represented as a first set of bits, where each bit of the first set of bits corresponds to a logical value. A first write current to write a first logical value to a storage element is less than a second write current to write a second logical value to the storage element. The method also includes applying a shaping operation to generate a second set of bits, where a proportion of bits having the first logical value is larger for the second set of bits than for the first set of bits. The method also includes writing the second set of bits to the memory. | 06-25-2015 |
20150287459 | Methods For Programming ReRAM Devices - A programming technique for a set of resistance-switching memory cells such as ReRAM cell involves programming the low resistance cells to the high resistance state (in a reset process) early in a programming operation, before programming the high resistance cells to the low resistance state (in a set process), to minimize losses due to leakage currents. The reset process can be performed in one or more phases. In some cases, a current limit is imposed which limits the number of cells which can be reset at the same time. Initially, the cells which are to be reset and set are identified by comparing a logical value of their current resistance state to a logical value of write data. If there is a match, the cell is not programmed. If there is not a match, the cell is programmed. | 10-08-2015 |
20160093372 | READING RESISTIVE RANDOM ACCESS MEMORY BASED ON LEAKAGE CURRENT - A data storage device includes a resistive random access memory (ReRAM). The data storage device includes read circuitry coupled to a storage element of the ReRAM. The read circuitry is configured to read a data value from the storage element, during a read operation, based on a read current sensed during a first phase of the reading operation and a leakage current sensed during a second phase of the reading operation. The data storage device also includes a controller coupled to the read circuitry. The controller is configured to provide an input value to an error correction coding (ECC) decoder, where the input value includes a hard bit value and a soft bit value. The hard bit value corresponds to the data value, and the soft bit value is at least partially based on the leakage current. | 03-31-2016 |
20160093373 | APPARATUS AND METHODS FOR SENSING HARD BIT AND SOFT BITS - A method is provided for reading a memory cell of a nonvolatile memory system. The method includes generating a hard bit and N soft bits for the memory cell in a total time corresponding to a single read latency period and N+1 data transfer times. | 03-31-2016 |
20160093374 | METHODS AND APPARATUS FOR VERTICAL CROSS POINT RE-RAM ARRAY BIAS CALIBRATION - Methods for operating a non-volatile storage system are described. The non-volatile storage system includes a plurality of bit lines, a plurality of word line combs each comprising a plurality of word lines, and a plurality of resistance-switching memory elements. Each resistance-switching memory element is coupled between one of the bit lines and one of the word lines. The method includes calibrating a plurality of bias voltages for the word lines and bit lines based on estimates of data values stored in the resistance-switching memory elements. | 03-31-2016 |
20160109926 | MODIFIED WRITE PROCESS BASED ON A POWER CHARACTERISTIC FOR A DATA STORAGE DEVICE - A data storage device includes a memory die. The memory die includes a resistive memory. A method includes determining a power characteristic associated with performing a write process to write data to the resistive memory. The method further includes initiating a modified write process in response to detecting that the power characteristic satisfies a threshold. | 04-21-2016 |
20160111150 | DUAL POLARITY READ OPERATION - A data storage device includes a memory die and a controller coupled to the memory die. The memory die includes a resistive memory and read/write circuitry configured to determine a first hard bit value and a second hard bit value of a storage element of the resistive memory. The first hard bit value and the second hard bit value are determined using opposite polarity read voltages. The controller is configured to perform error correction with respect to data read from the resistive memory. | 04-21-2016 |