Patent application number | Description | Published |
20090032961 | SEMICONDUCTOR DEVICE HAVING A LOCALLY ENHANCED ELECTROMIGRATION RESISTANCE IN AN INTERCONNECT STRUCTURE - By forming an alloy in a highly localized manner at a transition or contact area between a via and a metal line, the probability of forming an electromigration-induced shallow void may be significantly reduced, while not unduly affecting the overall electrical resistivity of the metal line. In one illustrative embodiment, an electroless deposition process may provide the alloy-forming species on the exposed metal region on the basis of an electroless plating process. | 02-05-2009 |
20090140431 | HYBRID CONTACT STRUCTURE WITH LOW ASPECT RATIO CONTACTS IN A SEMICONDUCTOR DEVICE - By forming the first metallization layer of a semiconductor device as a dual damascene structure, the contact elements may be formed on the basis of a significantly reduced aspect ratio, thereby enhancing process robustness and also improving electrical performance of the contact structure. | 06-04-2009 |
20090243116 | REDUCING PATTERNING VARIABILITY OF TRENCHES IN METALLIZATION LAYER STACKS WITH A LOW-K MATERIAL BY REDUCING CONTAMINATION OF TRENCH DIELECTRICS - By forming a protection layer prior to the application of the planarization layer during a dual damascene strategy for first patterning vias and then trenches, enhanced etch fidelity may be accomplished. In other aspects disclosed herein, via openings and trenches may be patterned in separate steps, which may be accomplished by different etch behaviors of respective dielectric materials and/or the provision of an appropriate etch stop layer, while filling the via opening and the trench with a barrier material and a highly conductive metal may be achieved in a common fill sequence. Hence, the via opening may be formed on the basis of a reduced aspect ratio, while nevertheless providing a highly efficient overall process sequence. | 10-01-2009 |
20090246951 | METHOD FOR PATTERNING A METALLIZATION LAYER BY REDUCING RESIST STRIP INDUCED DAMAGE OF THE DIELECTRIC MATERIAL - By forming a hardmask layer in combination with one or more cap layers, undue exposure of a sensitive dielectric material to resist stripping etch ambients may be reduced and integrity of the hardmask may also be maintained so that the trench etch process may be performed with a high degree of etch selectivity during the patterning of openings in a metallization layer of a semiconductor device. | 10-01-2009 |
20090294898 | MICROSTRUCTURE DEVICE INCLUDING A METALLIZATION STRUCTURE WITH SELF-ALIGNED AIR GAPS BETWEEN CLOSELY SPACED METAL LINES - Air gaps may be provided in a self-aligned manner with sub-lithography resolution between closely spaced metal lines of sophisticated metallization systems of semiconductor devices by recessing the dielectric material in the vicinity of the metal lines and forming respective sidewall spacer elements. Thereafter, the spacer elements may be used as an etch mask so as to define the lateral dimension of a gap on the basis of the corresponding air gaps, which may then be obtained by depositing a further dielectric material. | 12-03-2009 |
20090298279 | METHOD FOR REDUCING METAL IRREGULARITIES IN ADVANCED METALLIZATION SYSTEMS OF SEMICONDUCTOR DEVICES - In a manufacturing sequence for forming metallization levels of semiconductor devices, out-gassing of volatile components after an etch process may be initiated immediately after the etch process, thereby reducing the probability of creating contaminants in other substrates and transport carriers during transport activities. Consequently, the defect rate of deposition-related irregularities in the metallization level may be reduced. | 12-03-2009 |
20100052134 | 3-D INTEGRATED SEMICONDUCTOR DEVICE COMPRISING INTERMEDIATE HEAT SPREADING CAPABILITIES - In a three-dimensional chip configuration, a heat spreading material may be positioned between adjacent chips and also between a chip and a carrier substrate, thereby significantly enhancing heat dissipation capability. Furthermore, appropriately sized and positioned through holes in the heat spreading material may enable electrical chip-to-chip connections, while responding thermally conductive connectors may extend to the heat sink without actually contacting the corresponding chips. | 03-04-2010 |
20100052181 | USING A CAP LAYER IN METALLIZATION SYSTEMS OF SEMICONDUCTOR DEVICES AS A CMP AND ETCH STOP LAYER - During the manufacture of advanced metallization systems, a dielectric cap layer formed on a sensitive dielectric material may be partially maintained during a CMP process for removing excess metal, thereby avoiding the necessity for depositing a dedicated etch stop material, as may be required in conventional approaches when substantially completely consuming the dielectric cap material during the CMP process. Hence, reduced process complexity and/or enhanced flexibility may be accomplished in combination with increased integrity of the low-k dielectric material. | 03-04-2010 |
20100055903 | ENHANCING STRUCTURAL INTEGRITY OF LOW-K DIELECTRICS IN METALLIZATION SYSTEMS OF SEMICONDUCTOR DEVICES BY USING A CRACK SUPPRESSING MATERIAL LAYER - During the formation of metallization layers of sophisticated semiconductor devices, the damaging of sensitive dielectric materials, such as ULK materials, may be significantly reduced during a CMP process by applying a compressive stress level. This may be accomplished, in some illustrative embodiments, by forming a compressively stressed cap layer on the ULK material, thereby suppressing the propagation of micro cracks into the ULK material. | 03-04-2010 |
20100133699 | MICROSTRUCTURE DEVICE INCLUDING A METALLIZATION STRUCTURE WITH AIR GAPS FORMED COMMONLY WITH VIAS - Air gaps may be formed in a metallization layer of a microstructure device on the basis of a patterning sequence in which respective via openings are also formed. Thereafter, the via openings and the air gaps may be closed by a deposition process without significantly affecting the interior of the corresponding openings. Thereafter, the further processing may be continued by forming respective trenches while maintaining integrity of the covered air gaps. Thus, the relative permittivity of the interlayer dielectric material may be efficiently reduced without adding additional process complexity. | 06-03-2010 |
20100133700 | PERFORMANCE ENHANCEMENT IN METALLIZATION SYSTEMS OF MICROSTRUCTURE DEVICES BY INCORPORATING GRAIN SIZE INCREASING METAL FEATURES - In a sophisticated metallization system, enhanced electromigration behavior may be accomplished by incorporating electromigration barriers into metal lines after a given distance, which may be accomplished by providing an increased width in order to obtain an enhanced average grain size in the intermediate metal regions of increased lateral width. Consequently, the electromigration induced material diffusion may encounter an overall increased grain size along the entire depth of the metal lines, thereby resulting in a significantly reduced electromigration effect and thus enhanced reliability of the critical metal lines. | 06-03-2010 |
20100164121 | METALLIZATION SYSTEM OF A SEMICONDUCTOR DEVICE COMPRISING EXTRA-TAPERED TRANSITION VIAS - In a metallization system of a semiconductor device, a transition via may be provided with an increased degree of tapering by modifying a corresponding etch sequence. For example, the resist mask for forming the via opening may be eroded once or several times in order to increase the lateral size of the corresponding mask opening. Due to the pronounced degree of tapering, enhanced deposition conditions may be accomplished during the subsequent electrochemical deposition process for commonly filling the via opening and a wide trench connected thereto. | 07-01-2010 |
20100197133 | METHOD OF FORMING A METALLIZATION SYSTEM OF A SEMICONDUCTOR DEVICE BY USING A HARD MASK FOR DEFINING THE VIA SIZE - In a “via first/trench last” approach for forming metal lines and vias in a metallization system of a semiconductor device, a combination of two hard masks may be used, wherein the desired lateral size of the via openings may be defined on the basis of spacer elements, thereby resulting in significantly less demanding lithography conditions compared to conventional approaches. | 08-05-2010 |
20100219527 | METALLIZATION SYSTEM OF A SEMICONDUCTOR DEVICE INCLUDING METAL PILLARS HAVING A REDUCED DIAMETER AT THE BOTTOM - In a metallization system of a complex semiconductor device, metal pillars, such as copper pillars, may be formed in a nail-like configuration in order to reduce the maximum mechanical stress acting on the metallization system while providing a required contact surface for connecting to the package substrate. The nail-like configuration may be obtained on the basis of appropriately configured resist masks. | 09-02-2010 |
20100219534 | MICROSTRUCTURE DEVICE INCLUDING A METALLIZATION STRUCTURE WITH SELF-ALIGNED AIR GAPS AND REFILLED AIR GAP EXCLUSION ZONES - In a sophisticated metallization system, self-aligned air gaps may be provided in a locally selective manner by using a radiation sensitive material for filling recesses or for forming therein the metal regions. Consequently, upon selectively exposing the radiation sensitive material, a selective removal of exposed or non-exposed portions may be accomplished, thereby resulting in a highly efficient overall manufacturing flow. | 09-02-2010 |
20100301486 | HIGH-ASPECT RATIO CONTACT ELEMENT WITH SUPERIOR SHAPE IN A SEMICONDUCTOR DEVICE FOR IMPROVING LINER DEPOSITION - Contact elements of sophisticated semiconductor devices may be formed by lithographical patterning, providing a spacer element for defining the final critical width in combination with increasing a width of the contact opening prior to depositing the spacer material. The width may be increased, for instance by ion sputtering, thereby resulting in superior process conditions during the deposition of a contact metal. As a result, the probability of generating contact failures for contact elements having critical dimensions of approximately 50 nm and less may be significantly reduced. | 12-02-2010 |
20100301489 | MICROSTRUCTURE DEVICE INCLUDING A METALLIZATION STRUCTURE WITH SELF-ALIGNED AIR GAPS FORMED BASED ON A SACRIFICIAL MATERIAL - In a sophisticated metallization system of a semiconductor device, air gaps may be formed in a self-aligned manner on the basis of a sacrificial material, such as a carbon material, which is deposited after the patterning of a dielectric material for forming therein a via opening. Consequently, superior process conditions during the patterning of the via opening and the sacrificial material in combination with a high degree of flexibility in selecting appropriate materials for the dielectric layer and the sacrificial layer may provide superior uniformity and device characteristics. | 12-02-2010 |
20110049640 | SUPERIOR FILL CONDITIONS IN A REPLACEMENT GATE APPROACH BY USING A TENSILE STRESSED OVERLAYER - In a replacement gate approach for forming high-k metal gate electrodes in semiconductor devices, a tapered configuration of the gate openings may be accomplished by using a tensile stressed dielectric material provided laterally adjacent to the gate electrode structure. Consequently, superior deposition conditions may be achieved while the tensile stress component may be efficiently used for the strain engineering in one type of transistor. Furthermore, an additional compressively stressed dielectric material may be applied after providing the replacement gate electrode structures. | 03-03-2011 |
20110104867 | FABRICATING VIAS OF DIFFERENT SIZE OF A SEMICONDUCTOR DEVICE BY SPLITTING THE VIA PATTERNING PROCESS - When forming a complex metallization system in which vias of different lateral size have to be provided, a split patterning sequence may be applied. For this purpose, a lithography process may be specifically designed for the critical via openings and a subsequent second patterning process may be applied for forming the vias of increased lateral dimensions, while the critical vias are masked. In this manner, superior process conditions may be established for each of the patterning sequences. | 05-05-2011 |
20110104880 | CORNER ROUNDING IN A REPLACEMENT GATE APPROACH BASED ON A SACRIFICIAL FILL MATERIAL APPLIED PRIOR TO WORK FUNCTION METAL DEPOSITION - In a replacement gate approach, a top area of a gate opening has a superior cross-sectional shape which is accomplished on the basis of a plasma assisted etch process or an ion sputter process. During the process, a sacrificial fill material protects sensitive materials, such as a high-k dielectric material and a corresponding cap material. Consequently, the subsequent deposition of a work function adjusting material layer may not result in a surface topography which may result in a non-reliable filling-in of the electrode metal. In some illustrative embodiments, the sacrificial fill material may also be used as a deposition mask for avoiding the deposition of the work function adjusting metal in certain gate openings in which a different type of work function adjusting species is required. | 05-05-2011 |
20110201135 | Method of Reducing Contamination by Providing a Removable Polymer Protection Film During Microstructure Processing - By providing a protective layer in an intermediate manufacturing stage, an increased surface protection with respect to particle contamination and surface corrosion may be achieved. In some illustrative embodiments, the protective layer may be used during an electrical test procedure, in which respective contact portions are contacted through the protective layer, thereby significantly reducing particle contamination during a respective measurement process. | 08-18-2011 |
20110212616 | METALLIZATION SYSTEM OF A SEMICONDUCTOR DEVICE COMPRISING ROUNDED INTERCONNECTS FORMED BY HARD MASK ROUNDING - In sophisticated metallization systems, vertical contacts and metal lines may be formed on the basis of a dual inlaid strategy, wherein an edge rounding or corner rounding may be applied to the trench hard mask prior to forming the via openings on the basis of a self-aligned via trench concept. Consequently, self-aligned interconnect structures may be obtained, while at the same time providing superior fill conditions during the deposition of barrier materials and conductive fill materials. | 09-01-2011 |
20110241167 | Semiconductor Device Comprising a Capacitor in the Metallization System Formed by a Hard Mask Patterning Regime - Capacitors may be formed in the metallization system of semiconductor devices without requiring a modification of the hard mask patterning process for forming vias and trenches in the dielectric material of the metallization layer under consideration. To this end, a capacitor opening is formed prior to actually forming the hard mask for patterning the trench and via openings, wherein the hard mask material may thus preserve integrity of the capacitor opening and may remain as a portion of the electrode material after filling in the conductive material for the metal lines, vias and the capacitor electrode. | 10-06-2011 |
20110291196 | Self-Aligned Multiple Gate Transistor Formed on a Bulk Substrate - Three-dimensional transistors in a bulk configuration may be formed on the basis of gate openings or gate trenches provided in a mask material. Hence, self-aligned semiconductor fins may be efficiently patterned in the underlying active region in a portion defined by the gate opening, while other gate openings may be efficiently masked, in which planar transistors are to be provided. After patterning the semiconductor fins and adjusting the effective height thereof, the further processing may be continued on the basis of process techniques that may be commonly applied to the planar transistors and the three-dimensional transistors. | 12-01-2011 |
20120153366 | Semiconductor Device Comprising Self-Aligned Contact Bars and Metal Lines With Increased Via Landing Regions - When forming metal lines of the metal zero level, a reduced bottom width and an increased top width may be achieved by using appropriate patterning regimes, for instance using a spacer structure after forming an upper trench portion with a top width, or forming the lower portion of the trenches and subsequently applying a further mask and etch regime in which the top width is implemented. In this manner, metal lines connecting to self-aligned contact bars may be provided so as to exhibit a bottom width of 20 nm and less, while the top width may allow reliable contact to any vias of the metallization system. | 06-21-2012 |
20120223388 | SUPERIOR FILL CONDITIONS IN A REPLACEMENT GATE APPROACH BY USING A TENSILE STRESSED OVERLAYER - In a replacement gate approach for forming high-k metal gate electrodes in semiconductor devices, a tapered configuration of the gate openings may be accomplished by using a tensile stressed dielectric material provided laterally adjacent to the gate electrode structure. Consequently, superior deposition conditions may be achieved while the tensile stress component may be efficiently used for the strain engineering in one type of transistor. Furthermore, an additional compressively stressed dielectric material may be applied after providing the replacement gate electrode structures. | 09-06-2012 |
20130130498 | REDUCING PATTERNING VARIABILITY OF TRENCHES IN METALLIZATION LAYER STACKS WITH A LOW-K MATERIAL BY REDUCING CONTAMINATION OF TRENCH DIELECTRICS - Generally, the present disclosure is related to various techniques that may be used for forming metallization systems in a highly efficient manner by filling via openings and trenches in a common fill process, while reducing negative effects during the patterning of the via opening and the trenches. One illustrative method disclosed herein includes, among other things, forming a via opening in a first dielectric material of a metallization layer of a semiconductor device. Moreover, a second dielectric material is formed above the first dielectric material, wherein the second dielectric material fills the via opening. Furthermore, the method also includes forming a trench in the second dielectric material so as to connect to the via opening, and filling the trench and the via opening with a metal in a common fill process. | 05-23-2013 |
20130154018 | SEMICONDUCTOR DEVICE COMPRISING SELF-ALIGNED CONTACT BARS AND METAL LINES WITH INCREASED VIA LANDING REGIONS - Disclosed herein is an illustrative semiconductor device that includes a transistor having drain and source regions and a gate electrode structure. The disclosed semiconductor device also includes a contact bar formed in a first dielectric material that connects to one of the drain and source regions and includes a first conductive material, the contact bar extending along a width direction of the transistor. Moreover, the illustrative device further includes, among other things, a conductive line formed in a second dielectric material, the conductive line including an upper portion having a top width extending along a length direction of the transistor and a lower portion having a bottom width extending along the length direction that is less than the top width of the upper portion, wherein the conductive line connects to the contact bar and includes a second conductive material that differs from the first conductive material. | 06-20-2013 |