Patent application number | Description | Published |
20080239945 | PERIPHERAL COMPONENT SWITCH HAVING AUTOMATIC LINK FAILOVER - Disclosed are a PCI switch assembly, having automatic link failover, and a computer system including that switch assembly. The switch assembly comprises first and second interconnected, peripheral component switches. Each of the these switches has first and second primary ports and a plurality of secondary ports. The switch assembly has a normal mode and a failover mode. In the normal mode, each switch routes data through the switch to the secondary ports of the switch. In the failover mode, a failover path is defined and data are routed from the first switch to the second switch and then to one of the secondary ports of the second switch. The second switch detects a predefined fail condition, and changes the switch assembly from the normal mode to the failover mode in response to detecting the predefined fail condition. | 10-02-2008 |
20080240134 | MULTI-NODE, PERIPHERAL COMPONENT SWITCH FOR A COMPUTER SYSTEM - Disclosed are a PCI-Express multi-node switch assembly and a computer system including the switch assembly. This switch assembly comprises first and second interconnected PCI-Express switches, each of said switches having first and second primary ports and a plurality of secondary ports. The first primary ports of the switches are adapted to be connected to a host processor unit, and the second primary ports of the switches are connected to each other to transfer signals between the switches. In the preferred embodiment, the first primary ports of the switches are connected to first and second nodes of a host processor unit. The first and second switches receive functional traffic from said first and second node, respectively. Also, the first and second switches are able to receive configuration information from the second and first nodes, respectively, over the interconnection between the switches. | 10-02-2008 |
20090059916 | METHOD, SYSTEM, AND APPARATUS FOR RELIABLE DATA PACKET RECOVERY IN A LINK LAYER OF A DATA CENTER ETHERNET NETWORK - Dropped packets are recovered in a link layer of a Data Center Ethernet (DCE) network. Data packets for transmission are stored in a replay buffer. Each data packet includes a header having a field including data indicating that the data packet is formatted for reliable recovery at the link layer. The data packets are transmitted to a receiver across a link layer in the DCE network. The receiver determines whether a data packet has been dropped. If a data packet has not been dropped, an acknowledgement signal is sent to the transmitter in another data packet across the link layer, indicating that the data packet has been received. If a data packet has been dropped, a non-acknowledgement signal is sent to the transmitter in the other data packet across the link layer, indicating that the data packet has been dropped. In response to receipt of the non-acknowledgement signal or no receipt of an acknowledgement signal after the timeout period, the dropped data packet is retrieved from the replay buffer and is resent to the receiver across the link layer. | 03-05-2009 |
20090073978 | Low Latency Multicast for InfinibandR Host Channel Adapters - A low latency multicasting receive and send apparatus and method comprising low latency receive and send queues, in an InfiniBand® network each destination group of nodes (recipients) is identified by a unique Global ID (GID)+Local ID (LID). Each node whose ports are part of a multicast group identify themselves via a LID which identifies participating ports. When a switch receives such a multicast packet with a multicast LID in the packet's DLID field it replicates the packet to each of the designated ports. Each destination adapter at a receiving node receives the multicast packet and distributes copies of the packet to QPs in the host system that are registered for the multicast address. | 03-19-2009 |
20090073999 | Adaptive Low Latency Receive Queues - A receive queue provided in a computer system holds work completion information and message data together. An InfiniBand hardware adapter sends a single CQE+message data to the computer system that includes the completion information and data. This information is sufficient for the computer system to receive and process the data message, thereby providing a highly scalable low latency receiving mechanism. | 03-19-2009 |
20090077268 | Low Latency Multicast for Infiniband Host Channel Adapters - A low latency multicasting receive and send apparatus and method comprising low latency receive and send queues. In an InfiniBand® network each destination group of nodes (recipients) is identified by a unique Global ID (GID)+Local ID (LID). Each node whose ports are part of a multicast group identify themselves via a LID which identifies participating ports. When a switch receives such a multicast packet with a multicast LID in the packet's DLID field it replicates the packet to each of the designated ports. Each destination adapter at a receiving node receives the multicast packet and distributes copies of the packet to QPs in the host system that are registered for the multicast address. | 03-19-2009 |
20090077567 | Adaptive Low Latency Receive Queues - A receive queue provided in a computer system holds work completion information and message data together. An InfiniBand hardware adapter sends a single CQE+ message data to the computer system that includes the completion Information and data. This information is sufficient for the computer system to receive and process the data message, thereby providing a highly scalable low latency receiving mechanism. | 03-19-2009 |
20090080334 | METHOD, SYSTEM, AND COMPUTER PROGRAM PRODUCT FOR ADAPTIVE CONGESTION CONTROL ON VIRTUAL LANES FOR DATA CENTER ETHERNET ARCHITECTURE - Congestion is adaptively controlled in a data center Ethernet (DCE) network. Packets are received over at least one virtual lane in the DCE network. An absolute or relative packet arrival rate is computed over a time period. The absolute or relative packet arrival rate is compared to at least a first threshold and a second threshold. If the absolute or relative packet arrival rate increases beyond the first threshold, the packet transmission rate is caused to decrease. If the absolute or relative packet arrival rate is less than a second threshold, the packet transmission rate is caused to increase. | 03-26-2009 |
20090086635 | METHOD, SYSTEM, AND APPARATUS FOR FLOW CONTROL MANAGEMENT IN A DATA CENTER ETHERNET NETWORK OVER AN EXTENDED DISTANCE - Flow control in a data center Ethernet (DCE) network is managed between a source node and a destination node separated by an extended distance. An initiation sequence between the source node and the destination node is intercepted. The imitation sequence is for determining buffer credits available for receiving packets in the source node and the destination node. Replies are generated to the source node and the destination node indicating buffer credits available in at least one extended data interface interspersed between the source node and the destination node. The initiation sequence is completed based on the replies from the extended data interface. | 04-02-2009 |
20090086637 | METHOD, SYSTEM, AND APPARATUS FOR ACCELERATING RESOLUTION OF NETWORK CONGESTION - The response time for resolving network traffic congestion is accelerated in a Data Center Ethernet (DCE) network. A data packet is received at a node in the network. Congestion of the data packet at the node is detected, and a backward congestion notification signal for the data packet is generated. A packet injection rate is adapted based on at least one of the backward congestion notification signal generated by the node and another backward congestion notification signal. | 04-02-2009 |
20090157961 | TWO-SIDED, DYNAMIC CACHE INJECTION CONTROL - A method, system, and computer program product for two-sided, dynamic cache injection control are provided. An I/O adapter generates an I/O transaction in response to receiving a request for the transaction. The transaction includes an ID field and a requested address. The adapter looks up the address in a cache translation table stored thereon, which includes mappings between addresses and corresponding address space identifiers (ASIDs). The adapter enters an ASID in the ID field when the requested address is present in the cache translation table. IDs corresponding to device identifiers, address ranges and pattern strings may also be entered. The adapter sends the transaction to one of an I/O hub and system chipset, which in turn, looks up the ASID in a table stored thereon and injects the requested address and corresponding data in a processor complex when the ASID is present in the table, indicating that the address space corresponding to the ASID is actively running on a processor in the complex. The ASIDs are dynamically determined and set in the adapter during execution of an application in the processor complex. | 06-18-2009 |
20090157962 | CACHE INJECTION USING CLUSTERING - A method and system for cache injection using clustering are provided. The method includes receiving an input/output (I/O) transaction at an input/output device that includes a system chipset or input/output (I/O) hub. The I/O transaction includes an address. The method also includes looking up the address in a cache block indirection table. The cache block indirection table includes fields and entries for addresses and cluster identifiers (IDs). In response to a match resulting from the lookup, the method includes multicasting an injection operation to processor units identified by the cluster ID. | 06-18-2009 |
20090157966 | CACHE INJECTION USING SPECULATION - A method, system, and computer program product for cache injection using speculation are provided. The method includes creating a cache line indirection table at an input/output (I/O) hub, which includes fields and entries for addresses, processor ID, and cache type and includes cache level line limit fields. The method also includes setting cache line limits to the CLL fields and receiving a stream of contiguous addresses at the table. For each address in the stream, the method includes: looking up the address in the table; if the address is present in the table, inject the cache line corresponding to the address in the processor complex; if the address is not present in the table, search limit values from the lowest level cache to the highest level cache; and inject addresses not present in the table to the cache hierarchy of the processor last injected from the contiguous address stream. | 06-18-2009 |
20090157977 | DATA TRANSFER TO MEMORY OVER AN INPUT/OUTPUT (I/O) INTERCONNECT - A method, system, and computer program product for data transfer to memory over an input/output (I/O) interconnect are provided. The method includes reading a mailbox stored on an I/O adapter in response to a request to initiate an I/O transaction. The mailbox stores a directive that defines a condition under which cache injection for data values in the I/O transaction will not be performed. The method also includes embedding a hint into the I/O transaction when the directive in the mailbox matches data received in the request, and executing the I/O transaction. The execution of the I/O transaction causes a system chipset or I/O hub for a processor receiving the I/O transaction, to directly store the data values from the I/O transaction into system memory and to suppress the cache injection of the data values into a cache memory upon presence of the hint in a header of the I/O transaction. | 06-18-2009 |
20090157978 | TARGET COMPUTER PROCESSOR UNIT (CPU) DETERMINATION DURING CACHE INJECTION USING INPUT/OUTPUT (I/O) ADAPTER RESOURCES - A method, system, and computer program product for target computer processor unit (CPU) determination during cache injection using input/output (I/O) adapter resources are provided. The method includes storing locations of cache lines for pinned or affinity scheduled processes in a table on an input/output (I/O) adapter. The method also includes setting a cache injection hint in an input/output (I/O) transaction when an address in the I/O transaction is found in the table. The cache injection hint is set for performing direct cache injection. The method further includes entering a central processing unit (CPU) identifier and cache type in the I/O transaction, and updating a cache by injecting data values of the I/O transaction into the cache as determined by the CPU identifier and the cache type associated with the address in the table. | 06-18-2009 |
20090157979 | TARGET COMPUTER PROCESSOR UNIT (CPU) DETERMINATION DURING CACHE INJECTION USING INPUT/OUTPUT (I/O) HUB/CHIPSET RESOURCES - A method, system, and computer program product for target computer processor unit (CPU) determination during cache injection using I/O hub/chipset resources are provided. The method includes creating a cache injection indirection table on the input/output (I/O) hub or chipset. The cache injection indirection table includes fields for address or address range, CPU identifier, and cache type. In response to receiving an input/output (I/O) transaction, the hub/chipset reads the address in an address field of the I/O transaction, looks up the address in the cache injection indirection table, and injects the address and data of the I/O transaction to a target cache associated with a CPU as identified in the CPU identifier field when, in response to the look up, the address is present in the address field of the cache injection indirection table. | 06-18-2009 |
20090164684 | Throttling A Point-To-Point, Serial Input/Output Expansion Subsystem Within A Computing System - Methods, systems, and apparatus are disclosed for throttling a point-to-point, serial I/O expansion subsystem within a computing system that include: receiving, by a link configuration module, an external environmental parameter value representing a condition of an environment external to the computing system; determining, by the link configuration module, a link configuration of a communication link for an I/O adapter in a point-to-point, serial I/O expansion subsystem within the computing system in dependence upon the external environmental parameter value; and configuring, by the link configuration module, the communication link for the I/O adapter in dependence upon the link configuration. | 06-25-2009 |
20090198863 | TRANSPARENT PCI-BASED MULTI-HOST SWITCH - A transparent PCI-based multi-host switch. A switch is configured with multiple north facing ports to couple the switch to multiple hosts. The multi-host switch can be included in a variety of switch configurations, including configurations having one multi-host switch, configurations having multiple multi-host switches, and configurations including one or more multi-host switches and one or more single host switches. The switch is designed to include controls to accurately route a packet through the switch. | 08-06-2009 |
20090210770 | METHOD, SYSTEM AND COMPUTER PROGRAM PRODUCT FOR END TO END ERROR CHECKING IN ETHERNET - A method for network protocol error correction comprising, generating a data packet including a cycle redundancy check (CRC) field, an end to end error field that remains unchanged as the data packet is sent over a network, for use in performing error detection in one or more field of the data packet, and a flag field associated with the end to end field to indicate that the end to end error field contains error correction data, and sending the data packet over a network via an Ethernet protocol. | 08-20-2009 |
20090213127 | GUIDED ATTACHMENT OF ACCELERATORS TO COMPUTER SYSTEMS - A method of guided attachment of hardware accelerators to slots of a computing system includes dividing a first group of hardware accelerators into a plurality of priority classes, dividing a first group of slots of the computing system into a plurality of hierarchical tiers, and attaching each hardware accelerator of the first group of hardware accelerators to a slot matched to the hardware accelerators based on comparison of a priority class of the hardware accelerator and a hierarchical tier of the slot. | 08-27-2009 |
20090213861 | Reliable Link Layer Packet Retry - Communication over a computer network with a node having a first port with a point-to-point link connection to a second node having a second port. The first port transmits to the second port a reliable link layer (RLL) packet over the link. The RLL packet comprises a first RLL header and a first data packet, the first RLL header preceding the first data packet, the first RLL header comprising an RLL start-of-frame (SOF) character and an RLL packet sequence number (PSN). If the first port receives an RLL acknowledgment control packet from the link, it acknowledges receipt of the first data packet, and the first port does not retain the first data packet in the buffer. If the first port does not receive the RLL acknowledgment packet from the link, acknowledging receipt of the first data packet, the first port re-transmits from the buffer the first data packet. | 08-27-2009 |
20090216518 | EMULATED MULTI-TASKING MULTI-PROCESSOR CHANNELS IMPLEMENTING STANDARD NETWORK PROTOCOLS - A computer program product, apparatus and method for emulating channels in a multi-tasking multi-processor environment, including identifying a plurality of physical channels having an associated physical channel identifier for each of the plurality of physical channels, associating an emulated channel from a plurality of emulated channels for each of the plurality of physical channels, thereby generating a plurality of emulated channels, each of the plurality of emulated channels having a virtual channel identifier, mapping the plurality of emulated channels on a communications link, thereby generating an emulated channel path for each of the plurality of emulated channels, defining a queue pair link buffer from a plurality of queue pair link buffers for each of the emulated channels and increasing a number of queue pair link buffers. | 08-27-2009 |
20090217266 | STREAMING ATTACHMENT OF HARDWARE ACCELERATORS TO COMPUTER SYSTEMS - A method of streaming attachment of hardware accelerators to a computing system includes receiving a stream for processing, identifying a stream handler based on the received stream, activating the identified stream handler, and steering the stream to an associated hardware accelerator. | 08-27-2009 |
20090217275 | PIPELINING HARDWARE ACCELERATORS TO COMPUTER SYSTEMS - A method of pipelining hardware accelerators of a computing system includes associating hardware addresses to at least one processing unit (PU) or at least one logical partition (LPAR) of the computing system, receiving a work request for an associated hardware accelerator address, and queuing the work request for a hardware accelerator using the associated hardware accelerator address. | 08-27-2009 |
20090234974 | PERFORMANCE COUNTERS FOR VIRTUALIZED NETWORK INTERFACES OF COMMUNICATIONS NETWORKS - Performance counters are provided for virtualized network interfaces of communications networks, while minimizing the use of hardware resources. A virtualized network interface includes physical resources, as well as logical resources. Dedicated performance counters are provided for the physical resources of the virtualized network interface, as well as for logical partitions coupled to that interface, while non-dedicated performance counters are provided for the logical resources. This enables the provision of performance counters for virtualized network interfaces, while minimizing hardware resources consumed by those interfaces. | 09-17-2009 |
20090238068 | METHOD, SYSTEM AND COMPUTER PROGRAM PRODUCT INVOLVING CONGESTION AND FAULT NOTIFICATION IN ETHERNET - A method for sending congestion notifications from a node in an Ethernet protocol including, determining whether the node is congested, generating a congestion message including a unique identifier of the node, responsive to determining that the node is congested, and sending the congestion message to a source transmitter. | 09-24-2009 |
20090238211 | METHOD, SYSTEM AND COMPUTER PROGRAM PRODUCT INVOLVING CONGESTION DETECTION IN ETHERNET - A method for determining data packet transmission times in an Ethernet protocol including, receiving a first data packet having a first data packet send time, wherein the first data packet send time is a time the data packet is sent by a source transmitter, subtracting the first data packet send time from a first data packet receive time to yield a first data packet transmission time, wherein the first data packet receive time is the time the data packet is received by a destination receiver, comparing the first data packet transmission time to a third time, determining whether a difference between the first data packet transmission time and the third time exceeds a threshold value, and sending a notification of a transmission delay responsive to determining that the difference between the first data packet transmission time and the third time exceeds the threshold value. | 09-24-2009 |
20090307711 | INTEGRATING COMPUTATION AND COMMUNICATION ON SERVER ATTACHED ACCELERATORS - In a call-return-communicate scheme an OS/hypervisor/inter-partition shared memory usage is replaced by a software abstraction or mailbox router implemented on an accelerator which handles LPAR communication needs, thereby obviating the need to invoke the OS/hypervisor/inter-partition shared memory. By eliminating the need for the OS/hypervisor/shared memory, system latency is reduced by removing communication and hypervisor invocation time. | 12-10-2009 |
20100031272 | SYSTEM AND METHOD FOR LOOSE ORDERING WRITE COMPLETION FOR PCI EXPRESS - A method for managing the protocol of read/write messages in a PCI Express communication link is disclosed. The method comprises maintaining queues of write requests and read requests associated with each of a plurality of request identifications that are contained in a message header, wherein the read requests associated with a request identification are held in abeyance until such time that write requests associated with the request identification are completed. | 02-04-2010 |
20110068957 | DATA COMPRESSION SYSTEM AND ASSOCIATED METHODS - A system to compress an inter-system channel data stream may include a data compression application executing via a computer processor. The system may additionally include a transmit dictionary used by said data compression application to compress an inter-system channel data stream. The system may also include a data decompression application executing via a second computer processor to decompress the inter-system channel data stream. The system may further include a receive dictionary used by said data decompression application to decompress the inter-system channel data stream. | 03-24-2011 |
20110107035 | CROSS-LOGICAL ENTITY ACCELERATORS - A cross-logical entity group is created that includes one or more accelerators to be shared by a plurality of logical entities. Instantiated on the accelerators are functions that are common across multiple logical entities. The functions to be instantiated are determined, for instance, dynamically during run-time. | 05-05-2011 |
20110107066 | CASCADED ACCELERATOR FUNCTIONS - Accelerator functions are cascaded, such that a result of one accelerator function is directly forwarded to another accelerator function, bypassing the processor requesting the functions to be performed. The cascading may be provided during compilation of a program specifying the functions to be performed, but can be dynamically reversed during runtime of the program. | 05-05-2011 |
20110131430 | MANAGING ACCELERATORS OF A COMPUTING ENVIRONMENT - Accelerators of a computing environment are managed in order to optimize energy consumption of the accelerators. To facilitate the management, virtual queues are assigned to the accelerators, and a management technique is used to enqueue specific tasks on the queues for execution by the corresponding accelerators. The management technique considers various factors in determining which tasks to be placed on which virtual queues in order to manage energy consumption of the accelerators. | 06-02-2011 |
20110131580 | MANAGING TASK EXECUTION ON ACCELERATORS - Execution of tasks on accelerator units is managed. The managing includes multi-level grouping of tasks into groups based on defined criteria, including start time of tasks and/or deadline of tasks. The task groups and possibly individual tasks are mapped to accelerator units to be executed. During execution, redistribution of a task group and/or an individual task may occur to optimize a defined energy profile. | 06-02-2011 |
20110320637 | DISCOVERY BY OPERATING SYSTEM OF INFORMATION RELATING TO ADAPTER FUNCTIONS ACCESSIBLE TO THE OPERATING SYSTEM - A tiered discovery capability is employed to obtain attributes regarding adapters of an I/O configuration. The first tier obtains a list of the adapter functions accessible to an operating system; the second tier obtains attributes regarding a selected adapter function of the list of adapter functions; and a third tier obtains common attributes of a group of adapter functions, the group including the selected adapter function. | 12-29-2011 |
20110320638 | ENABLE/DISABLE ADAPTERS OF A COMPUTING ENVIRONMENT - An adapter is enabled for use. The enabling includes assigning one or more address spaces to the adapter, based on a request. For each address space assigned to the adapter, a corresponding device table entry is assigned. When the adapter is no longer needed, it is disabled and the assigned device table entries become available. | 12-29-2011 |
20110320643 | MEASUREMENT FACILITY FOR ADAPTER FUNCTIONS - A measurement facility is provided for capturing and presenting fine-grained usage information for adapter functions in an input/output subsystem. Adapter specific input/output traffic is tracked on a per function basis and the results are dynamically presented to the user. This information is useful for performance tuning, load balancing and usage based charging, as examples. | 12-29-2011 |
20110320644 | RESIZING ADDRESS SPACES CONCURRENT TO ACCESSING THE ADDRESS SPACES - Address spaces are resized concurrent to accessing those address spaces. The size of an address space can be increased or decreased concurrent to performing read or write operations on the address space. Further, cache entries associated with an address space being decreased in size are purged. | 12-29-2011 |
20110320652 | CONTROLLING ACCESS BY A CONFIGURATION TO AN ADAPTER FUNCTION - Access to an input/output adapter by a configuration is controlled. For each requested access to an adapter, checks are made to determine whether the configuration is authorized to access the adapter. If it is not authorized, then access is denied. If it is authorized, but access should be temporarily blocked, then instruction execution is altered to indicate such. If access is permitted, but should be blocked for another reason (other than temporarily), then access is denied. | 12-29-2011 |
20110320653 | SYSTEM AND METHOD FOR ROUTING I/O EXPANSION REQUESTS AND RESPONSES IN A PCIE ARCHITECTURE - A system for implementing non-standard input/output (I/O) adapters in a standardized I/O architecture, comprising an I/O hub communicatively coupled to an I/O bus and a plurality of I/O adapters at I/O adapter addresses, the I/O hub including logic for implementing a method comprising receiving requests from the plurality of I/O adapters, storing the I/O adapter addresses of a requester along with their corresponding target recipient addresses and operation codes, receiving a response from a responder, the response indicating that a request has been completed, determining that the response is in a format other than a format supported by the I/O bus, transforming the response into the format supported by the I/O bus, locating a stored I/O adapter address having a corresponding target recipient address that matches the responder address and a corresponding operation code that matches the responder operation code, and transmitting the response to the stored I/O adapter address. | 12-29-2011 |
20110320662 | IDENTIFICATION OF TYPES OF SOURCES OF ADAPTER INTERRUPTIONS - A source identification facility is provided that enables identification of the one or more types of adapters requesting an interrupt in order to facilitate processing of the interrupt. The adapter types are accessible to the operating system and are used to tailor processing by the operating system of the interrupt. | 12-29-2011 |
20110320663 | CONVERTING A MESSAGE SIGNALED INTERRUPTION INTO AN I/O ADAPTER EVENT NOTIFICATION TO A GUEST OPERATING SYSTEM - One or more message signaled interruption requests from one or more input/output (I/O) adapters are converted to I/O adapter event notifications while retaining the message vector indication. An I/O adapter event notification may be routed and presented to a host or to a guest that the host is executing. To present the notification to the correct host or to the correct guest, various data structures in host and/or guest memory are used. | 12-29-2011 |
20110320664 | CONTROLLING A RATE AT WHICH ADAPTER INTERRUPTION REQUESTS ARE PROCESSED - The conditions under which adapter interruptions are made pending are controlled. Responsive to an interruption being presented to an operating system, subsequent interruptions are suppressed on all central processing units in the configuration. The operating system processes the interruption, including examining and processing indicators of reported events until the operating system discontinues the suppression. This enables the operating system to control the number of pending interruptions and the number of processors processing those interruptions. | 12-29-2011 |
20110320666 | INPUT/OUTPUT (I/O) EXPANSION RESPONSE PROCESSING IN A PERIPHERAL COMPONENT INTERCONNECT EXPRESS (PCIE) ENVIRONMENT - A system for implementing non-standard input/output (I/O) adapters in a standardized I/O architecture, comprising an I/O hub communicatively coupled to an I/O bus and a plurality of I/O adapters, the I/O hub including logic for implementing a method comprising receiving a request from a requester to perform an operation on one of the plurality of I/O adapters. The method further comprising determining that the request is in a format other than a format supported by the I/O bus, determining that the requester requires a completion response for the request, transforming the request into the format supported by the I/O bus, transmitting the request to the I/O adapter, receiving the completion response from the I/O adapter, the completion response comprising an indicator that the request has been completed, the completion response in the format supported by the I/O bus and transmitting the completion response to the requester. | 12-29-2011 |
20110320670 | CONNECTED INPUT/OUTPUT HUB MANAGEMENT - A method for implementing connected input/output (I/O) hub configuration and management includes configuring a first I/O hub in wrap mode with a second I/O hub. The hubs are communicatively coupled via a wrap cable. The method further includes generating data traffic on a computing subsystem that includes the hubs. Generating traffic includes: converting, via the first hub, a request to implement a transaction into an I/O device-readable request packet and transmitting the request packet over the wrap cable; converting, via the second hub, the I/O device-readable (IODR) request packet into a system readable request and transmitting the request over a system bus; converting, via the second hub, the response to an IODR response packet, and transmitting the response packet over the wrap cable; and converting, via the first hub, the IODR response packet into a system readable response packet, and transmitting the response packet over the system bus. | 12-29-2011 |
20110320674 | UPBOUND INPUT/OUTPUT EXPANSION REQUEST AND RESPONSE PROCESSING IN A PCIE ARCHITECTURE - A system for implementing non-standard I/O adapters in a standardized input/output (I/O) architecture, the system comprising an I/O adapter communicatively coupled to an I/O hub via an I/O bus, the I/O adapter communicating in a first protocol, the I/O bus communicating in a second protocol different than the first protocol, and the I/O adapter including logic for implementing a method comprising initiating a first request to perform an operation on a host system, the first request formatted for the first protocol and comprising data required to process the first request, and creating a second request responsive to the first request, the second request comprising a header and formatted according to the second protocol, the creating comprising storing the data required to process the first request in the header of the second request. The method further comprising sending the second request to the host system. | 12-29-2011 |
20110320675 | SYSTEM AND METHOD FOR DOWNBOUND I/O EXPANSION REQUEST AND RESPONSE PROCESSING IN A PCIe ARCHITECTURE - A system for implementing non-standard I/O adapters in a standardized I/O architecture, the system comprising an I/O hub communicatively coupled to an I/O bus and at least one I/O adapter, the I/O hub including logic for implementing a method, the method comprising receiving a request to perform an operation on the I/O adapter from a requester at a requester address, the I/O adapter at a destination address, determining that the request is in a format other than a format supported by the I/O bus, the I/O bus expecting a requester identifier at a first location in a header of the request, reformatting the request into the format supported by the I/O bus, the reformatting comprising storing the requester address, the destination address and an operation code at the first location in the header of the reformatted request, and sending the reformatted request to the I/O adapter. | 12-29-2011 |
20110320703 | ASSOCIATING INPUT/OUTPUT DEVICE REQUESTS WITH MEMORY ASSOCIATED WITH A LOGICAL PARTITION - An address controller includes a bit selector that receives a first portion of a requester id and selects a bit from a vector that identifies whether a requesting function is an SR-IOV device or a standard PCIe device. The controller also includes a selector coupled to the bit selector that forms an output comprised of either a second portion of the RID or a first portion of the address portion based on an input received from the selector and an address control unit that receives the first portion of the RID and the output and determines the LPAR that owns the requesting function based thereon, the address control unit providing the corrected memory request to the memory. | 12-29-2011 |
20110320756 | RUNTIME DETERMINATION OF TRANSLATION FORMATS FOR ADAPTER FUNCTIONS - Various address translation formats are available for use in obtaining system memory addresses for use by requestors, such as adapter functions, in accessing system memory. The particular address translation format to be used by a given requestor is pre-registered in a device table entry associated with that requestor. | 12-29-2011 |
20110320757 | STORE/STORE BLOCK INSTRUCTIONS FOR COMMUNICATING WITH ADAPTERS - Communication with adapters of a computing environment is facilitated. Instructions are provided that explicitly target the adapters. Information provided in an instruction is used to steer the instruction to an appropriate location within the adapter. | 12-29-2011 |
20110320758 | TRANSLATION OF INPUT/OUTPUT ADDRESSES TO MEMORY ADDRESSES - An address provided in a request issued by an adapter is converted to an address directly usable in accessing system memory. The address includes a plurality of bits, in which the plurality of bits includes a first portion of bits and a second portion of bits. The second portion of bits is used to index into one or more levels of address translation tables to perform the conversion, while the first portion of bits are ignored for the conversion. The first portion of bits are used to validate the address. | 12-29-2011 |
20110320759 | MULTIPLE ADDRESS SPACES PER ADAPTER - A plurality of address spaces are assigned to an adapter. To select a particular address space for the adapter, a requestor identifier and address space identifier provided in a request by the adapter are used. Each address space may have a different address translation mechanism associated therewith. | 12-29-2011 |
20110320764 | LOAD INSTRUCTION FOR COMMUNICATING WITH ADAPTERS - Communication with adapters of a computing environment is facilitated. Instructions are provided that explicitly target the adapters. Information provided in an instruction is used to steer the instruction to an appropriate location within the adapter. | 12-29-2011 |
20110320772 | CONTROLLING THE SELECTIVELY SETTING OF OPERATIONAL PARAMETERS FOR AN ADAPTER - An instruction is provided to establish various operational parameters for an adapter. These parameters include adapter interruption parameters, input/output address translation parameters, resetting error indications, setting measurement parameters, and setting an interception control, as examples. The instruction specifies a function information block, which is a program representation of a device table entry used by the adapter, to be used in certain situations in establishing the parameters. A store instruction is also provided that stores the current contents of the function information block. | 12-29-2011 |
20110320860 | MANAGING PROCESSING ASSOCIATED WITH HARDWARE EVENTS - Detection, notification and/or processing of events, such as errors associated with adapters, are facilitated. Hardware detects an event, places one or more adapters in an error state to prevent access to/from the adapters, and notifies the operating system of the event. | 12-29-2011 |
20110320861 | SWITCH FAILOVER CONTROL IN A MULTIPROCESSOR COMPUTER SYSTEM - A system and a method for failover control comprising: maintaining a primary device table entry (DTE) in a first table activated for a first adapter in communication with a first processor node having a first root complex via a first switch assembly and maintaining a secondary DTE in standby for a second adapter in communication with a second processor node having a second root complex via a second switch assembly; maintaining a primary DTE in a second table activated for the second adapter and maintaining a secondary DTE in standby for the first adapter; and upon a failover, updating the secondary DTE in the first table as an active entry for the second adapter and forming a path to enable traffic to route from the second adapter through the second switch assembly over to the first switch assembly and up to the first root complex of the first processor node. | 12-29-2011 |
20110320887 | SCALABLE I/O ADAPTER FUNCTION LEVEL ERROR DETECTION, ISOLATION, AND REPORTING - A system for implementing scalable input/output (I/O) function level error detection, isolation, and reporting, the system comprising, an I/O hub communicatively coupled to a computer processor, system memory and at least one I/O adapter, the at least one I/O adapter include a function and the I/O hub including logic for implementing a method. The method comprising detecting an error in a communication initiated between the function and the system memory, the communication including an I/O request from an application. The method further comprising preventing future communication between the one function and the system memory in response to the detecting. The method additionally comprising notifying the application that the error in communication occurred in response to the detecting. | 12-29-2011 |
20110320892 | MEMORY ERROR ISOLATION AND RECOVERY IN A MULTIPROCESSOR COMPUTER SYSTEM - A system and computer implemented method for isolating errors in a computer system is provided. The method includes receiving a direct memory access (DMA) command to access a computer memory, a read response, or an interrupt; associating the DMA command to access the computer memory, the read response, or the interrupt with a stream identified by a stream identification (ID); detecting a memory error caused by the DMA command in the stream, the memory error resulting in stale data in the computer memory; and isolating the memory error in the stream associated with the stream ID from other streams associated with other stream IDs upon detecting the memory error. | 12-29-2011 |
20110321060 | OPERATING SYSTEM NOTIFICATION OF ACTIONS TO BE TAKEN RESPONSIVE TO ADAPTER EVENTS - Notification of hardware actions to be taken responsive to hardware events is facilitated. An operating system coupled, but external to, the hardware notifies firmware of the hardware action to be taken. | 12-29-2011 |
20110321061 | CONVERTING A MESSAGE SIGNALED INTERRUPTION INTO AN I/O ADAPTER EVENT NOTIFICATION - One or more message signaled interruption requests from one or more input/output (I/O) adapters are converted to I/O adapter event notifications. Each I/O adapter event notification includes the setting of one or more specific indicators in system memory and an interruption request, the first of which results in a pending I/O adapter interruption request. While a request for an I/O adapter interruption is pending, subsequent message signaled interruption requests are converted to I/O adapter event notifications, but do not result in additional requests for I/O adapter interruptions. | 12-29-2011 |
20110321158 | GUEST ACCESS TO ADDRESS SPACES OF ADAPTER - An authorization mechanism allows a host executing a guest operating system to grant permission for the guest to directly access an adapter function's address spaces without host intervention. This access is via instructions implemented based on the architecture of the adapter function. The host also has the capability to intervene in the execution of the instruction, if desired. | 12-29-2011 |
20120198114 | CONVERTING A MESSAGE SIGNALED INTERRUPTION INTO AN I/O ADAPTER EVENT NOTIFICATION TO A GUEST OPERATING SYSTEM - One or more message signaled interruption requests from one or more input/output (I/O) adapters are converted to I/O adapter event notifications while retaining the message vector indication. An I/O adapter event notification may be routed and presented to a host or to a guest that the host is executing. To present the notification to the correct host or to the correct guest, various data structures in host and/or guest memory are used. | 08-02-2012 |
20120213507 | ADAPTOR SYSTEM FOR AN ETHERNET NETWORK - An Ethernet adapter system may include a transmitter to insert a payload type identifier sequence in a generic frame procedure header to indicate that a network is a converged enhanced Ethernet network. The transmitter may insert idle sequences in a stream of data frames transmitted along a link. The system may include a receiver to recognize a condition and to force a loss of synchronization condition on the link that will be converted by the receiver into a loss of light condition. The receiver may scan the transmitted stream of data frames for invalid data frames and introduce a code into the stream of data frames whenever an invalid data frame is detected. | 08-23-2012 |
20120216022 | CONTROLLING THE SELECTIVELY SETTING OF OPERATIONAL PARAMETERS FOR AN ADAPTER - An instruction is provided to establish various operational parameters for an adapter. These parameters include adapter interruption parameters, input/output address translation parameters, resetting error indications, setting measurement parameters, and setting an interception control, as examples. The instruction specifies a function information block, which is a program representation of a device table entry used by the adapter, to be used in certain situations in establishing the parameters. A store instruction is also provided that stores the current contents of the function information block. | 08-23-2012 |
20120221757 | CONVERTING A MESSAGE SIGNALED INTERRUPTION INTO AN I/O ADAPTER EVENT NOTIFICATION - One or more message signaled interruption requests from one or more input/output (I/O) adapters are converted to I/O adapter event notifications. Each I/O adapter event notification includes the setting of one or more specific indicators in system memory and an interruption request, the first of which results in a pending I/O adapter interruption request. While a request for an I/O adapter interruption is pending, subsequent message signaled interruption requests are converted to I/O adapter event notifications, but do not result in additional requests for I/O adapter interruptions. | 08-30-2012 |
20120278503 | ENERGY MANAGEMENT SYSTEM FOR A DATA CENTER NETWORK - An energy management system for a data center network may include a central computer to establish an energy use policy for the computer data center network. The system may also include computer nodes in the computer data center network to receive a packet which is a query that obtains energy information from the nodes and/or a transmission reservation that provides instructions for the energy use policy to be implemented at the computer nodes. The computer nodes may reallocate data traffic on the computer data center network based on the energy use policy to improve energy consumption of the computer data center network. | 11-01-2012 |
20120300611 | Soft Error Recovery for Converged Networks - Detecting and recovering from soft errors in a network comprising a first device. A first device receives a first data packet. Responsive to receiving a second data packet, the first device determines whether the two data packets are identical. Responsive to the determination that the two data packets are not identical, the first device discards the two data packets, and requests retransmission of the two data packets. | 11-29-2012 |
20130067194 | TRANSLATION OF INPUT/OUTPUT ADDRESSES TO MEMORY ADDRESSES - An address provided in a request issued by an adapter is converted to an address directly usable in accessing system memory. The address includes a plurality of bits, in which the plurality of bits includes a first portion of bits and a second portion of bits. The second portion of bits is used to index into one or more levels of address translation tables to perform the conversion, while the first portion of bits are ignored for the conversion. The first portion of bits are used to validate the address. | 03-14-2013 |
20130073759 | UPBOUND INPUT/OUTPUT EXPANSION REQUEST AND RESPONSE PROCESSING IN A PCIE ARCHITECTURE - Embodiments of the invention relate to non-standard I/O adapters in a standardized input/output (I/O) architecture. An aspect of the invention includes initiating a first request to perform an operation on a host system. The first request formatted for a first protocol and including data required to process the first request. A second request is created responsive to the first request, the second request including a header and is formatted according to the second protocol. The creating includes storing the data required to process the first request in the header of the second request. The second request is sent to the host system. | 03-21-2013 |
20130073766 | INPUT/OUTPUT (I/O) EXPANSION RESPONSE PROCESSING IN A PERIPHERAL COMPONENT INTERCONNECT EXPRESS (PCIE) ENVIRONMENT - Embodiments of the invention relate to non-standard input/output (I/O) adapters in a standardized I/O architecture. An aspect of the invention includes implementing non-standard I/O adapters in a standardized I/O architecture. A request is received at an I/O adapter from a requester to perform an operation on one of the I/O adapters. It is determined that the request is in a format other than a format supported by an I/O bus and that the requester requires a completion response for the request. The request is transformed into the format supported by the I/O bus, and is transmitted to the I/O adapter. The completion response is received from the I/O adapter, and includes an indicator that the request has been completed. The completion response is in the format supported by the I/O bus. The completion response is transmitted to the requester. | 03-21-2013 |
20130073767 | INPUT/OUTPUT (I/O) EXPANSION RESPONSE PROCESSING IN A PERIPHERAL COMPONENT INTERCONNECT EXPRESS (PCIE) ENVIRONMENT - A system for implementing non-standard input/output (I/O) adapters in a standardized I/O architecture, comprising an I/O hub communicatively coupled to an I/O bus and a plurality of I/O adapters, the I/O hub including logic for implementing a method comprising receiving a request from a requester to perform an operation on one of the plurality of I/O adapters. The method further comprising determining that the request is in a format other than a format supported by the I/O bus, determining that the requester requires a completion response for the request, transforming the request into the format supported by the I/O bus, transmitting the request to the I/O adapter, receiving the completion response from the I/O adapter, the completion response comprising an indicator that the request has been completed, the completion response in the format supported by the I/O bus and transmitting the completion response to the requester. | 03-21-2013 |
20130086435 | SCALABLE I/O ADAPTER FUNCTION LEVEL ERROR DETECTION, ISOLATION, AND REPORTING - Embodiments of the invention relate to scalable input/output (I/O) function level error detection, isolation, and reporting. An aspect of the invention includes detecting an error in a communication initiated between the function and a system memory, the communication including an I/O request from an application. Future communication is prevented between the one function and the system memory in response to the detecting. The application is notified that the error in communication occurred in response to the detecting. | 04-04-2013 |
20130101284 | ADAPTOR SYSTEM FOR AN ETHERNET NETWORK - An Ethernet adapter system may include a transmitter to insert a payload type identifier sequence in a generic frame procedure header to indicate that a network is a converged enhanced Ethernet network. The transmitter may insert idle sequences in a stream of data frames transmitted along a link. The system may include a receiver to recognize a condition and to force a loss of synchronization condition on the link that will be converted by the receiver into a loss of light condition. The receiver may scan the transmitted stream of data frames for invalid data frames and introduce a code into the stream of data frames whenever an invalid data frame is detected. | 04-25-2013 |
20130114397 | Soft Error Recovery for Converged Networks - Detecting and recovering from soft errors in a network comprising a first device. A first device receives a first data packet. Responsive to receiving a second data packet, the first device determines whether the two data packets are identical. Responsive to the determination that the two data packets are not identical, the first device discards the two data packets, and requests retransmission of the two data packets. | 05-09-2013 |
20130128721 | SYSTEM TO IMPROVE AN ETHERNET NETWORK - A system to improve a Fibre Channel over Convergence Enhanced Ethernet (FCoCEE) network may include a sender in an FCoCEE network in which data packets having different data link layer structures are transmitted by the sender on a single data link. The system may also include a receiver to receive the data packets at the data link layer and to transmit an ACK and/or NAK in response to a sequence number in the data packets. The system may further include a replay buffer to retransmit the data packets where the replay buffer is sized by the length of the data link, data rate of the data link, the ACK and/or NAK processing time at either the sender and/or the receiver, and/or a threshold time for transmission and/or reception of the data packets. | 05-23-2013 |
20130128884 | SYSTEM TO IMPROVE AN ETHERNET NETWORK - A system to improve a Fibre Channel over Convergence Enhanced Ethernet (FCoCEE) network may include a sender in an FCoCEE network in which data packets having different data link layer structures are transmitted by the sender on a single data link. The system may also include a receiver to receive the data packets at the data link layer and to transmit an ACK and/or NAK in response to a sequence number in the data packets. The system may further include a replay buffer to retransmit the data packets where the replay buffer is sized by the length of the data link, data rate of the data link, the ACK and/or NAK processing time at either the sender and/or the receiver, and/or a threshold time for transmission and/or reception of the data packets. | 05-23-2013 |
20140101400 | STORE PERIPHERAL COMPONENT INTERCONNECT (PCI) FUNCTION CONTROLS INSTRUCTION - An instruction is provided that includes an opcode field to identify a store instruction to store in a designated location current values of operational parameters of an adapter function of an adapter; a first field to identify a location, the contents of which include a function handle identifying a handle of the adapter function for which the store instruction is being performed, and an indication of an address space associated with the adapter function identified by the function handle to which the store instruction applies; and a second field to identify the designated location of where a result of the store instruction is to be stored. Execution of the instruction includes obtaining information from a function information block associated with the adapter function; and copying the information from the function information block into the designated location, based on completion of one or more validity checks with one or more predefined results. | 04-10-2014 |
20140129796 | TRANSLATION OF INPUT/OUTPUT ADDRESSES TO MEMORY ADDRESSES - An address provided in a request issued by an adapter is converted to an address directly usable in accessing system memory. The address includes a plurality of bits, in which the plurality of bits includes a first portion of bits and a second portion of bits. The second portion of bits is used to index into one or more levels of address translation tables to perform the conversion, while the first portion of bits are ignored for the conversion. The first portion of bits are used to validate the address. | 05-08-2014 |
20140164644 | ENERGY MANAGEMENT SYSTEM FOR A DATA CENTER NETWORK - An energy management system for a data center network may include a central computer to establish an energy use policy for the computer data center network. The system may also include computer nodes in the computer data center network to receive a packet which is a query that obtains energy information from the nodes and/or a transmission reservation that provides instructions for the energy use policy to be implemented at the computer nodes. The computer nodes may reallocate data traffic on the computer data center network based on the energy use policy to improve energy consumption of the computer data center network. | 06-12-2014 |