Patent application number | Description | Published |
20100165748 | ERASE COMPLETION RECOGNITION - Embodiments include but are not limited to apparatuses and systems including a main memory array, at least one erase status memory cell associated with the main memory array and configured to store a value indicative of an erase completion status of the main memory array, and a control module operatively coupled to the at least one erase status memory cell, the control module configured to perform operations on the main memory array based at least in part on the value stored in the at least one erase status memory cell. Other embodiments may be described and claimed. | 07-01-2010 |
20120033493 | ERASE COMPLETION RECOGNITION - Embodiments include but are not limited to apparatuses and systems including a main memory array, at least one erase status memory cell associated with the main memory array and configured to store a value indicative of an erase completion status of the main memory array, and a control module operatively coupled to the at least one erase status memory cell, the control module configured to perform operations on the main memory array based at least in part on the value stored in the at least one erase status memory cell. Other embodiments may be described and claimed. | 02-09-2012 |
20120075923 | PHASE CHANGE MEMORY STATE DETERMINATION USING THRESHOLD EDGE DETECTION - Subject matter disclosed herein relates to techniques to read a memory cell that involve a threshold edge phenomenon of a reset state of phase change memory. | 03-29-2012 |
20120314491 | SET PULSE FOR PHASE CHANGE MEMORY PROGRAMMING - Subject matter disclosed herein relates to a memory device, and more particularly to a single pulse algorithm for programming a phase change memory. | 12-13-2012 |
20130242650 | SET PULSE FOR PHASE CHANGE MEMORY PROGRAMMING - A memory device and method for programming the memory device, including a method for a melting phase change memory cell by applying an electronic signal at a first value and subsequently decreasing the signal value. The phase change memory cell can be substantially crystallized after the decrease in signal value. | 09-19-2013 |
20140245107 | REARRANGING WRITE DATA TO AVOID HARD ERRORS - This disclosure relates to avoiding a hard error in memory during write time by shifting data to be programmed to memory to mask the hard error. In one implementation, a method of programming data to a memory array includes obtaining error data corresponding to a selected memory cell, shifting a data pattern such that a value to be stored by the selected memory cell matches a value associated with a hard error, and programming the shifted data pattern to memory array such that the value programmed to the selected memory cell matches the value associated with the hard error. | 08-28-2014 |
20150149838 | REARRANGING PROGRAMMING DATA TO AVOID HARD ERRORS - This disclosure relates to avoiding a hard error in memory during write time by shifting data to be programmed to memory to mask the hard error. In one implementation, a method of programming data to a memory array includes obtaining error data corresponding to a selected memory cell, shifting a data pattern such that a value to be stored by the selected memory cell matches a value associated with a hard error, and programming the shifted data pattern to memory array such that the value programmed to the selected memory cell matches the value associated with the hard error. | 05-28-2015 |
20160004595 | SHIFTING READ DATA - This disclosure relates to avoiding a hard error in memory during write time by shifting data to be programmed to memory to mask the hard error. In one implementation, a method of programming data to a memory array includes obtaining error data corresponding to a selected memory cell, shifting a data pattern such that a value to be stored by the selected memory cell matches a value associated with a hard error, and programming the shifted data pattern to memory array such that the value programmed to the selected memory cell matches the value associated with the hard error. | 01-07-2016 |
Patent application number | Description | Published |
20130271167 | CURRENT TESTS FOR I/O INTERFACE CONNECTORS - Current tests for I/O interface connectors are described. In one example a test may include applying a forced energy to a first pin of an interface of a data communications bus of an integrated circuit on a die, sensing the energy caused by the forced energy at a second pin of the interface, and comparing the forced energy and the sensed energy to determine an amount of current leaked by at least a portion of the interface. | 10-17-2013 |
20150084642 | ALTERNATING CURRENT COUPLED ELECTRONIC COMPONENT TEST SYSTEM AND METHOD - This disclosure relates generally to an electrical circuit and method. A capacitive element can be configured to be coupled in series with an electronic package component. A path resistance can be electrically coupled to the capacitive element. A driver can be configured to electrically charge the capacitive element. A voltage detector can be coupled to the capacitive element and configured to identify a condition of the electronic package component based on a measured voltage of the capacitive element. | 03-26-2015 |
20150324265 | TESTING I/O TIMING DEFECTS FOR HIGH PIN COUNT, NON-CONTACT INTERFACES - Indirect testing of multiple I/O interface signal lines concurrently. A system distributes a test data sequence to a group of signal lines. Each signal line receives the test data sequence and checks for errors in receiving the test data sequence at an associated I/O buffer. The system includes an error detection mechanism for each signal line. The system also includes an error detection mechanism for the group of multiple signal lines. If the I/O buffer receives any bit of the test data sequence incorrectly, the signal line error detection indicates an error. The group error detection accumulates pass/fail information for all signal lines in the group. Rather than sending a pass/fail indication on every cycle of the test, the group error detection can count pass/fail information for all signal lines of the group for all bits of the test data sequence and indicate error results after the entire test data is received. | 11-12-2015 |
20150377967 | DUTY CYCLE BASED TIMING MARGINING FOR I/O AC TIMING - Testing I/O (input/output) eye width for an interface with an inverted modulated strobe or clock signal. An I/O interface includes multiple signal lines, each with a hardware I/O buffer with timing characteristics. A system generates a strobe signal with a triggering edge that triggers a write, and a trailing edge that is modulated by adjusting the duty cycle of the strobe signal. The system inverts the modulated strobe signal to generate an inverted strobe signal, wherein the inverted strobe signal has a modulated triggering edge generated from inverting the modulated trailing edge. The device under test writes test data based on the triggering edge of the original strobe signal and reads test data based on the triggering edge of the inverted strobe signal. | 12-31-2015 |
Patent application number | Description | Published |
20090046519 | METHOD, DEVICE AND SYSTEM FOR CONFIGURING A STATIC RANDOM ACCESS MEMORY CELL FOR IMPROVED PERFORMANCE - A computer-implemented method of configuring a static random access memory (SRAM) bit cell for operation, an adaptive biasing device and semiconductor wafer testing system. In one embodiment, the method includes: (1) determining a performance characteristic of the SRAM bit cell on a wafer, (2) comparing the performance characteristic to a target and (3) configuring biasing circuitry associated with the SRAM bit cell based on the comparing. | 02-19-2009 |
20140298068 | DISTRIBUTION OF POWER GATING CONTROLS FOR HIERARCHICAL POWER DOMAINS - An integrated circuit device includes a first module disposed within a first power domain, a second module disposed in a second power domain that is a sub-domain of the first power domain, first power gating logic, and second power gating logic. The first power gating logic generates a first virtual power supply for the first module. The second power gating logic is powered by the first virtual power supply for generating a second virtual power supply for the second power domain. | 10-02-2014 |
20150022218 | TECHNIQUES AND CIRCUITS FOR TESTING A VIRTUAL POWER SUPPLY AT AN INTEGRATED CIRCUIT DEVICE - A power grid provides power to one or more modules of an integrated circuit device via a virtual power supply signal. A test module is configured to respond to assertion of a test signal so that, when the power grid is working properly and is not power gated, an output of the test module matches the virtual power supply. When the power grid is not working properly, the output of the test module is a fixed logic signal that does not vary based on the power gated state of the one or more modules. | 01-22-2015 |
20150026406 | SIZE ADJUSTING CACHES BY WAY - A size of a cache of a processing system is adjusted by ways, such that each set of the cache has the same number of ways. The cache is a set-associative cache, whereby each set includes a number of ways. In response to defined events at the processing system, a cache controller changes the number of ways of each set of the cache. For example, in response to a processor core indicating that it is entering a period of reduced activity, the cache controller can reduce the number of ways available in each set of the cache. | 01-22-2015 |
20150026407 | SIZE ADJUSTING CACHES BASED ON PROCESSOR POWER MODE - As a processor enters selected low-power modes, a cache is flushed of data by writing data stored at the cache to other levels of a memory hierarchy. The flushing of the cache allows the size of the cache to be reduced without suffering an additional performance penalty of writing the data at the reduced cache locations to the memory hierarchy. Accordingly, when the cache exits the selected low-power modes, it is sized to a minimum size by setting the number of ways of the cache to a minimum number. In response to defined events at the processing system, a cache controller changes the number of ways of each set of the cache. | 01-22-2015 |
20150117582 | PREDICTIVE PERIODIC SYNCHRONIZATION USING PHASE-LOCKED LOOP DIGITAL RATIO UPDATES - Embodiments are described for a method and system of enabling updates from a clock controller to be sent directly to a predictive synchronizer to manage instant changes in frequency between transmit and receive clock domains, comprising receiving receive and transmit reference frequencies from a phase-locked loop circuit, receiving receive and transmit constant codes from a controller coupled to the phase-locked loop circuit, obtaining a time delay factor to accommodate phase detection between the transmit and receive clock domains, and calculating new detection interval and frequency information using the time delay factor, the reference frequencies, and the constant codes. | 04-30-2015 |
20150372802 | SOURCE SYNCHRONOUS BUS CLOCK GATING SYSTEM - Embodiments are described for a method of reducing power consumption in source synchronous bus systems by reducing signal transitions in the system. Instead of sending clock and data valid signals, only the start and end of valid data packets are marked by clock signal transitions, or only a number of clock pulses that corresponds to number of data words is sent, or only a number transitions on clock signals are sent. The clock signal transitions may comprise either clock pulses or exclusively rising edge or falling edge transitions of the clock signal. | 12-24-2015 |
Patent application number | Description | Published |
20090203925 | SYNTHESIS OF HIMBACINE ANALOGS - The present invention relates to an improved process for preparing himbacine analogs. The compounds are useful as thrombin receptor antagonists. The improved process may allow for at least one of easier purification by crystallization, easier scalability, and improved process yield on the desired enantiomer. | 08-13-2009 |
20090203936 | SYNTHESIS OF 3-(5-NITROCYCLOHEX-1-ENYL) ACRYLIC ACID AND ESTERS THEREOF - This application discloses provides a process for the introduction of nitro-group functionality into a compound which contains also a site of unsaturation and/or oxygen functionality by direct (one step) oxidation of an oxime functional group mediated by a molybdenum VI/VII peroxo complex, the process comprising:
| 08-13-2009 |
20090281321 | EXO- AND DIASTEREO- SELECTIVE SYNTHESES OF HIMBACINE ANALOGS - This application discloses a novel process for the preparation of himbacine analogs useful as thrombin receptor antagonists. The process is based in part on the use of a base-promoted dynamic epimerization of a chiral nitro center. The chemistry taught herein can be exemplified by the following: | 11-12-2009 |
20100137597 | SYNTHESIS Of DIETHYLPHOSPHONATE - This application discloses a novel process for the preparation of phosphonate esters useful as intermediates in the preparation of himbacine analogs, themselves useful as thrombin receptor antagonists. The chemistry taught herein can be exemplified by the following scheme: | 06-03-2010 |
20100249411 | Stereoselective Alkylation of Chiral 2-Methly-4 Protected Piperazines - In an illustrative embodiment, the present invention describes the synthesis of the following compound and similar compounds, in high stereochemical purity by a novel stereoselective alkylation process: | 09-30-2010 |
20100267947 | EXO-SELECTIVE SYNTHESIS OF HIMBACINE ANALOGS - This application discloses a novel process for the synthesis of himbacine analogs, as well as the compounds produced thereby. The synthesis proceeds by alternative routes including the cyclic ketal amide route, the chiral carbamate amide route, and the chiral carbamate ester route. The compounds produced thereby are useful as thrombin receptor antagonists. The chemistry disclosed herein is exemplified in the following synthesis sequence: | 10-21-2010 |
20110144327 | PROCESS FOR THE SYNTHESIS OF AZETIDINONES - A process is provided for preparing azetidinones useful as intermediates in the synthesis of penems and as hypocholesterolemic agents, comprising reacting a β-(substituted-amino)amide, a β-(substituted-amino)acid ester, or a β-(substituted-amino)thiolcarbonic acid ester with a silylating agent and a cyclizing agent selected from the group consisting of alkali metal carboxylates, quaternary ammonium carboxylates, quaternary ammonium hydroxides, quaternary ammonium alkoxides, quaternary ammonium aryloxides and hydrates thereof, or the reaction product of: (i) at least one quaternary ammonium halide and at least one alkali metal carboxylate; or (ii) at least one quaternary ammonium chloride, quaternary ammonium bromide, or quaternary ammonium iodide and at least one alkali metal fluoride, wherein a quaternary ammonium moiety of the cyclizing agent is unsubstituted or substituted by one to four groups independently selected from the group consisting of alkyl, arylalkyl and arylalkyl-alkyl. | 06-16-2011 |
20110251392 | EXO- AND DIASTEREO- SELECTIVE SYNTHESIS OF HIMBACINE ANALOGS - This application discloses a novel process for the preparation of himbacine analogs useful as thrombin receptor antagonists. The process is based in part on the use of a base-promoted dynamic epimerization of a chiral nitro center. The chemistry taught herein can be exemplified by the following: | 10-13-2011 |
20120083601 | PROCESS FOR THE SYNTHESIS OF AZETIDINONES - A process is provided for preparing azetidinones useful as intermediates in the synthesis of penems and as hypocholesterolemic agents, comprising reacting a β-(substituted-amino)amide, a β-(substituted-amino)acid ester, or a β-(substituted-amino)thiolcarbonic acid ester with a silylating agent and a cyclizing agent selected from the group consisting of alkali metal carboxylates, quaternary ammonium carboxylates, quaternary ammonium hydroxides, quaternary ammonium alkoxides, quaternary ammonium aryloxides and hydrates thereof, or the reaction product of: (i) at least one quaternary ammonium halide and at least one alkali metal carboxylate; or (ii) at least one quaternary ammonium chloride, quaternary ammonium bromide, or quaternary ammonium iodide and at least one alkali metal fluoride, wherein a quaternary ammonium moiety of the cyclizing agent is unsubstituted or substituted by one to four groups independently selected from the group consisting of alkyl, arylalkyl and arylalkyl-alkyl. | 04-05-2012 |
20120142914 | EXO-SELECTIVE SYNTHESIS OF HIMBACINE ANALOGS - This application discloses a novel process for the synthesis of himbacine analogs, as well as the compounds produced thereby. The synthesis proceeds by alternative routes including the cyclic ketal amide route, the chiral carbamate amide route, and the chiral carbamate ester route. The compounds produced thereby are useful as thrombin receptor antagonists. The chemistry disclosed herein is exemplified in the following synthesis sequence: | 06-07-2012 |
20120296093 | EXO- AND DIASTEREO- SELECTIVE SYNTHESIS OF HIMBACINE ANALOGS - This application discloses a novel process for the preparation of himbacine analogs useful as thrombin receptor antagonists. The process is based in part on the use of a base-promoted dynamic epimerization of a chiral nitro center. The chemistry taught herein can be exemplified by the following: | 11-22-2012 |
20120302745 | EXO-SELECTIVE SYNTHESIS OF HIMBACINE ANALOGS - This application discloses a novel process for the synthesis of himbacine analogs, as well as the compounds produced thereby. The synthesis proceeds by alternative routes including the cyclic ketal amide route, the chiral carbamate amide route, and the chiral carbamate ester route. The compounds produced thereby are useful as thrombin receptor antagonists. The chemistry disclosed herein is exemplified in the following synthesis sequence: | 11-29-2012 |