Patent application number | Description | Published |
20100161886 | Architecture for Address Mapping of Managed Non-Volatile Memory - The disclosed architecture uses address mapping to map a block address on a host interface to an internal block address of a non-volatile memory (NVM) device. The block address is mapped to an internal chip select for selecting a Concurrently Addressable Unit (CAU) identified by the block address. The disclosed architecture supports generic NVM commands for read, write, erase and get status operations. The architecture also supports an extended command set for supporting read and write operations that leverage a multiple CAU architecture. | 06-24-2010 |
20110173462 | CONTROLLING AND STAGGERING OPERATIONS TO LIMIT CURRENT SPIKES - Systems and methods are disclosed for managing the peak power consumption of a system, such as a non-volatile memory system (e.g., flash memory system). The system can include multiple subsystems and a controller for controlling the subsystems. Each subsystem may have a current profile that is peaky. Thus, the controller may control the peak power of the system by, for example, limiting the number of subsystems that can perform power-intensive operations at the same time or by aiding a subsystem in determining the peak power that the subsystem may consume at any given time. | 07-14-2011 |
20120030506 | READ DISTURB SCORECARD - Systems and methods are disclosed for handling read disturbs based on one or more characteristics of read operations performed on a non-volatile memory (“NVM”). In some embodiments, a control circuitry of a system can generate a variable damage value determined based on one or more characteristics of a read operation. Using the damage value, the control circuitry can update a score associated with the block. If the control circuitry determines that the score exceeds a pre-determined threshold, at least a portion of the block can be relocated to a different memory location in the NVM. In some embodiments, portions of the block may be relocated over a period of time. | 02-02-2012 |
20120047409 | SYSTEMS AND METHODS FOR GENERATING DYNAMIC SUPER BLOCKS - Systems and methods are disclosed for generating dynamic super blocks from one or more grown bad blocks of a non-volatile memory (“NVM”). In some embodiments, a dynamic super block can be formed by striping together a subset of memory locations of grown bad blocks from one or more dies of a NVM. The subset of memory locations may be selected based on at least one reliability measurement of the subset of memory locations. In some embodiments, in response to detecting one or more access failures in a portion of the dynamic super block, the NVM interface can retire at least a portion of the dynamic super block. In some embodiments, the NVM interface can reconstruct a new dynamic super block from the dynamic super block by progressively increasing the size of the new dynamic super block. | 02-23-2012 |
20130212318 | ARCHITECTURE FOR ADDRESS MAPPING OF MANAGED NON-VOLATILE MEMORY - The disclosed architecture uses address mapping to map a block address on a host interface to an internal block address of a non-volatile memory (NVM) device. The block address is mapped to an internal chip select for selecting a Concurrently Addressable Unit (CAU) identified by the block address. The disclosed architecture supports generic NVM commands for read, write, erase and get status operations. The architecture also supports an extended command set for supporting read and write operations that leverage a multiple CAU architecture. | 08-15-2013 |
Patent application number | Description | Published |
20110176363 | JUNCTION LEAKAGE SUPPRESSION IN MEMORY DEVICES - A memory device includes a substrate and source and drain regions formed in the substrate. The source and drain regions include both phosphorous and arsenic and the phosphorous may be implanted prior to the arsenic. The memory device also includes a first dielectric layer formed over the substrate and a charge storage element formed over the first dielectric layer. The memory device may further include a second dielectric layer formed over the charge storage element and a control gate formed over the second dielectric layer. | 07-21-2011 |
20130078795 | ETCH STOP LAYER FOR MEMORY CELL RELIABILITY IMPROVEMENT - A memory device and a method of making the memory device are provided. A first dielectric layer is formed on a substrate, a floating gate is formed on the first dielectric layer, a second dielectric layer is formed on the floating gate, a control gate is formed on the second dielectric layer, and at least one film, including a conformal film, is formed over a surface of the memory device. | 03-28-2013 |
20130140720 | VOID FREE INTERLAYER DIELECTRIC - A method of manufacturing a non-volatile memory device includes forming a number of memory cells. The method also includes depositing a first dielectric layer over the memory cells, where the first dielectric layer is a conformal layer having a substantially uniform thickness. The method further includes depositing a second dielectric layer over the first dielectric layer. Together, the first and second dielectric layers form an interlayer dielectric without voids. | 06-06-2013 |
Patent application number | Description | Published |
20100088404 | MONITORING RELATED CONTENT REQUESTS - Multiple transaction components that comprise a transaction are correlated using a GUID generated at a browser application. The transaction components may occur asynchronously or synchronously between a network browser and one or more applications. An identifier is generated for a set of network browser requests corresponding to a single user input or some other event and the identifier is included in each request. Server traffic and the servers processing the request are monitored and data which includes the identifier is generated. Data for the transaction with multiple transaction components is reported using the GUID associated with the transaction. | 04-08-2010 |
20110022707 | HIERARCHY FOR CHARACTERIZING INTERACTIONS WITH AN APPLICATION - Application runtime data is obtained from an application monitoring system which monitors execution of an application, and traffic monitoring data is obtained from a traffic monitoring system which monitors traffic to/from the application as the clients interact with the application. Corresponding application runtime data and traffic monitoring data can be selectively output to assist an operator in investigating an anomalous condition. The data can be classified and selectively output according to one or more hierarchies which characterize the interactions. The hierarchies can include a domain level, a business process level (where a domain is made up of a number of business processes), a business transaction level (where a business process is made up of different business transactions), an individual transaction level (where a business transaction is made up of different transactions), and a transaction component level (where a transaction is made up of one or more transaction components). | 01-27-2011 |
20110167156 | MONITORING RELATED CONTENT REQUESTS - Multiple transaction components that comprise a transaction are correlated using a GUID generated at a browser application. The transaction components may occur asynchronously or synchronously between a network browser and one or more applications. An identifier is generated for a set of network browser requests corresponding to a single user input or some other event and the identifier is included in each request. Server traffic and the servers processing the request are monitored and data which includes the identifier is generated. Data for the transaction with multiple transaction components is reported using the GUID associated with the transaction. | 07-07-2011 |
20120016983 | Synthetic Transactions To Test Blindness In A Network System - Synthetic transactions for a network system are generated based on monitoring of the network system to determine whether the network system may be blind to traffic. A process determines whether an application within an application server in a network system is processing traffic received by the application server, and whether a web server within the network system and in communication with the application server is receiving traffic that requires processing by the application. The process determines that the network system may be blind to the traffic, and, in response, generates a synthetic transaction instruction and a corresponding synthetic transaction to test whether the network system is blind to the traffic. Based on a response of the network system to the synthetic transaction, the process determines whether there is a malfunction of the application server or a period of low traffic activity of the application server. | 01-19-2012 |