Patent application number | Description | Published |
20100031182 | METHOD, COMPUTER PROGRAM PRODUCT, AND APPARATUS FOR PROVIDING AN ENERGY MAP - A method for providing an energy map may include receiving an indication of status for each of a plurality of individual entities with respect to corresponding priorities defined for each respective individual entity, correlating received indications of status to respective group priorities, providing a representation of a plurality of the group priorities, and mapping an amount of energy associated with the group priorities by providing a graphical representation of a respective amount of resources associated with the group priorities based on the received indications. | 02-04-2010 |
20120204124 | METHOD, COMPUTER PROGRAM PRODUCT, AND APPARATUS FOR PROVIDING AN ENERGY MAP - A method for providing an energy map may include receiving an indication of status for each of a plurality of individual entities with respect to corresponding priorities defined for each respective individual entity, correlating received indications of status to respective group priorities, providing a representation of a plurality of the group priorities, and mapping an amount of energy associated with the group priorities by providing a graphical representation of a respective amount of resources associated with the group priorities based on the received indications. | 08-09-2012 |
20140172485 | METHOD, COMPUTER PROGRAM PRODUCT, AND APPARATUS FOR PROVIDING AN ENERGY MAP - A method for providing an energy map may include receiving an indication of status for each of a plurality of individual entities with respect to corresponding priorities defined for each respective individual entity, correlating received indications of status to respective group priorities, providing a representation of a plurality of the group priorities, and mapping an amount of energy associated with the group priorities by providing a graphical representation of a respective amount of resources associated with the group priorities based on the received indications. | 06-19-2014 |
Patent application number | Description | Published |
20080299717 | METHOD OF FORMING A SEMICONDUCTOR DEVICE FEATURING A GATE STRESSOR AND SEMICONDUCTOR DEVICE - A semiconductor device ( | 12-04-2008 |
20080299724 | METHOD OF MAKING A SEMICONDUCTOR DEVICE WITH EMBEDDED STRESSOR - A method for forming a semiconductor device includes providing a semiconductor substrate; forming a gate dielectric over the semiconductor substrate; forming a gate electrode over the gate dielectric; forming an insulating layer over a sidewall of the gate electrode; defining source and drain regions in the semiconductor substrate adjacent to the insulating layer; implanting a dopant in the source and drain regions of the semiconductor substrate to form doped source and drain regions; forming a sidewall spacer adjacent to the insulating layer; forming a recess in the semiconductor substrate in the source and drain regions, wherein the recess extends directly underneath the spacer a predetermined distance from a channel regions; and forming a stressor material in the recess. The method allows the stressor material to be formed closer to a channel region, thus improving carrier mobility in the channel while not degrading short channel effects. | 12-04-2008 |
20100013021 | METHOD TO REDUCE THRESHOLD VOLTAGE (Vt) IN SILICON GERMANIUM (SIGE), HIGH-K DIELECTRIC-METAL GATE, P-TYPE METAL OXIDE SEMICONDUCTOR FIELD EFFECT TRANSISTORS - Disclosed are embodiments of a p-type, silicon germanium (SiGe), high-k dielectric-metal gate, metal oxide semiconductor field effect transistor (PFET) having an optimal threshold voltage (Vt), a complementary metal oxide semiconductor (CMOS) device that includes the PFET and methods of forming both the PFET alone and the CMOS device. The embodiments incorporate negatively charged ions (e.g., fluorine (F), chlorine (Cl), bromine (Br), iodine (I), etc.) into the high-k gate dielectric material of the PFET only so as to selectively adjust the negative Vt of the PFET (i.e., so as to reduce the negative Vt of the PFET). | 01-21-2010 |
20100102393 | METAL GATE TRANSISTORS - An integrated circuit that includes a substrate having first and second active regions is disclosed. A first transistor of a first type and a second transistor of a second type are disposed in the first and second active regions respectively. Each transistor includes a gate stack having a metal gate electrode over a gate dielectric layer. First and second gate threshold voltage adjusting (GTVA) layers contacting first and second gate dielectric layer of the first and second transistors are provided. The first GTVA layer tunes a gate threshold voltage of the first transistor. A channel of the second transistor includes dopants to tune the gate threshold voltage of the second transistor. | 04-29-2010 |
20110169096 | BALANCING NFET AND PFET PERFORMANCE USING STRAINING LAYERS - An integrated circuit structure includes a substrate and at least one pair of complementary transistors on or in the substrate. The pair of complementary transistors comprises a first transistor and a second transistor. The structure also includes a first stress-producing layer on the first transistor and the second transistor, and a second stress-producing layer on the first stress-producing layer over the first transistor and the second transistor. The first stress-producing layer applies tensile strain force on the first transistor and the second transistor. The second stress-producing layer applies compressive strain force on the first stress-producing layer, the first transistor, and the second transistor. | 07-14-2011 |
20110220975 | METHOD OF FORMING A SEMICONDUCTOR DEVICE FEATURING A GATE STRESSOR AND SEMICONDUCTOR DEVICE - A semiconductor device is formed in a semiconductor layer. A gate stack is formed over the semiconductor layer and comprises a first conductive layer and a second layer over the first layer. The first layer is more conductive and provides more stopping power to an implant than the second layer. A species is implanted into the second layer. Source/drain regions are formed in the semiconductor layer on opposing sides of the gate stack. The gate stack is heated after the step of implanting to cause the gate stack to exert stress in the semiconductor layer in a region under the gate stack. | 09-15-2011 |
20120256268 | INTEGRATED CIRCUIT STRUCTURE HAVING SUBSTANTIALLY PLANAR N-P STEP HEIGHT AND METHODS OF FORMING - Solutions for forming an integrated circuit structure having a substantially planar N-P step height are disclosed. In one embodiment, a method includes: providing a structure having an n-type field effect transistor (NFET) region and a p-type field effect transistor (PFET) region; forming a mask over the PFET region to leave the NFET region exposed; performing dilute hydrogen-flouride (DHF) cleaning on the exposed NFET region to substantially lower an STI profile of the NFET region; and forming a silicon germanium (SiGE) channel in the PFET region after the performing of the DHF. | 10-11-2012 |