Patent application number | Description | Published |
20080297267 | Voltage controlled oscillator circuit and a method for configuring a voltage controlled oscillator circuit - The voltage controlled oscillator (VCO) circuit comprises a tank circuit, a first tuning section comprising first capacitor elements wherein each one of the first capacitor elements is individually utilizable for the tank circuit, and a second tuning section comprising second capacitor elements wherein each one of the second capacitor elements is individually utilizable for the tank circuit and the capacitance of each one of the second capacitor elements is continuously adjustable in a predetermined capacitance range in dependence on a tuning voltage. | 12-04-2008 |
20100214715 | Variable Capacitance Unit - Implementations of differential variable capacitance systems are disclosed. | 08-26-2010 |
20120057655 | Polar Transmitter Suitable for Monolithic Integration in SoCs - The disclosed polar modulation transmitter circuit is configured to generate an output signal having a transmission frequency that minimizes crosstalk effects between different transmission bands (e.g., Bluetooth, GSM, UMTS, etc.). In particular, a polar modulation transceiver circuit, having an amplitude modulated (AM) signal and a phase modulated (PM) signal, comprises a digitally controlled oscillator (DCO) configured to generate a DCO signal having a DCO frequency. The DCO signal is provided to one or more frequency dividers that are configured to selectively divide the DCO signal to generate various lower frequency signals, used to select a sampling rate for a DAC operating on the AM signal and an RF carrier signal frequency, which result in an output signal having a frequency that does not interfere with other RF systems on the same IC (e.g., that falls outside of the downlink frequency of other RF systems). Other systems and methods are also disclosed. | 03-08-2012 |
20120319749 | DIGITAL PLL WITH AUTOMATIC CLOCK ALIGNMENT - One embodiment of the present invention relates to a digital phase locked loop (ADPLL) configured to generate a plurality of time-aligned output clock signals having different frequency values. The ADPLL comprises a digital controlled oscillator configured to generate a variable clock signal that is separated into two signal paths operating according to two separate clock domains. A first signal path is configured to generate a feedback signal that synchronizes the variable clock signal with a reference signal. A second signal path comprises a clock divider circuit configured to synchronously divide the variable clock signal to automatically generate a plurality of time-aligned output clock signals having different frequencies. A clock aligner monitors a phase difference between the variable clock signal and one of the plurality of time-aligned output clock signals and generates a control signal that causes a programmable delay line to automatically time-align the output clock signals with the variable clock signal. | 12-20-2012 |
20130009473 | Oscillator Circuit - Devices are provided comprising oscillator circuits coupled to a supply voltage via an adjustable resistance. Corresponding methods to control adjustable resistances are also provided. | 01-10-2013 |
20130107978 | Split Varactor Array with Improved Matching and Varactor Switching Scheme | 05-02-2013 |
20140103976 | MULTI-OUTPUT PHASE DETECTOR - Representative implementations of devices and techniques provide a multi-bit binary representation of a phase difference between two signals. The multi-bit binary representation may include information regarding a sign of the phase difference and a magnitude of the phase difference. | 04-17-2014 |
20140119476 | POLAR TRANSMITTER SUITABLE FOR MONOLITHIC INTEGRATION IN SoCs - The disclosed polar modulation transmitter circuit is configured to generate an output signal having a transmission frequency that minimizes crosstalk effects between different transmission bands (e.g., Bluetooth, GSM, UMTS, etc.). In particular, a polar modulation transceiver circuit, having an amplitude modulated (AM) signal and a phase modulated (PM) signal, comprises a digitally controlled oscillator (DCO) configured to generate a DCO signal having a DCO frequency. The DCO signal is provided to one or more frequency dividers that are configured to selectively divide the DCO signal to generate various lower frequency signals, used to select a sampling rate for a DAC operating on the AM signal and an RF carrier signal frequency, which result in an output signal having a frequency that does not interfere with other RF systems on the same IC (e.g., that falls outside of the downlink frequency of other RF systems). Other systems and methods are also disclosed. | 05-01-2014 |
20150070060 | MULTI-OUTPUT PHASE DETECTOR - Representative implementations of devices and techniques provide a multi-bit binary representation of a phase difference between two signals. The multi-bit binary representation may include information regarding a sign of the phase difference and a magnitude of the phase difference. | 03-12-2015 |