Teyssier
Jeremie Teyssier, Grenoble FR
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20130287254 | Method and Device for Detecting an Object in an Image - A method for detecting at least one object in an image including a pixel array, by means of an image processing device, including searching out the silhouette of the object in the image only if pixels of the image are at the minimum or maximum level. | 10-31-2013 |
20150145768 | METHOD AND DEVICE FOR CONTROLLING AN APPARATUS USING SEVERAL DISTANCE SENSORS - A method for controlling an apparatus, includes steps of: determining distance measurements of an object in a first direction, using distance sensors defining between them a second direction different from the first direction, assessing a first inclination of the object in relation to a second direction based on the distance measurements, and determining a first command of the apparatus according to the inclination assessment. | 05-28-2015 |
Jeremie Teyssier Teyssier, Grenoble FR
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20150144767 | METHOD FOR EVALUATING POSITION AND MOTION USING TIME OF FLIGHT DETECTORS - A method is for evaluating a coverage factor of a photon emission cone of a time of flight sensor. The method may include the steps of assigning a reference curve to the sensory providing a photon flux intensity as a function of time of flight; and acquiring a time of flight and a corresponding flux intensity with the sensor. The method may also include reading the intensity provided by the reference curve for the acquired time of flight, and providing an indication of the coverage factor based on the ratio between the acquired intensity and the read intensity. | 05-28-2015 |
Melanie Emanuelle Lucie Teyssier, Sophia Antipolis Cedex FR
Patent application number | Description | Published |
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20130290635 | PROVISION OF ACCESS CONTROL DATA WITHIN A DATA PROCESSING SYSTEM - A data processing system ( | 10-31-2013 |
20140181416 | RESOURCE MANAGEMENT WITHIN A LOAD STORE UNIT - A load store pipeline | 06-26-2014 |
20140195787 | TRACKING SPECULATIVE EXECUTION OF INSTRUCTIONS FOR A REGISTER RENAMING DATA STORE - First processing circuitry processes at least part of a stream of program instructions. The first processing circuitry has registers for storing data and register renaming circuitry for mapping architectural register specifiers to physical register specifiers. A renaming data store stores renaming entries for identifying a register mapping between the architectural and physical register specifiers. At least some renaming entries have a count value indicating a number of speculation points occurring between generation of a previous count value and generation of the count value. The speculation points may for example be branch operation or load/store operations. | 07-10-2014 |
Melanie Emanuelle Lucie Teyssier, Grasse FR
Patent application number | Description | Published |
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20120110396 | Error handling mechanism for a tag memory within coherency control circuitry - A data processing system | 05-03-2012 |
20120124300 | Apparatus and method for predicting target storage unit - A data processing apparatus comprises processing circuitry and a plurality of storage units. When the processing circuitry executes a data access instruction, then a storage controller identifies based on a target storage address of the data access instruction, which of the storage units includes the target storage location identified by the target storage address. Prediction circuitry is provided to predict a predicted storage unit predicted to include the target storage location, so that retrieval of the data value from the predicted storage unit can be initiated before the storage controller has identified the target storage unit. The prediction circuitry makes the prediction based on the type of the data access instruction executed by the processing circuitry. | 05-17-2012 |
20130151819 | RECOVERING FROM EXCEPTIONS AND TIMING ERRORS - A data processing apparatus with a processing pipeline, the pipeline including exception control circuitry and error detection circuitry. An exception storage unit is configured to maintain an age-ordered list of entries corresponding to instructions issued to the processing pipeline for execution. The unit is configured to store, in association with each entry, an exception indicator indicating whether the instruction is an exception instruction and whether it has generated an exception and an error indicator indicating whether the instruction has generated an error. The apparatus is configured to indicate to the exception storage unit that an instruction is resolved when processing of the instruction has reached a stage such that it is known whether the instruction will generate an error and whether the instruction will generate an exception; and the exception control circuitry is configured to sequentially retire oldest resolved entries from the list in the exception storage unit. | 06-13-2013 |
20130166952 | DATA PROCESSING APPARATUS WITH AN EXECUTION PIPELINE AND ERROR RECOVERY UNIT AND METHOD OF OPERATING THE DATA PROCESSING APPARATUS - A data processing apparatus executes instructions in a sequence of pipelined execution stages. An error detection unit twice samples a signal associated with execution of an instruction and generates an error signal if the samples differ. An exception storage unit maintains an age-ordered list of entries corresponding to instructions issued to the execution pipeline and can mark an entry to show if the error signal has been generated in association with that instruction. A timer unit is responsive to generation of the error signal to initiate timing of a predetermined time period. An error recovery unit initiates a soft pipeline flush procedure if an oldest pending entry in the list has said error marker stored in association therewith and initiates a hard pipeline flush procedure if said predetermined time period elapses, said hard flush procedure comprising resetting said pipeline to a predetermined state. | 06-27-2013 |
20140019734 | DATA PROCESSING APPARATUS AND METHOD USING CHECKPOINTING - A data processing apparatus and method of data processing are provided. The data processing apparatus comprises execution circuitry configured to execute a sequence of program instructions. Checkpoint circuitry is configured to identify an instance of a predetermined type of instruction in the sequence of program instructions and to store checkpoint information associated with that instance. The checkpoint information identifies a state of the data processing apparatus prior to execution of that instance of the predetermined type of instruction, wherein the predetermined type of instruction has an expected long completion latency. If the execution circuitry does not complete execution of that instance of the predetermined type of instruction due to occurrence of a predetermined event, the data processing apparatus is arranged to reinstate the state of the data processing apparatus with reference to the checkpoint information, such that the execution circuitry is then configured to recommence execution of the sequence of program instructions at that instance of the predetermined type of instruction. | 01-16-2014 |
20140310480 | DATA PROCESSING APPARATUS AND METHOD FOR PERFORMING LOAD-EXCLUSIVE AND STORE-EXCLUSIVE OPERATIONS - A data processing apparatus is provided in which a processor unit accesses data values stored in a memory and a cache stores local copies of a subset of the data values. The cache maintains a status value for each local copy stored in the cache. When the processor unit executes a load-exclusive operation, a first data value is loaded from a specified memory location and an exclusive use monitor begins monitoring the specified memory location for accesses. When the processor unit executes a store-exclusive operation, a second data value is stored to the specified memory location if the exclusive use monitor indicates that the first data value has not been modified since the load-exclusive operation was executed. When a local copy of the first data value is stored in the cache and the status value for the local copy of the first data value indicates that the processor unit has exclusive usage of the first data value, the data processing apparatus is configured to prevent modification of the status value for a predetermined time period after the processor unit has executed the load-exclusive operation. | 10-16-2014 |
Mélanie Emanuelle Lucie Teyssier, Grasse FR
Patent application number | Description | Published |
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20120036340 | Data processing apparatus and method using checkpointing - A data processing apparatus and method of data processing are provided. The data processing apparatus comprises execution circuitry configured to execute a sequence of program instructions. Checkpoint circuitry is configured to identify an instance of a predetermined type of instruction in the sequence of program instructions and to store checkpoint information associated with that instance. The checkpoint information identifies a state of the data processing apparatus prior to execution of that instance of the predetermined type of instruction, wherein the predetermined type of instruction has an expected long completion latency. If the execution circuitry does not complete execution of that instance of the predetermined type of instruction due to occurrence of a predetermined event, the data processing apparatus is arranged to reinstate the state of the data processing apparatus with reference to the checkpoint information, such that the execution circuitry is then configured to recommence execution of the sequence of program instructions at that instance of the predetermined type of instruction. | 02-09-2012 |
20130166952 | DATA PROCESSING APPARATUS WITH AN EXECUTION PIPELINE AND ERROR RECOVERY UNIT AND METHOD OF OPERATING THE DATA PROCESSING APPARATUS - A data processing apparatus executes instructions in a sequence of pipelined execution stages. An error detection unit twice samples a signal associated with execution of an instruction and generates an error signal if the samples differ. An exception storage unit maintains an age-ordered list of entries corresponding to instructions issued to the execution pipeline and can mark an entry to show if the error signal has been generated in association with that instruction. A timer unit is responsive to generation of the error signal to initiate timing of a predetermined time period. An error recovery unit initiates a soft pipeline flush procedure if an oldest pending entry in the list has said error marker stored in association therewith and initiates a hard pipeline flush procedure if said predetermined time period elapses, said hard flush procedure comprising resetting said pipeline to a predetermined state. | 06-27-2013 |
Olivier Teyssier, Les Clos Des Roches FR
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20120079332 | DEVICE FOR SECURING A JTAG TYPE BUS - A device to secure a JTAG type bus in its “scan chain” component chaining mode functionality, when several components are connected in series on the JTAG bus, includes a first interface for receiving JTAG signals and a second interface for the JTAG signals originating from a chain of components. The device includes the following modules: a JTAG frame generator module for verifying the continuity of operation of said Bus and components; a module for monitoring the electrical activity of said Bus and components; an alarm module for sending back an alarm detected by the above modules; an alarm module for managing the operating mode of the device; and a security functions activation module AFS. | 03-29-2012 |
Peggy Marion Teyssier, Milford, OH US
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20100305920 | LIQUID LAUNDRY DETERGENT COMPOSITIONS WITH IMPROVED STABILITY AND TRANSPARENCY - An improved method for predicting stability of liquid detergent composition, identifying and designing liquid detergent compositions that provide said desired stability, consumer acceptance and performance. | 12-02-2010 |
20110152162 | Liquid Laundry Detergent Compositions with Improved Stability and Transparency - An improved method for predicting stability of liquid detergent composition, identifying and designing liquid detergent compositions that provide said desired stability, consumer acceptance and performance. | 06-23-2011 |
20110214696 | LIQUID LAUNDRY DETERGENT COMPOSITIONS WITH IMPROVED STABILITY AND TRANSPARENCY - An improved method for predicting stability of liquid detergent composition, identifying and designing liquid detergent compositions that provide said desired stability, consumer acceptance and performance. | 09-08-2011 |
20140349908 | LOW PH DETERGENT COMPOSITION COMPRISING NONIONIC SURFACTANTS - Detergent compositions and, more specifically, low pH detergent compositions comprising nonionic surfactants that are suitable for washing of clothes, and methods of making and using the same. | 11-27-2014 |
Pierre Teyssier, Toussieu FR
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20100174464 | VEHICLE PARK BRAKE STATUS MONITORING METHOD - A vehicle brake system can include a service brake system and a park brake system wherein, the service brake system includes a service brake chamber is delimited by a service brake displaceable wall upon which a brake pushrod is fixed, the brake pushrod is connected to a vehicle braking arrangement and is capable of moving under a pneumatic pressure from a first position whereby the braking arrangement is released to a second position whereby the braking arrangement is actuated, the park brake system having an actuating arrangement capable of pushing the brake pushrod into its second position. This method is based on measuring the volume of the service brake chamber as the volume of the service brake chamber is a parameter which is representative of the actual position of the brake push rod and thus is representative of the actual park brake status. | 07-08-2010 |
Remi Teyssier, Grasse FR
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20100162063 | Control of clock gating - Clock signal control circuitry is disclosed along with a method for switching a clock between modes and a computer program product. The clock signal control circuitry is for receiving a clock signal from a clock signal generator and for outputting said clock signal to synchronous circuitry that is to be clocked by said clock signal. It comprises: an input for receiving mode switching signals indicating said synchronous circuitry is to switch between modes, said mode switching signals comprising a clock gating request signal indicating said synchronous circuitry is to enter a sleep mode during which said circuitry is not clocked and a wake up request signal indicating said synchronous circuitry is to enter an operational mode during which said circuitry is clocked; and is responsive to said clock gating request signal to gate said clock signal such that no clock signal is output to said synchronous circuitry and being responsive to said wake up request signal to output said clock signal to said synchronous circuitry. The clock signal control circuitry further comprises: a data store for storing a delay value; and delay circuitry for delaying switching of said clock signal between modes in response to at least one of said mode switching signals, said delay circuitry delaying said switching by an amount dependent upon said stored delay value. | 06-24-2010 |
20140019734 | DATA PROCESSING APPARATUS AND METHOD USING CHECKPOINTING - A data processing apparatus and method of data processing are provided. The data processing apparatus comprises execution circuitry configured to execute a sequence of program instructions. Checkpoint circuitry is configured to identify an instance of a predetermined type of instruction in the sequence of program instructions and to store checkpoint information associated with that instance. The checkpoint information identifies a state of the data processing apparatus prior to execution of that instance of the predetermined type of instruction, wherein the predetermined type of instruction has an expected long completion latency. If the execution circuitry does not complete execution of that instance of the predetermined type of instruction due to occurrence of a predetermined event, the data processing apparatus is arranged to reinstate the state of the data processing apparatus with reference to the checkpoint information, such that the execution circuitry is then configured to recommence execution of the sequence of program instructions at that instance of the predetermined type of instruction. | 01-16-2014 |
Rémi Teyssier, Grasse FR
Patent application number | Description | Published |
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20120036340 | Data processing apparatus and method using checkpointing - A data processing apparatus and method of data processing are provided. The data processing apparatus comprises execution circuitry configured to execute a sequence of program instructions. Checkpoint circuitry is configured to identify an instance of a predetermined type of instruction in the sequence of program instructions and to store checkpoint information associated with that instance. The checkpoint information identifies a state of the data processing apparatus prior to execution of that instance of the predetermined type of instruction, wherein the predetermined type of instruction has an expected long completion latency. If the execution circuitry does not complete execution of that instance of the predetermined type of instruction due to occurrence of a predetermined event, the data processing apparatus is arranged to reinstate the state of the data processing apparatus with reference to the checkpoint information, such that the execution circuitry is then configured to recommence execution of the sequence of program instructions at that instance of the predetermined type of instruction. | 02-09-2012 |
20120066481 | Dynamic instruction splitting - A data processing apparatus and method are provided. The data processing apparatus is configured to perform data processing operations in response to data processing instructions including a multiple operation instruction, in response to which multiple data processing operations are performed. The data processing apparatus comprises two or more data processing units configured to perform the data processing operations and an instruction arbitration unit configured to perform sub-division of a multiple operation instruction into a plurality of sub-instructions and to perform allocation of the plurality of sub-instructions amongst the two or more data processing units, wherein each sub-instruction is arranged to cause one of the two or more data processing units to perform at least one data processing operation of the multiple data processing operations. The instruction arbitration unit is configured to perform the sub-division and the allocation dynamically in dependence on a current availability of a resource for each of the two or more data processing units, enabling more efficient usage of the resources of each of the data processing units to be made. | 03-15-2012 |
Sylvie Teyssier, Saint Ismier FR
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20100132477 | INTEGRATED DEVICE FOR MONITORING DEFORMATIONS OF AN ELECTRICALLY INSULATING PART AND METHOD FOR MANUFACTURING ONE SUCH DEVICE - An integrated device for monitoring an electrically insulating part comprising an optic fiber in which at least one Bragg grating is formed, the electrically insulating part being made from a composite material with a thermosetting matrix, and the optic fiber comprising a mechanical protection sleeve made from polyimide material. | 06-03-2010 |