Tey
Ching-Hwa Tey, Singapore SG
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20100173466 | METHOD FOR FABRICATING A SEMICONDUCTOR DEVICE - A method for fabricating a semiconductor device includes providing a substrate sequentially having a polysilicon layer and an insulating layer formed thereon; patterning the polysilicon layer and the insulating layer to form at least a gate structure on the substrate; forming lightly doped regions in the substrate respectively at two side of the gate structure; forming a spacer on a sidewall of the gate structure; forming barrier layers respectively on a top surface of the gate structure and surfaces of the substrate at two sides of the spacer, and forming a source/drain in the substrate respectively at two sides of the spacer. | 07-08-2010 |
20120309199 | MANUFACTURING METHOD FOR DUAL DAMASCENE STRUCTURE - A manufacturing method for a dual damascene structure first includes providing a substrate having at least a dielectric layer, a first hard mask layer, a first cap layer, a second hard mask layer, and a second cap layer sequentially formed thereon, performing a first double patterning process to form a plurality of first trench openings and second trench openings in the second cap layer and the second hard mask, and the first layer being exposed in bottoms of the first trench openings and the second trench openings, performing a second double patterning process to form a plurality of first via openings and second via openings in the first cap layer and the first hard mask layer, and transferring the first trench openings, the second trench openings, the first via openings, and the second via openings to the dielectric layer to form a plurality of dual damascene openings. | 12-06-2012 |
20130181264 | SEMICONDUCTOR STRUCTURE AND PROCESS THEREOF - A semiconductor structure includes at least a fin-shaped structure, a gate, a source/drain region, an interdielectric layer and an epitaxial structure. At least a fin-shaped structure is located on a bottom substrate. The gate covers the fin-shaped structure. The source/drain region is located in the fin-shaped structure next to the gate. The interdielectric layer covers the gate and the fin-shaped structure, wherein the interdielectric layer has a plurality of contact holes, respectively exposing at least a part of the source/drain region. The epitaxial structure is located in each of the contact holes, directly contacts and is only located on the source/drain region. Additionally, a semiconductor process formed said semiconductor structure is also provided. | 07-18-2013 |
20140361438 | SEAL RING STRUCTURE AND METHOD OF FORMING THE SAME - A method of forming a seal ring structure includes the following steps. A substrate is provided, and the substrate includes a seal ring region. A metal stack is formed in the seal ring region. A first dielectric layer covering the metal stack is formed. A part of the first dielectric layer is removed to form an opening to expose the metal stack, and at least a side of the opening is not perpendicular to a top surface of the first dielectric layer. A conductive layer is formed to fill the opening. A second dielectric layer is formed to continuously cover the first dielectric layer and the conductive layer, and the second dielectric layer has a v-shaped surface totally overlapping the conductive layer. | 12-11-2014 |
Ching-Hwa Tey, De Royale SG
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20130130460 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF - A method for fabricating a semiconductor device comprises steps as follows: A first dummy gate having a first high-k gate insulator layer, a first composite sacrificial layer, and a first dummy gate electrode sequentially stacked on a substrate is firstly provided. The first dummy gate electrode is subsequently removed to expose the first composite sacrificial layer. The first composite sacrificial layer is then removed. Thereafter, a first work function layer is formed on the first high-k gate insulator layer, and a first metal gate electrode is formed on the first work function layer. | 05-23-2013 |
Ching Sze Tey, Singapore SG
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20100007286 | POWER SUPPLY SYSTEM AND METHOD - A power supply system and a method for providing power supply to electrical equipment from conventional lighting circuits in buildings are disclosed. The invention is intended to provide power supply to electrical equipment, without the need of conventional alternating current (AC) power supply power socket outlets. Instead, it obtains electrical power from existing lighting points. An embodiment of the invention is disclosed for achieving this without disrupting normal operation of turning on and off existing lighting sources. The present invention consists a wall switch unit and a lighting source control unit. The wall switch unit control s the level or waveforms of AC voltage supply to the lighting source control unit while the lighting source control unit detects the AC voltage level or waveforms for switching on or off a lighting source. Additionally, regardless of whether the lighting source is switched on or off, an uninterrupted power supply is derived from the lighting source control unit with this power supply being usable for electrically powering external electrical equipment connected thereto. | 01-14-2010 |
Ju Nie Tey, Singapore SG
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20110237000 | Method for detecting an analyte molecule - The invention relates to a method for detecting the presence or amount of an analyte, said method comprising (a) coupling the analyte to a carrier molecule, wherein the carrier molecule is larger in size, electrically charged and/or polar, to form an analyte:carrier molecule complex; (b) contacting the analyte:carrier molecule complex of (a) with an analyte-binding molecule coupled to a semiconducting nanostructure; and (c) determining the change in conductance upon binding of the analyte:carrier molecule complex to the analyte-binding molecule and correlating the determined change in conductance to the presence or amount of the analyte. Alternatively, the analyte:carrier molecule complex of (a) is immobilized on the nanostructure and the immobilized analyte:carrier molecule complex is contacted with the analyte-binding molecule. | 09-29-2011 |
Tiam Fatt Tey, Singapore SG
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20100134219 | TUNER CIRCUIT WITH LOOP THROUGH FUNCTION - The tuner circuit comprises a HF input and a HF output with a loop through function, wherein a variable capacitance diode is coupled with a first terminal to the HF input and with a second terminal to the HF output for providing a passive loop through function. The variable capacitance diode is in particular in a passing mode, when no DC reverse voltage is applied, for providing a passive loop through function. In a preferred embodiment, the tuner circuit is designed for reception of television channels, and for the variable capacitance diode one or two tuning variable capacitance diode is used being designed for satellite tuners with a frequency range of 1-2 GHz, or a specially designed variable capacitance diode with a capacitance ratio C | 06-03-2010 |
Wee Jin Tey, Singapore SG
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20130190915 | EFFICIENT TRANSFER OF MATERIALS IN MANUFACTURING - Methods for manufacturing automation and a computer executed automated handling system for forming a device are presented. The method includes issuing a transfer request by a tool. The transfer request is processed by a production control system configured for tracking and controlling the flow of carriers. The processing of the transfer request includes selecting a carrier containing production material. A transport system having transport and load/unload (U/L) units in a production area to effect a transfer is controlled and the carrier is transferred by the transport system. | 07-25-2013 |