Patent application number | Description | Published |
20090144531 | BOOTING WITH SUB SOCKET PARTITIONING - A method of booting up a computer system comprising a first multi-cored processor comprising a first plurality of cores and a second multi-cored processor comprising a second plurality of cores is disclosed. The method may comprise configuring a first partition comprising a first one or more cores from the first plurality of cores and from the second plurality of cores, configuring a second partition comprising a second one or more cores from the first plurality of cores and from the second plurality of cores, and configuring a third partition comprising a third one or more cores from the first plurality of cores and one or more cores from the second plurality of cores. | 06-04-2009 |
20090198694 | Resolving conflicts in a transactional execution model of a multiprocessor system - In one embodiment, the present invention includes a method for resolving conflicts, including receiving data access requests from multiple requestors at a home agent that owns the data, determining whether any of the requests are transactional requests, any of the requestors obtains the data forwarded from another agent, and a highest priority transactional requestor, and based at least in part on the determining, sending from the home agent a first message to the highest priority transactional requestor to indicate that the highest priority transactional requestor is to not abort its transaction and a second message to the other requestor to indicate that the corresponding requestor is to abort its transaction. Other embodiments are described and claimed. | 08-06-2009 |
20100241825 | Opportunistic Transmission Of Software State Information Within A Link Based Computing System - A method is described that involves determining that software state information of program code is to be made visible to a monitoring system. The method also involves initiating the writing of the software state information into a register. The method also involves waiting for the software state information to be placed onto a link within a link based computing system. | 09-23-2010 |
20100244573 | HYBRID POWER DELIVERY SYSTEM AND METHOD - A power control circuit includes a selector coupled to a first power source and a second power source. The selector selects power from the first power source for powering a load based on a status signal from at least the first power source. The first power source may be an environmental power source and the second power source may be another type of power source. | 09-30-2010 |
20120311360 | Reducing Power Consumption Of Uncore Circuitry Of A Processor - In one embodiment, a multi-core processor includes multiple cores and an uncore, where the uncore includes various logic units including a cache memory, a router, and a power control unit (PCU). The PCU can clock gate at least one of the logic units and the cache memory when the multi-core processor is in a low power state to thus reduce dynamic power consumption. | 12-06-2012 |
20130007560 | RANK-SPECIFIC CYCLIC REDUNDANCY CHECK - Embodiments of the present disclosure describe methods, apparatus, and system configurations for providing rank-specific cyclic redundancy checks in memory systems. | 01-03-2013 |
20130042126 | MEMORY LINK POWER MANAGEMENT - Embodiments of the invention describe systems and processes directed towards improving link power-management during memory subsystem idle states. Embodiments of the invention control memory link operations when various components of a memory subsystem enter low power states under certain operating conditions. Embodiments of the invention similarly describe exiting low power states for memory links and various components of a memory subsystem upon detecting certain operating conditions. | 02-14-2013 |
20130042127 | IDLE POWER REDUCTION FOR MEMORY SUBSYSTEMS - Embodiments of the invention describe systems and processes directed towards reducing memory subsystem idle power consumption. Embodiments of the invention enable low power states for various components of a memory subsystem under certain operating conditions, and exiting said low power states under certain operating conditions. | 02-14-2013 |
20130179713 | REDUCING POWER CONSUMPTION OF UNCORE CIRCUITRY OF A PROCESSOR - In one embodiment, a multi-core processor includes multiple cores and an uncore, where the uncore includes various logic units including a cache memory, a router, and a power control unit (PCU). The PCU can clock gate at least one of the logic units and the cache memory when the multi-core processor is in a low power state to thus reduce dynamic power consumption. | 07-11-2013 |
20130332795 | RANK-SPECIFIC CYCLE REDUNDANCY CHECK - Embodiments of the present disclosure describe methods, apparatus, and system configurations for providing rank-specific cyclic redundancy checks in memory systems. | 12-12-2013 |
20130346966 | MONITORING RESOURCE USAGE BY A VIRTUAL MACHINE - Embodiments of apparatus, computer-implemented methods, systems, devices, and computer-readable media are described herein for tracking per-virtual machine (“VM”) resource usage independent of a virtual machine monitor (“VMM”). In various embodiments, a first logic unit may associate one or more virtual central processing units (“vCPUs”) operated by one or more physical processing units of a computing device with a first VM of a plurality of VMs operated by the computing device, and collect data about resources used by the one or more physical processing units to operate the one or more vCPUs associated with the first VM. In various embodiments, a second logic unit of the computing device may determine resource-usage by the first VM based on the collected data. In various embodiments, the first and second logic units may perform these functions independent of a VMM of the computing device. | 12-26-2013 |
20140040550 | MEMORY CHANNEL THAT SUPPORTS NEAR MEMORY AND FAR MEMORY ACCESS - A semiconductor chip comprising memory controller circuitry having interface circuitry to couple to a memory channel. The memory controller includes first logic circuitry to implement a first memory channel protocol on the memory channel. The first memory channel protocol is specific to a first volatile system memory technology. The interface also includes second logic circuitry to implement a second memory channel protocol on the memory channel. The second memory channel protocol is specific to a second non volatile system memory technology. The second memory channel protocol is a transactional protocol. | 02-06-2014 |
20140089943 | METHOD, SYSTEM AND APPARATUS FOR HANDLING EVENTS FOR PARTITIONS IN A SOCKET WITH SUB-SOCKET PARTITIONING - In one aspect, the issues of events that may impact one or more partitions of sub-socket partitioning in one or more sockets can be handled. Specifically, events for partitions can be handled in a socket with sub-socket partitioning, wherein the events may include reset, interrupts, errors and reliability, availability, and serviceability (RAS) management. | 03-27-2014 |
20140122834 | Generating And Communicating Platform Event Digests From A Processor Of A System - In an embodiment, a processor includes a plurality of counters each to provide a count of a performance metric of at least one core of the processor, a plurality of threshold registers each to store a threshold value with respect to a corresponding one of the plurality of counters, and an event logic to generate an event digest packet including a plurality of indicators each to indicate whether an event occurred based on a corresponding threshold value and a corresponding count value. Other embodiments are described and claimed. | 05-01-2014 |
20140173317 | APPARATUS AND METHOD FOR REDUCING LEAKAGE POWER OF A CIRCUIT - Described is a processor comprising: a plurality of transistors operable to provide dynamically adjustable transistor size, the plurality of transistors coupled at one end to a first power supply and coupled at another end to a second power supply; a circuit coupled to the second power supply, the second power supply to provide power to the circuit; and a power control unit (PCU) to monitor the level of the first power supply, and to dynamically adjust the transistor size of the plurality of transistors so that the second power supply is adjusted to keep the circuit operational. | 06-19-2014 |
20140281445 | PROCESSOR HAVING FREQUENCY OF OPERATION INFORMATION FOR GUARANTEED OPERATION UNDER HIGH TEMPERATURE EVENTS - A processor is described having a semiconductor chip having non volatile storage circuitry. The non volatile storage circuitry has information identifying a maximum operational frequency of the processor at which the processor's operation is guaranteed for an ambient temperature that corresponds to an extreme thermal event. | 09-18-2014 |
20150039920 | REDUCING POWER CONSUMPTION OF UNCORE CIRCUITRY OF A PROCESSOR - In one embodiment, a multi-core processor includes multiple cores and an uncore, where the uncore includes various logic units including a cache memory, a router, and a power control unit (PCU). The PCU can clock gate at least one of the logic units and the cache memory when the multi-core processor is in a low power state to thus reduce dynamic power consumption. | 02-05-2015 |
20160077567 | APPARATUS AND METHOD FOR REDUCING LEAKAGE POWER OF A CIRCUIT - Described is a processor comprising: a plurality of transistors operable to provide dynamically adjustable transistor size, the plurality of transistors coupled at one end to a first power supply and coupled at another end to a second power supply; a circuit coupled to the second power supply, the second power supply to provide power to the circuit; and a power control unit (PCU) to monitor the level of the first power supply, and to dynamically adjust the transistor size of the plurality of transistors so that the second power supply is adjusted to keep the circuit operational. | 03-17-2016 |
20160077568 | METHOD AND APPARATUS FOR SAVING POWER OF A PROCESSOR SOCKET IN A MULTI-SOCKET COMPUTER SYSTEM - Described is an apparatus comprising: a plurality of system agents, at least one system agent including one or more queues; and logic to monitor the one or more queues in at least one system agent and to cause the plurality of system agents to block traffic after satisfaction of a criterion. | 03-17-2016 |
Patent application number | Description | Published |
20090164730 | Method,apparatus,and system for shared cache usage to different partitions in a socket with sub-socket partitioning - A cache that supports sub-socket partitioning is discussed. Specifically, the cache supports different quality of service levels and victim cache line selection for a cache miss operation. The different quality of service levels allow for programmable ceiling usage and floor usage thresholds that allow for different techniques for victim cache line selection. | 06-25-2009 |
20090164739 | Method,system and apparatus for handling events for partitions in a socket with sub-socket partitioning - In one aspect, the issues of events that may impact one or more partitions of sub-socket partitioning in one or more sockets can be handled. Specifically, events for partitions can be handled in a socket with sub-socket partitioning, wherein the events may include reset, interrupts, errors and reliability, availability, and serviceability (RAS) management. | 06-25-2009 |
20090164747 | Method,system and apparatus for memory address mapping for sub-socket partitioning - Sub-socket partitioning is enabled using embodiments of the present invention. In one aspect, the memory mapping is performed to isolate memory access for each of the partitions by assigning a partition address and a generated physical address. | 06-25-2009 |
20090164751 | Method,system and apparatus for main memory access subsystem usage to different partitions in a socket with sub-socket partitioning - Embodiments enable sub-socket partitioning that facilitates access among a plurality of partitions to a shared resource. A round robin arbitration policy is to allow each partition, within a socket, that may utilize a different operating system, access to the shared resource based at least in part on whether an assigned bandwidth parameter for each partition is consumed. Embodiments may further include support for virtual channels. | 06-25-2009 |