Patent application number | Description | Published |
20080238568 | Package embedded three dimensional balun - Methods and apparatus relating to package embedded three dimensional baluns are described. In one embodiment, components of one or more baluns may be embedded in a single semiconductor substrate. Other embodiments are also described. | 10-02-2008 |
20080238587 | PACKAGE EMBEDDED EQUALIZER - A passive equalizer circuit is embedded within a substrate of a package containing an integrated circuit. It is believed that substantial reduction in uneven frequency dependent loss may be achieved for interconnects interconnecting the integrated circuit with other integrated circuits on a printed circuit board. Other aspects are described and claimed. | 10-02-2008 |
20090039986 | PACKAGE-BASED FILTERING AND MATCHING SOLUTIONS - A microelectronic package having a radio frequency (RF) amplifier circuit and, incorporating harmonic rejection filters and matching circuits integrally formed in the package is disclosed. A harmonic rejection filter may comprise a metal-insulator-metal (MIM) capacitor serially coupled between bond pads disposed on a RF amplifier circuit die, a first wire bond coupling a first bond pad to a package output, where the first bond pad is coupled to the output of the RF amplifier, and a second wire bond coupling a second bond pad to a package ground. The harmonic rejection filter may be appropriately configured to filter one or more harmonics at different frequencies. | 02-12-2009 |
20090051477 | PLANAR TRANSFORMER, TRANSMISSION LINE BALUN AND METHOD OF FABRICATION - A planar transformer or balun device, having small trace spacing and high mutual coupling coefficient, and a method of fabricating the same is disclosed. The method may comprise providing a first and a second inductor on a primary and a second substrate respectively, interleaving at least partially the first inductor with the second inductor, coupling the primary and the secondary substrates to form a unitary structure, and providing electrical contacts to couple the first and second inductors with another device or circuit. | 02-26-2009 |
20090321876 | SYSTEM WITH RADIO FREQUENCY INTEGRATED CIRCUITS - A semiconductor package comprises an integrated radio frequency circuit that may be provided in a semiconductor die. A ground plane may be attached to the semiconductor die. The ground plane is selectively patterned in a direction that is perpendicular to an inductor trace of an inductor of the radio frequency circuit. In some embodiments, the ground plane may be selectively patterned to allow an eddy current in the semiconductor package not to flow in opposite direction of a main current in the inductor. In one example, the ground plane may be a portion of the semiconductor package substrate or a die back metallization of the semiconductor die. | 12-31-2009 |
20090322304 | SERIES AND PARALLEL HYBRID SWITCHED CAPACITOR NETWORKS FOR IC POWER DELIVERY - Series switches for power delivery. A regulator operated as a current source is arranged in parallel with a switched capacitor divider. A switched capacitor divider is configured in series with a plurality of linear regulators with each regulating one of a plurality of voltage outputs from the switched capacitor divider. In another embodiment, a series switch bridge has a first pair of switches connected in series with a second pair of switches across a voltage input, each switch within a pair of switches is switched in-phase with the other while the first pair of switches is switched out of phase with the second pair of switches. A balancing capacitor is coupled across one switch in both the first and second pair to be in parallel when either of the pair of switches is closed to reduce a charge imbalance between the switches. | 12-31-2009 |
20090322384 | Drive and startup for a switched capacitor divider - Drive and startup circuits are described particularly suitable for use with a switched capacitor divider. In one example, a drive circuit has a level shifter coupled to a gate of each switch of a switched capacitor drive circuit to couple alternating current into the respective gate, a positive phase low side driver coupled to each level shifter to drive the gates of the top switch path through the respective level shifters, and a negative phase low side driver coupled to each level shifter to drive gates of the bottom switch path through the respective level shifters. A startup circuit, such as a capacitive soft start circuit may be used to slow the application of the current to each switch. | 12-31-2009 |
20090322414 | INTEGRATION OF SWITCHED CAPACITOR NETWORKS FOR POWER DELIVERY - Switched capacitor networks for power delivery to packaged integrated circuits. In certain embodiments, the switched capacitor network is employed in place of at least one stage of a cascaded buck converter for power delivery. In accordance with particular embodiments of the present invention, a two-stage power delivery network comprising both switched capacitor stage and a buck regulator stage deliver power to a microprocessor or other packaged integrated circuit (IC). In further embodiments, a switched capacitor stage is implemented with a series switch module comprising low voltage MOS transistors that is then integrated onto a package of at least one IC to be powered. In certain embodiments, a switched capacitor stage is implemented with capacitors formed on a motherboard, embedded into an IC package or integrated into a series switch module. | 12-31-2009 |
20110115597 | TRANSFORMER DEVICES - A planar transformer or balun device, having small trace spacing and high mutual coupling coefficient, and a method of fabricating the same is disclosed. The method may comprise providing a first and a second inductor on a primary and a second substrate respectively, interleaving at least partially the first inductor with the second inductor, coupling the primary and the secondary substrates to form a unitary structure, and providing electrical contacts to couple the first and second inductors with another device or circuit. | 05-19-2011 |
20120092076 | PACKAGE-BASED FILTERING AND MATCHING SOLUTIONS - A microelectronic package having a radio frequency (RF) amplifier circuit and, incorporating harmonic rejection filters and matching circuits integrally formed in the package is disclosed. A harmonic rejection filter may comprise a metal-insulator-metal (MIM) capacitor serially coupled between bond pads disposed on a RF amplifier circuit die, a first wire bond coupling a first bond pad to a package output, where the first bond pad is coupled to the output of the RF amplifier, and a second wire bond coupling a second bond pad to a package ground. The harmonic rejection filter may be appropriately configured to filter one or more harmonics at different frequencies. | 04-19-2012 |
20120280366 | RADIO- AND ELECTROMAGNETIC INTERFERENCE THROUGH-SILICON VIAS FOR STACKED- DIE PACKAGES, AND METHODS OF MAKING SAME - An apparatus includes a radio-frequency die with shielding through-silicon vias and a die backside lattice lid that shield a sector in the RF die from radio - and electromagnetic interference. | 11-08-2012 |
20120280380 | HIGH PERFORMANCE GLASS-BASED 60 GHZ / MM-WAVE PHASED ARRAY ANTENNAS AND METHODS OF MAKING SAME - A glass-based, high-performance 60 GHz/mm-wave antenna includes cavities disposed in a phased-array antenna (PAA) substrate. The cavities are disposed below planar antenna elements. Emitter traces are disposed on the PAA substrate opposite the planar antenna elements and the emitter traces, the cavities, and the planar antenna elements are vertically aligned. | 11-08-2012 |
20120280860 | CHIP PACKAGES INCLUDING THROUGH-SILICON VIA DICE WITH VERTICALLY INEGRATED PHASED-ARRAY ANTENNAS AND LOW-FREQUENCY AND POWER DELIVERY SUBSTRATES - An apparatus includes a die with through-silicon vias and radio frequency integrated circuit capabilities and it is vertically integrated with a phased-array antenna substrate. The through-silicon via and a radio frequency integrated circuit is coupled to a plurality of antenna elements disposed on the phased-array antenna substrate where each of the plurality of antenna elements is coupled to the through-silicon vias and radio frequency integrated circuit through a plurality of through-silicon vias. A process of assembling the through-silicon vias and radio frequency integrated circuit to the phased-array antenna substrate includes testing the apparatus. | 11-08-2012 |
20130058141 | SERIES AND PARALLEL HYBRID SWITCHED CAPACITOR NETWORKS FOR IC POWER DELIVERY - Series switches for power delivery. A regulator operated as a current source is arranged in parallel with a switched capacitor divider. A switched capacitor divider is configured in series with a plurality of linear regulators with each regulating one of a plurality of voltage outputs from the switched capacitor divider. In another embodiment, a series switch bridge has a first pair of switches connected in series with a second pair of switches across a voltage input, each switch within a pair of switches is switched in-phase with the other while the first pair of switches is switched out of phase with the second pair of switches. A balancing capacitor is coupled across one switch in both the first and second pair to be in parallel when either of the pair of switches is closed to reduce a charge imbalance between the switches. | 03-07-2013 |
20130335059 | FULLY INTEGRATED VOLTAGE REGULATORS FOR MULTI-STACK INTEGRATED CIRCUIT ARCHITECTURES - A voltage regulator for one or more dies in a multi-stack integrated circuit includes an inductor located on a die, a voltage controller that is electrically coupled to the inductor and is also located on the die, and a capacitor that is electrically coupled to the inductor and the voltage controller and is also located on the die. The inductor defines an interior space and the voltage controller and the capacitor are located within the interior space of the inductor. The inductor can be a lateral inductor or a through layer via inductor. The multi-stack integrated circuit may have multiple dies. A voltage controller may be electrically coupled to each of the dies, although it may be located on only one of the dies. Alternatively, separate voltage controllers may be electrically coupled to each of the multiple dies and may be located on each of the respective dies. | 12-19-2013 |
20140001643 | HYBRID PACKAGE TRANSMISSION LINE CIRCUITS | 01-02-2014 |
20140027880 | INTEGRATED INDUCTOR FOR INTEGRATED CIRCUIT DEVICES - A three-dimensional inductor is formed in an integrated circuit die using conductive through-body-vias which pass through the body of the die and contact one or more metal interconnect layers on the front side of the die and terminate on the back side of the die. In another embodiment, the through-body-vias may pass through a dielectric material disposed in a plug in the body of the die. In yet another aspect, a transformer may be formed by coupling multiple inductors formed using through-body-vias. In still another aspect, a three-dimensional inductor may include conductors formed of stacks of on chip metallization layers and conductive through-layer-vias disposed in insulation layers between metallization layers. Other embodiments are described. | 01-30-2014 |
20140092574 | INTEGRATED VOLTAGE REGULATORS WITH MAGNETICALLY ENHANCED INDUCTORS - Magnetically enhanced inductors integrated with microelectronic devices at chip-level. In embodiments, magnetically enhanced inductors include a through substrate vias (TSVs) with fill metal to carry an electrical current proximate to a magnetic layer disposed on a substrate through which the TSV passes. In certain magnetically enhanced inductor embodiments, a TSV fill metal is disposed within a magnetic material lining the TSV. In certain magnetically enhanced inductor embodiments, a magnetically enhanced inductor includes a plurality of interconnected TSVs disposed proximate to a magnetic material layer on a side of a substrate. In embodiments, voltage regulation circuitry disposed on a first side of a substrate is integrated with one or more magnetically enhanced inductors utilizing a TSV passing through the substrate. In further embodiments, integrated circuitry on a same substrate as the magnetically enhanced inductor, or on another substrate stacked thereon, completes the VR and/or is powered by the VR circuitry. | 04-03-2014 |
20140159681 | SERIES AND PARALLEL HYBRID SWITCHED CAPACITOR NETWORKS FOR IC POWER DELIVERY - Series switches for power delivery. A regulator operated as a current source is arranged in parallel with a switched capacitor divider. A switched capacitor divider is configured in series with a plurality of linear regulators with each regulating one of a plurality of voltage outputs from the switched capacitor divider. In another embodiment, a series switch bridge has a first pair of switches connected in series with a second pair of switches across a voltage input, each switch within a pair of switches is switched in-phase with the other while the first pair of switches is switched out of phase with the second pair of switches. A balancing capacitor is coupled across one switch in both the first and second pair to be in parallel when either of the pair of switches is closed to reduce a charge imbalance between the switches. | 06-12-2014 |
20140176368 | PACKAGE STRUCTURES INCLUDING DISCRETE ANTENNAS ASSEMBLED ON A DEVICE - Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods and structures may include forming a package structure comprising a discrete antenna disposed on a back side of a device, wherein the discrete antenna comprises an antenna substrate, a through antenna substrate via vertically disposed through the antenna substrate. A through device substrate via that is vertically disposed within the device is coupled with the through antenna substrate via, and a package substrate is coupled with an active side of the device. | 06-26-2014 |
20140191905 | INTEGRATION OF MILLIMETER WAVE ANTENNAS ON MICROELECTRONIC SUBSTRATES - A high performance antenna incorporated on a microelectronic substrate by forming low-loss dielectric material structures in the microelectronic substrates and forming the antenna on the low-loss dielectric material structures. The low-loss dielectric material structures may be fabricated by forming a cavity in a build-up layer of the microelectronic substrate and filling the cavity with a low-loss dielectric material. | 07-10-2014 |
20140266902 | SINGLE-PACKAGE PHASED ARRAY MODULE WITH INTERLEAVED SUB-ARRAYS - Embodiments of the present disclosure are directed to a single-package communications device that includes an antenna module with a plurality of independently selectable arrays of antenna elements. The antenna elements of the different arrays may send and/or receive data signals over different ranges of signal angles. The communications device may further include a switch module to separately activate the individual arrays. In some embodiments, a radio frequency (RF) communications module may be included in the package of the communications device. In some embodiments, the RF communications module may be configured to communicate over a millimeter-wave (mm-wave) network using the plurality of arrays of antenna elements. | 09-18-2014 |
20140333480 | CHIP PACKAGES INCLUDING THROUGH-SILICON VIA DICE WITH VERTICALLY INEGRATED PHASED-ARRAY ANTENNAS AND LOW-FREQUENCY AND POWER DELIVERY SUBSTRATES - An apparatus includes a die with through-silicon vias and radio frequency integrated circuit capabilities and it is vertically integrated with a phased-array antenna substrate. The through-silicon via and a radio frequency integrated circuit is coupled to a plurality of antenna elements disposed on the phased-array antenna substrate where each of the plurality of antenna elements is coupled to the through-silicon vias and radio frequency integrated circuit through a plurality of through-silicon vias. A process of assembling the through-silicon vias and radio frequency integrated circuit to the phased-array antenna substrate includes testing the apparatus. | 11-13-2014 |
20150069629 | HYBRID PACKAGE TRANSMISSION LINE CIRCUITS - “Hybrid” transmission line circuits employing multiple interconnect levels for the propagation, or return, of a single signal line across a package length are described. In package transmission line circuit embodiments, a signal line employs co-located traces in two different interconnect levels that are electrically coupled together. In further embodiments, a reference plane is provided above, below or co-planar with at least one of the co-locate traces. In embodiments, a balanced signal line pair includes first and second co-located traces in two adjacent interconnect levels as a propagation signal line and third and fourth co-located traces in the two adjacent interconnect levels as a return signal line with a ground plane co-planar with, and/or above and/or below the two adjacent interconnect levels. | 03-12-2015 |
20150084139 | DEVICE, SYSTEM AND METHOD FOR PROVIDING MEMS STRUCTURES OF A SEMICONDUCTOR PACKAGE - Techniques and mechanisms for providing precisely fabricated structures of a semiconductor package. In an embodiment, a build-up carrier of the semiconductor package includes a layer of porous dielectric material. Seed copper and plated copper is disposed on the layer of porous dielectric material. Subsequent etching is performed to remove copper adjacent to the layer of porous dielectric material, forming a gap separating a suspended portion of a MEMS structure from the layer of porous dielectric material. In another embodiment, the semiconductor package includes a copper structure disposed between portions of an insulating layer or portions of a layer of silicon nitride material. The layer of silicon nitride material couples the insulating layer to another insulating layer. One or both of the insulating layers are each protected from desmear processing with a respective release layer structure. | 03-26-2015 |
20150084830 | ANTENNA INTEGRATED IN A PACKAGE SUBSTRATE - An antenna integrated in a package substrate, the antenna comprising an upper antenna element, a lower antenna element and a coupling element disposed between the upper antenna element and the lower antenna element, the coupling element comprising an aperture, and configured to provide a coupling between the upper antenna element and the lower antenna element. | 03-26-2015 |