Patent application number | Description | Published |
20090074884 | FAMILY OF PFKFB3 INHIBITORS WITH ANTI-NEOPLASTIC ACTIVITIES - A methods and compounds for inhibiting 6-phosphofructo-2-kinase/fructose-2,6-bisphosphatase 3 (PFKFB3) are described. Also described are methods of inhibiting cell proliferation, treating cancer, and screening compounds to determine their ability to inhibit PFKFB3. | 03-19-2009 |
20100267815 | PFKFB4 Inhibitors And Methods Of Using The Same - Methods of reducing expression of 6-phosphofructo-2-kinase/fructose-2,6-bisphosphatase 4 (PFKFB4) and methods of treating a cancer in a cell are provided, the methods including contacting a cell with an effective amount of a PFKFB4 inhibitor. Short hairpin RNA (shRNA) and small interfering RNA (siRNA) inhibitors of PFKFB4 and their methods of use are also provided. | 10-21-2010 |
20110212994 | Small Molecule Choline Kinase Inhibitors, Screening Assays, and Methods for Safe and Effective Treatment of Neoplastic Disorders - Small molecule choline kinase inhibitors, pharmaceutical compositions thereof, and screening methods for identifying and evaluating choline kinase inhibitors are provided. Safe and effective methods for treating subjects suffering from a disorder or disease characterized by neoplastic cell proliferation employing the choline kinase inhibitors are also provided. | 09-01-2011 |
20110257211 | Small-Molecule Choline Kinase Inhibitors as Anti-Cancer Therapeutics - Small molecule choline kinase inhibitors having the following formula: | 10-20-2011 |
20120177749 | FAMILY OF PFKFB3 INHIBITORS WITH ANTI-NEOPLASTIC ACTIVITIES - A methods and compounds for inhibiting 6-phosphofructo-2-kinase/fructose-2,6-bisphosphatase 3 (PFKFB3) are described. Also described are methods of inhibiting cell proliferation, treating cancer, and screening compounds to determine their ability to inhibit PFKFB3. | 07-12-2012 |
20130012557 | Small Molecule Choline Kinase Inhibitors, Screening Assays, and Methods for Treatment of Neoplastic Disorders - Small molecule choline kinase inhibitors, pharmaceutical compositions thereof, and screening methods for identifying and evaluating choline kinase inhibitors are provided. Safe and effective methods for treating subjects suffering from a disorder or disease characterized by neoplastic cell proliferation employing the choline kinase inhibitors are also provided. | 01-10-2013 |
20130059879 | Small Molecule Inhibitors of PFKFB3 and Glycolytic Flux and Their Methods of Use as Anti-Cancer Therapeutics - Small molecule inhibitors of 6-phosphofructo-2-kinase/fructose-2,6-biphosphatase 3 (PFKFB3) having the following formula: Formula (1) are provided herein. Also provided herein are pharmaceutical compositions containing Formula I compounds, together with methods of treating cancer, methods of inhibiting PFK.FB3 enzymatic activity, methods of inhibiting glycolytic flux, and methods of treating tumors by administering an effective amount of a Formula I compound. | 03-07-2013 |
Patent application number | Description | Published |
20090232151 | MULTI-RATE BACKPLANE TRANSCEIVER - An apparatus is disclosed that includes first transceiver circuitry adapted for transmitting and receiving Ethernet data over a network using a first Ethernet communication protocol at a first data rate, second transceiver circuitry adapted for transmitting and receiving Ethernet data over a network using a second Ethernet communication protocol at a second data rate; and third transceiver circuitry adapted for transmitting and receiving Ethernet data over a network using a third Ethernet communication protocol at a third data rate. | 09-17-2009 |
20100135442 | Adaptive offset adjustment algorithm - An apparatus and method is disclosed to compensate for one or more offsets in a communications signal. A communications receiver may carry out an offset adjustment algorithm to compensate for the one or more offsets. An initial search procedure determines one or more signal metric maps for one or more selected offset adjustment corrections from the one or more offset adjustment corrections. The offset adjustment algorithm determines one or more optimal points for one or more selected offset adjustment correction based upon the one or more signal maps. The adaptive offset algorithm adjusts each of the one or more selected offset adjustment corrections to their respective optimal points and/or each of one or more non-selected offset adjustment corrections to a corresponding one of a plurality of possible offset corrections to provide one or more adjusted offset adjustment corrections. A tracking mode procedure optimizes the one or more adjusted offset adjustment corrections. | 06-03-2010 |
20120002713 | MULTI-PROTOCOL COMMUNICATIONS RECEIVER WITH SHARED ANALOG FRONT-END - According to an example embodiment, a communications receiver may include a variable gain amplifier (VGA) configured to amplify received signals, a VGA controller configured to control the VGA, a plurality of analog to digital converter (ADC) circuits coupled to an output of the VGA, wherein the plurality of ADC circuits are operational when the communications receiver is configured to process signals of a first communications protocol, and wherein only a subset of the ADC circuits are operational when the communications receiver is configured to process signals of a second communications protocol. | 01-05-2012 |
20120007640 | Multi-Channel Multi-Protocol Transceiver With Independent Channel Configuration Using Single Frequency Reference Clock Source - A circuit for producing one of a plurality of output clock frequencies from a single, constant input reference clock frequency. The circuit comprises a reference clock system and a phase lock loop. The reference clock system includes a bypass path, a divider path including a first integer divider, and a multiplexer. A divisor of the first integer divider is based on a selected communications protocol of a group of possible communications protocols. The multiplexer is configured to route the bypass path or the divider path based on the selected communications protocol. The phase lock loop includes a voltage controlled oscillator and a feedback path. The feedback path includes a second integer divider. A divisor of the second integer divider is based on the selected communications protocol. The reference clock system is configured to receive a constant reference clock frequency. The voltage controlled oscillator is configured to produce one of a plurality of output clock frequencies corresponding to the selected communications protocol. The selected output clock frequency is produced based on at least one of the routing of the multiplexer, the divisor of the first integer divider, and the divisor of the second integer divider. | 01-12-2012 |
20130121391 | Adaptive Offset Adjustment Algorithm - An apparatus and method is disclosed to compensate for one or more offsets in a communications signal. A communications receiver may carry out an offset adjustment algorithm to compensate for the one or more offsets. An initial search procedure determines one or more signal metric maps for one or more selected offset adjustment corrections from the one or more offset adjustment corrections. The offset adjustment algorithm determines one or more optimal points for one or more selected offset adjustment correction based upon the one or more signal maps. The adaptive offset algorithm adjusts each of the one or more selected offset adjustment corrections to their respective optimal points and/or each of one or more non-selected offset adjustment corrections to a corresponding one of a plurality of possible offset corrections to provide one or more adjusted offset adjustment corrections. A tracking mode procedure optimizes the one or more adjusted offset adjustment corrections. | 05-16-2013 |
20130243072 | MULTI-PROTOCOL COMMUNICATIONS RECEIVER WITH SHARED ANALOG FRONT-END - According to an example embodiment, a communications receiver may include a variable gain amplifier (VGA) configured to amplify received signals, a VGA controller configured to control the VGA, a plurality of analog to digital converter (ADC) circuits coupled to an output of the VGA, wherein the plurality of ADC circuits are operational when the communications receiver is configured to process signals of a first communications protocol, and wherein only a subset of the ADC circuits are operational when the communications receiver is configured to process signals of a second communications protocol. | 09-19-2013 |
20140075076 | Overclocked Line Rate for Communication with PHY Interfaces - A system side interface of a PHY chip used in conjunction with a 100GBASE backplane, sends and receives data using an NRZ signal format, but at a data rate of between about 26.5 Gbps/per lane to 27.2 Gbps/per lane, which is consistent with the PAM 4 signaling protocol. Thus, chip-to-chip communications between a PHY chip and a switch or controller chip can use an “overclocked” NRZ signaling format, reducing the amount of logic needed, which in turn can reduce signal latency, and reduce the chip area and power consumption required to implement the logic. | 03-13-2014 |
20140153620 | USE OF MULTI-LEVEL MODULATION SIGNALING FOR SHORT REACH DATA COMMUNICATIONS - A short reach communication system includes a plurality of communication SERDES that communicate data over a short reach channel medium such as a backplane connection (e.g., PCB trace) between, for example, chips located on a common PCB. A multi-level modulated data signal is generated to transmit/receive data over the short reach channel medium. Multi-level modulated data signals, such as four-level PAM, reduce the data signal rate therefore reducing insertion loss, power, complexity of the circuits and required chip real estate. | 06-05-2014 |
20150146766 | USE OF MULTI-LEVEL MODULATION SIGNALING FOR SHORT REACH DATA COMMUNICATIONS - A short reach communication system includes a plurality of communication SERDES that communicate data over a short reach channel medium such as a backplane connection (e.g., PCB trace) between, for example, chips located on a common PCB. A multi-level modulated data signal is generated to transmit/receive data over the short reach channel medium. Multi-level modulated data signals, such as four-level PAM, reduce the data signal rate therefore reducing insertion loss, power, complexity of the circuits and required chip real estate. | 05-28-2015 |