Patent application number | Description | Published |
20090133254 | Components with posts and pads - A packaged microelectronic element includes connection component incorporating a dielectric layer ( | 05-28-2009 |
20100001410 | FLIP CHIP OVERMOLD PACKAGE - An integrated circuit (IC) package having a packaging substrate, an IC disposed onto the packaging substrate, and a rigid support member attached to the substrate layer through an adhesive spacer is provided. The packaging substrate includes multiple decoupling capacitors positioned thereon around the IC. A heat sink is placed over the IC. The rigid support member provides enhanced structural support for the IC packaging and there is ample space between a bottom surface of the rigid support member and the packaging substrate to allow the placement of the decoupling capacitors underneath the rigid support member. | 01-07-2010 |
20100193970 | MICRO PIN GRID ARRAY WITH PIN MOTION ISOLATION - A microelectronic package includes a microelectronic element having faces and contacts, a flexible substrate overlying and spaced from a first face of the microelectronic element, and a plurality of conductive terminals exposed at a surface of the flexible substrate. The conductive terminals are electrically interconnected with the microelectronic element and the flexible substrate includes a gap extending at least partially around at least one of the conductive terminals. In certain embodiments, the package includes a support layer, such as a compliant layer, disposed between the first face of the microelectronic element and the flexible substrate. In other embodiments, the support layer includes at least one opening that is at least partially aligned with one of the conductive terminals. | 08-05-2010 |
20100232129 | MICROELECTRONIC PACKAGES AND METHODS THEREFOR - A method of making a microelectronic assembly includes providing a microelectronic package having a substrate, a microelectronic element overlying the substrate and at least two conductive elements projecting from a surface of the substrate, the at least two conductive elements having surfaces remote from the surface of the substrate. The method includes compressing the at least two conductive elements so that the remote surfaces thereof lie in a common plane, and after the compressing step, providing an encapsulant material around the at least two conductive elements for supporting the microelectronic package and so that the remote surfaces of the at least two conductive elements remain accessible at an exterior surface of the encapsulant material. | 09-16-2010 |
20100258956 | MICROELECTRONIC PACKAGES AND METHODS THEREFOR - A microelectronic package includes a microelectronic element having faces and contacts, the microelectronic element having an outer perimeter, and a substrate overlying and spaced from a first face of the microelectronic element, whereby an outer region of the substrate extends beyond the outer perimeter of the microelectronic element. The microelectronic package includes a plurality of etched conductive posts exposed at a surface of the substrate and being electrically interconnected with the microelectronic element, whereby at least one of the etched conductive posts is disposed in the outer region of the substrate. The package includes an encapsulating mold material in contact with the microelectronic element and overlying the outer region of the substrate, the encapsulating mold material extending outside of the etched conductive posts for defining an outermost edge of the microelectronic package. | 10-14-2010 |
20110165733 | MICROELECTRONIC PACKAGES AND METHODS THEREFOR - A method of making a microelectronic assembly can include molding a dielectric material around at least two conductive elements which project above a height of a substrate having a microelectronic element mounted thereon, so that remote surfaces of the conductive elements remain accessible and exposed within openings extending from an exterior surface of the molded dielectric material. The remote surfaces can be disposed at heights from said surface of said substrate which are lower or higher than a height of the exterior surface of the molded dielectric material from the substrate surface. The conductive elements can be arranged to simultaneously carry first and second different electric potentials: e.g., power, ground or signal potentials. | 07-07-2011 |
20110204476 | Electronic Package with Fluid Flow Barriers - The present invention is directed to a method and electronic computer package that is formed by placing an integrated circuit, having a plurality of bonding pads with solder bumps deposited thereon, in contact with the substrate so that one of the plurality of solder bumps is in superimposition with respect to one of the contacts and one of the plurality of bonding pads, with a volume being defined between region of the substrate in superimposition with the integrated circuit. A portion of the volume is filled with a quantity of underfill. A fluid flow bather is formed on the substrate and defines a perimeter of the volume, defining a flow restricted region. The fluid flow barrier has dimensions sufficient to control the quantity of underfill egressing from the flow restricted region. | 08-25-2011 |
20110260320 | METHOD OF MAKING A CONNECTION COMPONENT WITH POSTS AND PADS - A packaged microelectronic element includes connection component incorporating a dielectric layer ( | 10-27-2011 |
20110269272 | MICROELECTRONIC PACKAGES AND METHODS THEREFOR - A microelectronic package includes a microelectronic element having faces and contacts, the microelectronic element having an outer perimeter, and a substrate overlying and spaced from a first face of the microelectronic element, whereby an outer region of the substrate extends beyond the outer perimeter of the microelectronic element. The microelectronic package includes a plurality of etched conductive posts exposed at a surface of the substrate and being electrically interconnected with the microelectronic element, whereby at least one of the etched conductive posts is disposed in the outer region of the substrate. The package includes an encapsulating mold material in contact with the microelectronic element and overlying the outer region of the substrate, the encapsulating mold material extending outside of the etched conductive posts for defining an outermost edge of the microelectronic package. | 11-03-2011 |
20120126407 | WAFER LEVEL CHIP PACKAGE AND A METHOD OF FABRICATING THEREOF - Wafer level chip packages including risers having sloped sidewalls and methods of fabricating such chip packages are disclosed. The inventive wafer level chip packages may advantageously be used in various microelectronic assemblies. | 05-24-2012 |
20120155055 | SEMICONDUCTOR CHIP ASSEMBLY AND METHOD FOR MAKING SAME - A microelectronic assembly may include a substrate including a rigid dielectric layer having electrically conductive elements, a microelectronic element having a plurality of contacts exposed at a face thereof, and conductive vias extending through a compliant dielectric layer overlying the rigid dielectric layer. The vias electrically connect the substrate contacts respectively to the conductive elements, and the substrate contacts are joined respectively to the contacts of the microelectronic element. The vias, compliant layer and substrate contacts are adapted to appreciably relieve stress at the substrate contacts associated with differential thermal contact and expansion of the assembly. | 06-21-2012 |
20120268899 | REINFORCED FAN-OUT WAFER-LEVEL PACKAGE - A microelectronic package includes a microelectronic element including a first surface having contacts thereon, a second surface remote therefrom, and edge surfaces extending between the first and second surfaces. A reinforcing layer adheres to the at least one edge surface and extends in a direction away therefrom, the reinforcing layer not extending along the first surface of the microelectronic element. A conductive redistribution layer including a plurality of conductive elements extends from the contacts along the first surface and along a surface of the reinforcing layer beyond the at least one edge surface. An encapsulant overlies at least the reinforcing layer. The microelectronic element has a first coefficient of thermal expansion, the encapsulant has a second coefficient of thermal expansion, and the reinforcing layer has a third coefficient of thermal expansion that is between the first and second coefficients of thermal expansion. | 10-25-2012 |
20120280386 | PACKAGE-ON-PACKAGE ASSEMBLY WITH WIRE BONDS TO ENCAPSULATION SURFACE - A microelectronic assembly includes a substrate having a first surface and a second surface remote from the first surface. A microelectronic element overlies the first surface and first electrically conductive elements are exposed at one of the first surface and the second surface. Some of the first conductive elements are electrically connected to the microelectronic element. Wire bonds have bases joined to the conductive elements and end surfaces remote from the substrate and the bases, each wire bond defining an edge surface extending between the base and the end surface. An encapsulation layer extends from the first surface and fills spaces between the wire bonds such that the wire bonds are separated by the encapsulation layer. Unencapsulated portions of the wire bonds are defined by at least portions of the end surfaces of the wire bonds that are uncovered by the encapsulation layer. | 11-08-2012 |
20130203216 | PACKAGE-ON-PACKAGE ASSEMBLY WITH WIRE BONDS TO ENCAPSULATION SURFACE - A method of making a microelectronic package includes forming a dielectric encapsulation layer on an in-process unit having a substrate having a first surface and a second surface remote therefrom. A microelectronic element is mounted to the first surface of the substrate, and a plurality of conductive elements exposed at the first surface, at least some of which are electrically connected to the microelectronic element. Wire bonds have bases joined to the conductive elements and end surfaces remote from the bases and define an edge surface extending away between the base and the end surface. The encapsulation layer is formed to at least partially cover the first surface and portions of the wire bonds with unencapsulated portions of the wire bonds being defined by at least one of the end surface or a portion of the edge surface that is uncovered thereby. | 08-08-2013 |
20140145329 | FINE PITCH MICROCONTACTS AND METHOD FOR FORMING THEREOF - A method includes applying a final etch-resistant material to an in-process substrate so that the final etch-resistant material at least partially covers first microcontact portions integral with the substrate and projecting upwardly from a surface of the substrate, and etching the surface of the substrate so as to leave second microcontact portions below the first microcontact portions and integral therewith, the final etch-resistant material at least partially protecting the first microcontact portions from etching during the further etching step. A microelectronic unit includes a substrate, and a plurality of microcontacts projecting in a vertical direction from the substrate, each microcontact including a base region adjacent the substrate and a tip region remote from the substrate, each microcontact having a horizontal dimension which is a first function of vertical location in the base region and which is a second function of vertical location in the tip region. | 05-29-2014 |
20140213021 | MICROELECTRONIC PACKAGES AND METHODS THEREFOR - A method of making a microelectronic assembly can include molding a dielectric material around at least two conductive elements which project above a height of a substrate having a microelectronic element mounted thereon, so that remote surfaces of the conductive elements remain accessible and exposed within openings extending from an exterior surface of the molded dielectric material. The remote surfaces can be disposed at heights from said surface of said substrate which are lower or higher than a height of the exterior surface of the molded dielectric material from the substrate surface. The conductive elements can be arranged to simultaneously carry first and second different electric potentials: e.g., power, ground or signal potentials. | 07-31-2014 |