Patent application number | Description | Published |
20090111420 | DEGENERATED PASSIVE MIXER IN SAW-LESS RECEIVER - In a SAW-less receiver involving a passive mixer, novel degenerative impedance elements having substantial impedances are disposed in incoming signal paths between the differential signal output leads of a low-noise amplifier (LNA) and the differential signal input leads of the passive mixer. The passive mixer outputs signals to a transimpedance amplifier and baseband filter (TIA). Providing the novel degenerative impedance elements decreases noise in the overall receiver as output from the TIA, with only minimal degradation of other receiver performance characteristics. In some examples, the passive mixer receives local oscillator signals having duty cycles of substantially less than fifty percent. In some examples, the degenerative impedance elements can have one of several impedances. | 04-30-2009 |
20090239592 | REDUCED POWER-CONSUMPTION RECEIVERS - An exemplary embodiment disclosed comprises a mixer having a plurality of input leads; a first degenerative impedance element coupled to a first input lead of the mixer; a second degenerative impedance element coupled to a second input lead of the mixer; and a local oscillator (LO) system comprising a plurality of duty cycle modes to generate a LO signal for the mixer, the local oscillator system operates in a first duty cycle based on a first gain state of the mixer, and in a second duty cycle based on a second gain state of the mixer. | 09-24-2009 |
20100029323 | SYSTEMS AND METHODS FOR ADJUSTING THE GAIN OF A RECEIVER THROUGH A GAIN TUNING NETWORK - A circuit is described. The circuit includes a low noise amplifier (LNA), a passive switching core (PSC), a transimpedance amplifier filter (TIA-filter) and a degenerative-impedance gain-tuning network (Zdeg network) having a first Zdeg network input lead, a second Zdeg network input lead, a first Zdeg network output lead and a second Zdeg network output lead, wherein the first Zdeg network input lead is coupled to a first output lead of the LNA and the second Zdeg network input lead is coupled to a second output lead of the LNA, and wherein the first Zdeg network output lead is coupled to a first signal input lead of the PSC and the second Zdeg network output lead is coupled to a second signal input lead of the PSC. The LNA, the Zdeg network, the PSC, and the TIA-filter together form a receiver. A receiver gain is adjusted by the Zdeg network. | 02-04-2010 |
20110018635 | MULTI-MODE LOW NOISE AMPLIFIER WITH TRANSFORMER SOURCE DEGENERATION - A multi-mode low noise amplifier (LNA) with transformer source degeneration is described. In an exemplary design, the multi-mode LNA includes first, second, and third transistors and first and second inductors. The first transistor has its source coupled to the first inductor, amplifies an input signal, and provides a first amplified signal in a first mode. The second transistor has its source coupled to the second inductor, amplifies the input signal, and provides a second amplified signal in a second mode. The third transistor has its source coupled to the second inductor. The first and third transistors receive the input signal and conduct current through the first and second inductors, respectively, in a third mode. The first transistor observes source degeneration from a transformer formed by the first and second inductors, amplifies the input signal, and provides a third amplified signal in the third mode. | 01-27-2011 |
20110128084 | METHODS AND APPARATUS FOR INDUCTORS WITH INTEGRATED PASSIVE AND ACTIVE ELEMENTS - An integrated circuit is described. The integrated circuit includes an inductor that has a large empty area in the center of the inductor. The integrated circuit also includes additional circuitry. The additional circuitry is located within the large empty area in the center of the inductor. The additional circuitry may include a capacitor bank, transistors, electrostatic discharge (ESD) protection circuitry and other miscellaneous passive or active circuits. | 06-02-2011 |
20140105336 | REDUCED POWER-CONSUMPTION RECEIVERS - An exemplary embodiment disclosed comprises a mixer having a plurality of input leads; a first degenerative impedance element coupled to a first input lead of the mixer; a second degenerative impedance element coupled to a second input lead of the mixer; and a local oscillator (LO) system comprising a plurality of duty cycle modes to generate a LO signal for the mixer, the local oscillator system operates in a first duty cycle based on a first gain state of the mixer, and in a second duty cycle based on a second gain state of the mixer. | 04-17-2014 |
Patent application number | Description | Published |
20100289579 | SWITCHABLE INPUT PAIR OPERATIONAL AMPLIFIERS - Techniques for designing a switchable amplifier are described. In one aspect, a switchable amplifier including a core amplifier circuit configured to selectively enable one or more parallel input transistor pairs is described. The core amplifier circuit comprises a permanently enabled input transistor pair. In another aspect, a device operable between a first mode of operation and a second mode of operation comprising a receiver logic circuit for selectably enabling and disabling a plurality of input transistor pairs within a switchable amplifier is described where the switchable amplifier also includes a core amplifier circuit coupled to the receiver logic circuit for selectably enabling and disabling a transistor pair therein. The described switchable amplifiers result in the ability to provide varying amplifier performance characteristics based upon the current mode of operation of the device. | 11-18-2010 |
20100311378 | MULTIPLE MULTI-MODE LOW-NOISE AMPLIFIER RECEIVER WITH SHARED DEGENERATIVE INDUCTORS - A device with multiple multi-mode low-noise amplifiers (LNAs), each with common operating modes and separate operating frequency bands, are coupled to shared degenerative inductors for common operating modes. Common load inductors are coupled to the multi-mode LNA outputs to reduce the number of load inductors required. The multi-mode LNAs have parallel transistor gain stages and form part of an integrated circuit (IC) for use in a wireless communication receiver. Each multi-mode LNA has the capability to switch between at least one higher linearity transistor gain stage and at least one lower linearity transistor gain stage for different operating modes. Multiple lower linearity transistor gain stages for different multi-mode LNAs may be merged into a single lower linearity transistor gain stage shared among multiple multi-mode LNAs through multiple RF switches between a set of common RF inputs and common inputs and common input matching networks. | 12-09-2010 |
20110200161 | DIFFERENTIAL QUADRATURE DIVIDE-BY-THREE CIRCUIT WITH DUAL FEEDBACK PATH - A divide-by-three circuit includes a chain of three dynamic flip-flops and a feedback circuit of combinatorial logic. The divide-by-three circuit receives a clock signal that synchronously clocks each dynamic flip-flop. The feedback circuit supplies a feedback signal onto the first dynamic-flop of the chain. In a first mode, a signal from a slave stage of the first flip-flop and a signal from a slave stage of the second flip-flop are used by the feedback circuit to generate the feedback signal. In a second mode, a signal from a master stage of the first flip-flop and a signal from a master stage of the second flip-flop are used by the feedback circuit to generate the feedback signal. By proper selection of the mode, the frequency range of the overall divider is extended. Combinatorial logic converts thirty-three percent duty cycle signals from the flip-flop chain into fifty percent duty cycle quadrature signals. | 08-18-2011 |
Patent application number | Description | Published |
20130316668 | LOW NOISE AMPLIFIERS WITH TRANSFORMER-BASED SIGNAL SPLITTING FOR CARRIER AGGREGATION - Low noise amplifiers (LNAs) supporting carrier aggregation are disclosed. In an exemplary design, an apparatus (e.g., a wireless device, an integrated circuit, etc.) includes an amplifier circuit, a transformer, and a plurality of downconverters. The amplifier circuit receives and amplifies an input radio frequency (RF) signal and provides an amplified RF signal. The input RF signal includes transmissions sent on multiple carriers at different frequencies to a wireless device. The transformer includes a primary coil coupled to the amplifier circuit and a plurality of secondary coils providing a plurality of output RF signals. The plurality of downconverters downconvert the plurality of output RF signals with a plurality of local oscillator (LO) signals at different frequencies. Each downconverter includes a pair of mixers that receives one output RF signal and one LO signal and provides inphase and quadrature downconverted signals for one set of carriers being received. | 11-28-2013 |
20130316669 | LOW NOISE AMPLIFIERS WITH CASCODE DIVERT SWITCH FOR CARRIER AGGREGATION - Low noise amplifiers (LNAs) supporting carrier aggregation are disclosed. In an exemplary design, an apparatus (e.g., a wireless device, an integrated circuit, etc.) includes first and second amplifier circuits and a divert cascode transistor. Each amplifier circuit may include a gain transistor and a cascode transistor. The divert cascode transistor is coupled between the output of the first amplifier circuit and the gain transistor in the second amplifier circuit. The first and second amplifier circuits receive an input radio frequency (RF) signal including transmissions sent on multiple carriers at different frequencies to a wireless device. The first and second amplifier circuits and the divert cascode transistor are controlled to amplify the input RF signal and provide (i) one amplified RF signal for one set of carriers in a first operating mode or (ii) two amplified RF signals for two sets of carriers in a second operating mode. | 11-28-2013 |
20130316670 | MULTIPLE-INPUT MULTIPLE-OUTPUT (MIMO) LOW NOISE AMPLIFIERS FOR CARRIER AGGREGATION - Multiple-input multiple-output (MIMO) low noise amplifiers (LNAs) supporting carrier aggregation are disclosed. In an exemplary design, an apparatus (e.g., a wireless device, an integrated circuit, etc.) includes a MIMO LNA having a plurality of gain circuits, a drive circuit, and a plurality of load circuits. The gain circuits receive at least one input radio frequency (RF) signal and provide at least one amplified RF signal. Each gain circuit receives and amplifies one input RF signal and provides one amplified RF signal when the gain circuit is enabled. The at least one input RF signal include transmissions sent on multiple carriers at different frequencies to the wireless device. The drive circuit receives the at least one amplified RF signal and provides at least one drive RF signal. The load circuits receive the at least one drive RF signal and provide at least one output RF signal. | 11-28-2013 |
20140134959 | EXPANDABLE TRANSCEIVERS AND RECEIVERS - Expandable transceivers and receivers supporting operation on multiple frequency bands and multiple carriers are disclosed. In an exemplary design, an apparatus (e.g., a wireless device, an integrated circuit (IC) chip, or circuit module) includes a low noise amplifier (LNA) and interface circuit. The LNA resides on an IC chip and includes a first/on-chip output and a second/off-chip output. The interface circuit also resides on the IC chip, is coupled to the second output of the LNA, and provides an amplified RF signal outside of the IC chip. The apparatus may further include a buffer, load circuit, and downconverter circuit. The buffer resides on the IC chip, is coupled to the first output of the LNA, and receives a second amplified RF signal from outside of the IC chip. The load circuit is coupled to the first output of the LNA. The downconverter circuit is coupled to the load circuit. | 05-15-2014 |
20140134960 | OMNI-BAND AMPLIFIERS - Omni-band amplifiers supporting multiple band groups are disclosed. In an exemplary design, an apparatus (e.g., a wireless device, an integrated circuit, etc.) includes at least one gain transistor and a plurality of cascode transistors for a plurality of band groups. Each band group covers a plurality of bands. The gain transistor(s) receive an input radio frequency (RF) signal. The cascode transistors are coupled to the gain transistor(s) and provide an output RF signal for one of the plurality of band groups. In an exemplary design, the gain transistor(s) include a plurality of gain transistors for the plurality of band groups. One gain transistor and one cascode transistor are enabled to amplify the input RF signal and provide the output RF signal for the selected band group. The gain transistors may be coupled to different taps of a single source degeneration inductor or to different source degeneration inductors. | 05-15-2014 |
20140213209 | SINGLE-INPUT MULTIPLE-OUTPUT AMPLIFIERS WITH INDEPENDENT GAIN CONTROL PER OUTPUT - Amplifiers with multiple outputs and separate gain control per output are disclosed. In an exemplary design, an apparatus (e.g., a wireless device or an integrated circuit) may include first and second amplifier circuits. The first amplifier circuit may receive and amplify an input radio frequency (RF) signal based on a first variable gain and provide a first amplified RF signal. The second amplifier circuit may receive and amplify the input RF signal based on a second variable gain and provide a second amplified RF signal. The input RF signal may include a plurality of transmitted signals being received by the wireless device. The first variable gain may be adjustable independently of the second variable gain. Each variable gain may be set based on the received power level of at least one transmitted signal being received by the wireless device. | 07-31-2014 |