| Patent application number | Description | Published |
|---|
| 20120219777 | Ultrathin Laminates - Ultrathin copper clad laminates including a fabric sheet material layer having a first planar surface, a second planar surface and an original thickness of from about 10 to about 30 microns and at least one copper foil sheet that is adhered to a planar surface of the fabric sheet material by a cured resin wherein the base laminate has a thickness of from about 1.0 to about 1.75 mils. | 08-30-2012 |
| 20140011962 | Synthesized Resins and Varnishes and Prepegs and Laminates Made Therefrom - Synthesized base resin compositions that include a raw resin and a maleimide and/or bismaleimide monomer as well as compounded varnishes that include a raw resin or synthesized base resin as well as a monomer, flame retardant and initiator as well as prepregs and laminates made using the synthesized base resin and compounded varnishes. | 01-09-2014 |
| 20140024278 | Synthesized Resins and Varnishes and Prepegs and Laminates Made Therefrom - Synthesized base resin compositions that include a raw resin and a maleimide and/or bismaleimide monomer as well as compounded varnishes that include a raw resin or synthesized base resin as well as a monomer, flame retardant and initiator as well as prepregs and laminates made using the synthesized base resin and compounded varnishes. | 01-23-2014 |
| 20140220844 | Prepregs and Laminates Having Homogeneous Dielectric Properties - Resin compositions including one or more base resins and one or more high dielectric constant materials wherein the one or more high dielectric constant materials are present in the resin composition in an amount sufficient to impart the resin composition with a cured Dk that matches the Dk of the reinforcing material to which the resin composition is to be applied to within plus or minus (±) 15% as well as prepregs and laminates made using the resin compositions. | 08-07-2014 |
| 20140231007 | Ultrathin Laminates - Ultrathin copper clad laminates including a fabric sheet material layer having a first planar surface, a second planar surface and an original thickness of from about 10 to about 30 microns and at least one copper foil sheet that is adhered to a planar surface of the fabric sheet material by a cured resin wherein the base laminate has a thickness of from about 1.0 to about 1.75 mils. | 08-21-2014 |
| 20150030822 | Prepregs and Laminates Having Homogeneous Dielectric Properties - Prepregs and laminates made from resin compositions having a free resin portion and a resin impregnated reinforcing material portion where the resin includes one or more base resins and one or more high Dk materials wherein the one or more high Dk materials are present in the resin composition in an amount sufficient to impart the resin composition with a cured Dk | 01-29-2015 |
| 20150105505 | Varnishes and Prepregs and Laminates Made Therefrom - Varnishes useful in manufacturing prepregs and laminates including at least one polymer selected from the group consisting of polyphenylene ether, polyphenylene oxide and combinations thereof; at least on reactive monomer; and at least one initiator. | 04-16-2015 |
| 20160075839 | High Tg Epoxy Formulation with Good Thermal Properties - Varnish compositions and prepregs and laminates made therefrom wherein the varnish compositions include at least one first epoxy resin and at least one second epoxy resin that includes a bisphenol-A novolac epoxy resin and a harder wherein the at least one first epoxy resin and the at least one second bisphenol-A novolac epoxy resin are present in the varnish at a weight ratio ranging from about 1:1 to about 1:3. | 03-17-2016 |
| Patent application number | Description | Published |
|---|
| 20110153288 | METHOD AND SYSTEM FOR OPTIMALLY CONNECTING INTERFACES ACROSS MUTIPLE FABRICS - A method of connecting an interface to a fabric of an electronic device, the interface having a plurality of nets to be connected to corresponding connectors in the fabric includes associating with each of the connectors in the fabric a first variable indicating that the connector belongs to the interface; associating with each of the connectors in the fabric a second variable indicating a number of higher numbered adjacent connectors for the connector in the interface; connecting each of the nets in the interface to a corresponding one of the connectors in the fabric such that the second variable has a non-zero value at exactly one of the corresponding connectors in the interface. | 06-23-2011 |
| 20110153289 | METHOD AND SYSTEM FOR SPECIFYING SYSTEM LEVEL CONSTRAINTS IN A CROSS-FABRIC DESIGN ENVIRONMENT - A method of specifying system level constraints for connecting an interface of an electronic device between first and second fabrics includes specifying one or more first condition relating to a placement of the interface, specifying one or more second condition relating to a connection of a net in the interface between the first and second fabrics, generating one or more first equation expressing the first condition as a function of the location of the connectors, generating one or more second equation expressing the second condition as a function of the location of connectors, generating one or more third equation expressing an optimality criterion for the interface, and outputting the one or more first equation, the one or more second equation and the one or more third equation to a data file in a computer readable format. | 06-23-2011 |
| 20110154276 | METHOD AND SYSTEM FOR OPTIMALLY PLACING AND ASSIGNING INTERFACES IN A CROSS-FABRIC DESIGN ENVIRONMENT - A system for connecting an interface of an electronic device between first and second fabrics includes a constraint generator that associates first and second conditions with the interface, a first equation solver that solves one or more first equation to select a first plurality of connectors in the first fabric and a second plurality of connectors in the second fabric that satisfy the first condition based on an optimality criterion for the interface; and a second equation solver that solves one or more second equation to select one of the first plurality of connectors in the fabric and one of the second plurality of connectors in the second fabric that satisfy the second condition based on the optimality criterion for the interface. | 06-23-2011 |
| 20110173582 | METHOD AND APPARATUS FOR RULE-BASED AUTOMATIC LAYOUT PARASITIC EXTRACTION IN A MULTI-TECHNOLOGY ENVIRONMENT - A system for extracting a layout from an object in a fabric includes means for providing fabric data to a rule-based layout extraction engine; means for maintaining a layout extraction rule to select a layout object from the fabric data; means for maintaining a binding rule to bind the layout object to a solver; means for maintaining a boundary rule to specify a boundary condition for a solver; and means for executing the solver on the layout object to generate a model of the object. | 07-14-2011 |
| Patent application number | Description | Published |
|---|
| 20120059971 | METHOD AND APPARATUS FOR HANDLING CRITICAL BLOCKING OF STORE-TO-LOAD FORWARDING - The present invention provides a method and apparatus for handling critical blocking of store-to-load forwarding. One embodiment of the method includes recording a load that matches an address of a store in a store queue before the store has valid data. The load is blocked because the store does not have valid data. The method also includes replaying the load in response to the store receiving valid data so that the valid data is forwarded from the store queue to the load. | 03-08-2012 |
| 20120096226 | TWO LEVEL REPLACEMENT SCHEME OPTIMIZES FOR PERFORMANCE, POWER, AND AREA - A two-level replacement scheme is provided for selecting an entry in a cache memory to replace when a cache miss takes place and the memory is full. The scheme divides the tags associated with each memory location of the cache into two or more groups, each group relating to a subset of memory locations of the cache. The scheme uses a first algorithm to select one of the groups and passes the tags for the group through a second algorithm. The second algorithm produces a local index which, when combined with a group index, produces a replacement index that identifies a memory location in the cache to replace. | 04-19-2012 |
| 20130311724 | CACHE SYSTEM WITH BIASED CACHE LINE REPLACEMENT POLICY AND METHOD THEREFOR - A cache system includes plurality of first caches at a first level of a cache hierarchy and a second cache at a second level of the cache hierarchy which is lower than the first level of cache hierarchy coupled to each of the plurality of first caches. The second cache enforces a cache line replacement policy in which the second cache selects a cache line for replacement based in part on whether the cache line is present in any of the plurality of first caches and in part on another factor. | 11-21-2013 |
| 20130346694 | PROBE FILTER FOR SHARED CACHES - The claimed subject matter provides a method and apparatus for filtering probes to shared caches. One embodiment of the method includes filtering a probe of one or more of a plurality of first caches based on a plurality of first bits associated with a line indicated by the probe. Each of the plurality of first bits is associated with a different subset of the plurality of first caches and each first bit indicates whether the line is resident in a corresponding subset of the plurality of first caches. A second bit indicates whether the line is resident in more than one of the plurality of first caches in at least one of the subsets of the plurality of first caches. | 12-26-2013 |
| 20140129776 | STORE REPLAY POLICY - A method is provided for executing a cacheable store. The method includes determining whether to replay a store instruction to re-acquire one or more cache lines based upon a state of the cache line(s) and an execution phase of the store instruction. The store instruction is replayed in response to determining to replay the store instruction. An apparatus is provided that includes a store queue (SQ) configurable to determine whether to replay a store instruction to re-acquire one or more cache lines based upon a state of the cache line(s) and an execution phase of the store instruction. Computer readable storage devices for adapting a fabrication facility to manufacture the apparatus are provided. | 05-08-2014 |
| 20140189245 | MERGING EVICTION AND FILL BUFFERS FOR CACHE LINE TRANSACTIONS - A processor includes a first cache memory and a bus unit in some embodiments. The bus unit includes a plurality of buffers and is operable to allocate a selected buffer of a plurality of buffers for a fill request associated with a first cache line to be stored in a first cache memory, load fill data from the first cache line into the selected buffer, and transfer the fill data to the first cache memory in parallel with storing eviction data for an evicted cache line from the first cache memory in the selected buffer. | 07-03-2014 |
| 20140310506 | ALLOCATING STORE QUEUE ENTRIES TO STORE INSTRUCTIONS FOR EARLY STORE-TO-LOAD FORWARDING - The present invention provides a method and apparatus for allocating store queue entries to store instructions for early store-to-load forwarding. Some embodiments of the method include allocating an entry in a store queue to a store instruction in response to the store instruction being dispatched and prior to receiving a translation of a virtual address to a physical address associated with the store instruction. The entry includes storage for data to be written to the physical address by the store instruction. | 10-16-2014 |
| 20140317356 | MERGING DEMAND LOAD REQUESTS WITH PREFETCH LOAD REQUESTS - A processor includes a processing unit, a cache memory, and a central request queue. The central request queue is operable to receive a prefetch load request for a cache line to be loaded into the cache memory, receive a demand load request for the cache line from the processing unit, merge the prefetch load request and the demand load request to generate a promoted load request specifying the processing unit as a requestor, receive the cache line associated with the promoted load request, and forward the cache line to the processing unit. | 10-23-2014 |
| 20140317357 | PROMOTING TRANSACTIONS HITTING CRITICAL BEAT OF CACHE LINE LOAD REQUESTS - A processor includes a cache memory, a first core including an instruction execution unit, and a memory bus coupling the cache memory to the first core. The memory bus is operable to receive a first portion of a cache line of data for the cache memory, the first core is operable to identify a plurality of data requests targeting the cache line and the first portion and select one of the identified plurality of data requests for execution, and the memory bus is operable to forward the first portion to the instruction execution unit and to the cache memory in parallel. | 10-23-2014 |
| 20150186280 | CACHE REPLACEMENT POLICY METHODS AND SYSTEMS - An embodiment includes a system, comprising: a cache configured to store a plurality of cache lines, each cache line associated with a priority state from among N priority states; and a controller coupled to the cache and configured to: search the cache lines for a cache line with a lowest priority state of the priority states to use as a victim cache line; if the cache line with the lowest priority state is not found, reduce the priority state of at least one of the cache lines; and select a random cache line of the cache lines as the victim cache line if, after performing each of the searching of the cache lines and the reducing of the priority state of at least one cache line K times, the cache line with the lowest priority state is not found. N is an integer greater than or equal to 3; and K is an integer greater than or equal to 1 and less than or equal to N−2. | 07-02-2015 |
| 20150331608 | ELECTRONIC SYSTEM WITH TRANSACTIONS AND METHOD OF OPERATION THEREOF - An electronic system includes: a storage unit configured to store a data array; a control unit configured to: determine availability of the data array; reorder access to the data array; and provide access to the data array. | 11-19-2015 |
| Patent application number | Description | Published |
|---|
| 20090265490 | High-Speed Video Serializer and Deserializer - A high-speed video serializer has an X bit parallel input bus and a Y bit parallel output bus, where X and Y are multiples of one another (e.g., 2). A multiplexer is connected between the input bus and the output bus and is operated such that a frequency of the signals on the output bus is a multiple of the frequency of the signals on the input bus. A circuit provides a clock signal substantially in sync with the signals on the output bus. A high speed video deserializer is also disclosed as are methods of operating the serializer and deserializer. | 10-22-2009 |
| 20090303381 | Video Serializer and Deserializer with Mapping Conversion - A method for converting data received in either a Level A or Level B SMPTE 425M compliant format into either a Level B or a Level A compliant format, respectively, includes receiving and processing data in one of a Level A or a Level B SMPTE 425M compliant format. Inputting the received Level A formatted data into a storage device and reading out Level B formatted data at an output of the storage device, or inputting Level B formatted data into the storage device and reading out Level A formatted data at an output of the storage device. Back-end circuitry further processes the Level A formatted data when Level B formatted data is received or further processes the Level B formatted data when Level A formatted data is received. The storage device is operated as a line multiplexer to convert data in a Level B format to data in a Level A format and is operated as a line demultiplexer to convert data in a Level A format to data in a Level B format. Receivers and transmitters capable of performing the method are also disclosed. | 12-10-2009 |
| 20130208812 | HIGH-SPEED INTERFACE FOR ANCILLARY DATA FOR SERIAL DIGITAL INTERFACE APPLICATIONS - A high speed interface for ancillary data is provided. The interface extracts ancillary data encoded in a serial digital data signal received over the serial digital data input; assembles a plurality of data packets, each packet comprising identification information identifying the data packet, length information identifying a length of the data packet, and value information representing a portion of the extracted ancillary data; sequentially encodes the plurality of data packets within a high-speed data stream; and transmits the high speed data stream via a high speed data output. | 08-15-2013 |
