Patent application number | Description | Published |
20120156918 | CONNECTOR ASSEMBLY - A connector assembly includes a first connector with a positioning portion and a second connector with a latch. A blocking portion is located on a second side of the first connector. The latch defines an oblique latching plane, the positioning portion defines an oblique sliding plane, and the blocking portion defines an oblique blocking plane. If the latch is aligned with the positioning portion and is slid towards the first connector, the oblique direction of the second latching plane is substantially the same as the oblique positioning plane. If the latch is aligned with the blocking portion and is slid towards the first connector, an acute angle is defined between the oblique direction of the second latching plane and the oblique direction of the blocking plane. | 06-21-2012 |
20120188709 | ELECTRONIC DEVICE WITH HEAT DISSIPATION STRUCTURE - An electronic device includes a computer, a circuit board, a supporting base attached to a top surface of the circuit board, and a backboard attached to a bottom surface of the circuit board. The case includes a bottom plate. The circuit board defines a through hole. A CPU is located on the supporting base. The backboard defines a retaining hole. The supporting base defines a fixing hole. A heat sink is attached to the supporting base and contacted the CPU. A fixing member is engaged with the retaining hole, the fixing hole and the through hole, to engage the backboard and the supporting base to the circuit board. | 07-26-2012 |
20120212915 | EXPANSION CARD MOUNTING APPARATUS - An expansion card mounting apparatus including an enclosure, the enclosure including a support plate and a flange, the enclosure defining a slot, the support plate and the flange located above the slot; a mounting plate, the mounting plate including a mounting plate body and a bent portion extending from the mounting plate body; the mounting plate body securing an expansion card and covering the slot; the bent portion located on the support plate; a securing element, the securing element pressing the bent portion; and a pressing member, the pressing member including a resilient arm and a securing portion extending from the resilient arm; the resilient arm including a first and a second ends, the first end resisting the expansion card; the second end resisting on the securing element; and the securing portion engaging with the flange to enable the pressing member sandwiched between the securing element and the flange. | 08-23-2012 |
20130004303 | FAN ASSEMBLY - A fan assembly includes a case, a bracket and a fan module. The cage includes a ventilation plate. An installation portion and a positioning post are located on the ventilation plate. The fan module is secured to the ventilation plate and includes a bracket and a fan secured to the bracket. The bracket includes a body, a first sidewall, and a second sidewall. The first and second sidewalls are located on opposite sides of the body. The first sidewall defines a first receiving slot and a first positioning hole. The second sidewall defines a second receiving slot and a second positioning hole. The first positioning hole is aligned with the second positioning hole. An area of the first receiving slot is larger than that of the second receiving slot. The positioning post is engaged in the positioning hole. The installation portion is received in the first receiving slot. | 01-03-2013 |
20130044439 | MOUNTING APPARATUS FOR BLUETOOTH COMPONENT - A mounting apparatus includes an enclosure and a securing member. The enclosure includes a plate. The securing member is secured to an outer surface of the plate. The securing member includes a base board and a locking portion located on the base board. The locking portion is configured to secure a bluetooth component to the base board. The locking portion is located between the base board and the outer surface of the plate. | 02-21-2013 |
20130044453 | MOUNTING APPARATUS FOR POWER SUPPLY - An assembly comprises a chassis and a power supply installed on the chassis. The chassis comprises a bottom panel and a rear panel located on the bottom panel. A supporting plate is located on the bottom panel. The rear panel defines a through hole. A limiting piece and a positioning piece are located on the rear panel. The power supply is placed on the supporting plate. The power supply comprises a rear wall and two sidewalls located on two opposite sides of the rear wall. The rear wall defines an installation hole. A first distance between the limiting piece and the positioning piece is substantially equal to a second distance between the two sidewalls. The installation hole is aligned with the through hole when the power supply is located between the limiting piece and the positioning piece. | 02-21-2013 |
20130142644 | FAN ASSEMBLY - A fan assembly includes a bracket and a fan module. The bracket includes a ventilation plate. A limiting portion protrudes from the ventilation plate. The fan module is secured to the ventilation plate and includes a frame and a plurality of fan blades. The frame includes a first sidewall and a second sidewall opposite to the first sidewall. The plurality of fan blades are received in the frame, and each of the plurality of fan blades includes a first edge adjacent to the first sidewall and a second edge adjacent to the second sidewall. A height of the limiting portion is greater than a distance between the first edge and the first sidewall and smaller than a distance between the second edge and the second sidewall. | 06-06-2013 |
Patent application number | Description | Published |
20100314436 | FOLDABLE PACKING BOX - A foldable packing box of the present invention comprises a base board, a pair of side boards, and a pair of fixing boards. The base board includes a first end board, a bottom board connected to the first end board, and a second end board connected to the bottom board opposite to the first end board. The pair of side boards are respectively fixed to the opposite two sides of the bottom board. The fixing boards are respectively fixed to the sides of the first end board and the second end board apart from the bottom board. The base board, the side boards, and the fixing boards are foldable to locate at a same plane. While assembling the packing box, the side boards are fixed to the base board by the fixing boards. The foldable packing box of the present invention can locate in a plane to save the occupied space thereof during storage and transportation, so as to facilitate to reduce the storage and transportation cost. Furthermore, the foldable packing box of the present invention separately makes the base board, side boards, and fixing boards for make full use of the material thereby reducing the production cost. | 12-16-2010 |
20100320262 | Demountable Packing Box - A demountable packing box of the present invention comprises a main body, an upper cover located at the upper portion of the main body, a lower cover located at the lower portion of the main body, and a plurality of connecting bands respectively connected to the upper cover and the lower cover. The main body is a flat plate with two connecting portions at opposite sides thereof after disassembled. A pair of fixing parts matable with each other is respectively disposed at the two connecting portions of the main body. The upper cover is a flat plate with a predetermined shape. A plurality of upper tabs respectively extends outwards from the periphery of the upper over. The lower cover is a flat plate with a shape corresponding to the upper cover. A plurality of lower tabs extends outwards from the periphery of the lower cover. The upper portion of the main body is provided with a plurality of upper positioning parts corresponding to the upper tabs of the upper cover. The lower portion of the main body is provided with a plurality of lower positioning parts corresponding to the lower tabs of the lower cover. | 12-23-2010 |
20100320741 | Notebook - A notebook of the present invention comprises a main body, and a cover. The main body includes a plurality of pages with four corners thereof being round. The cover covers the main body with round corners corresponding to the four round corners of the main body. The width of the notebook from left to right is larger than the length of the notebook from up to down. The notebook of the present invention can protect the corners thereof from curling, deforming, or damaging during contact with other objects. Not only the notebook is kept a clean appearance, but also the service life of the notebook can be increased at a certain extent The notebook is convenient to use through flipping upwards and making the proportion between the width and the length greater than 1. | 12-23-2010 |
20100323175 | Paper Board and Making Method Thereof - The present invention relates to a paper board and making method thereof. The paper board comprises a kraft paper, a glue layer located on the kraft paper, and an aluminium plating film located on the glue layer. The method of making a paper board comprises: step 1, providing a kraft paper; step 2, providing an aluminium plating film; step 3, compounding the aluminium plating film to the kraft paper via glue. In step 3, the aluminium plating film is closely attached to the kraft paper with glue through pressing, so as to form a composite paper board. The method of making the paper board of the present invention is simple and reduces the cost. The paper board has a reliable quality, a long endurance, a beautiful appearance, and a low cost. | 12-23-2010 |
20100323867 | Method of Making Paper Packing Box - A method of making a paper packing box of the present invention comprises the following steps: step | 12-23-2010 |
Patent application number | Description | Published |
20110317004 | IV Monitoring by Digital Image Processing - We describe an apparatus using an image capturing device to obtain image of the IV container, and uses digital image processing technique to analyze information in the image. We also describe the use of barcode which can read by the apparatus so that relevant information of the drug, container, and the patient can be made use of. | 12-29-2011 |
20120013735 | IV monitoring by video and image processing - We describe a method and apparatus for monitoring the dripping speed in IV process, as well as detecting the its end. The apparatus includes a camera and a processing unit to analyze the information from the acquired video. Features from the image sequence are extracted and the dripping speed is computed accordingly by discrete Fourier transform. The apparatus is also capable of detecting the end of the dripping process by finding the location of liquid surface in the drip chamber. We also describe the use of barcode to provide information to the monitoring device and program. | 01-19-2012 |
20120197185 | Electromechanical system for IV control - We describe electromechanical systems for IV control. Based on dripping speed measurement by video processing technique, we adjust the position of the presser to press the dripping tube to the appropriate position to control the dripping speed. To do this mechanically, the processing unit issues commands to a stepper motor to control its rotation, and either a leadscrew or its variants, or a cam, is used to translate motor's rotation into presser's linear motion. When the processing unit detects that the dripping is finished, the device will also cut the dripping off immediately with the presser. | 08-02-2012 |
20140327759 | Image Processing, Frequency Estimation, Mechanical Control and Illumination for an Automatic IV Monitoring and Controlling system - This invention covers all aspects of an automatic IV monitoring and controlling system. It expands and completes the inventor's three earlier applications: U.S. application Ser. Nos. 12/825,368, 12/804,163 and 13/019,698. The monitoring is done by video/image processing. We give details on enhancing and processing the image. Frequency estimation can be done by a variety of techniques and we covered each class by giving at least one example. Then we discussed the mechanical system for speed control in detail covering topics such as actuator, motion guide and tube presser/supporter. In the last we discussed ways of illumination so that clear image can be obtained. A variety of techniques are given but most can be subsumed into the two principles discussed in §4.2. | 11-06-2014 |
20140340512 | Designs of an Automatic IV Monitoring and Controlling System - When analyzing video frames captured for monitoring the IV dripping process, dew droplets could exist in the image. We discussed image processing methods to remove the dew droplets from the background, including computing the difference between frames and averaging to get a proper background image. We also discussed various methods to keep the temperature of some areas of the inner surface of the drip chamber to be above the dew points in order to prevent dew droplets' formation or to remove them. In the end we showed how video of the dripping process could be shown on external display(s) for devices enclosing the drip chamber inside. | 11-20-2014 |
Patent application number | Description | Published |
20130296549 | PURIFICATION METHOD OF AZTREONAM - It discloses a process for refining Aztreonam, comprising the steps of 1) treating Aztreonam material with an alkali metal alkoxylate or an alkali earth metal alkoxylate under heating in the presence of a suitable solvent or a mixture of solvents, followed by adjusting the pH value with a suitable acid and cooling down to precipitate Aztreonam, which provides a primary purified Aztreonam; 2) adsorbing Aztreonam with strongly basic ion exchange resin, followed by eluting the resin and collecting the eluate, to provide a secondary purified Aztreonam after concentration under reduced pressure; 3) adjusting the pH value with a suitable acid to allow crystallization, followed by centrifuging and washing the resultant crystals, to provide a tertiary purified Aztreonam after drying. The refined Aztreonam product has a purity of no less than 99.2%, mostly no less than 99.5%, with little residue on ignition and significantly low content of heavy metals. | 11-07-2013 |
20130303754 | REFINING PROCESS OF CEFAMANDOLE SODIUM - It discloses a novel process for refining cefamandole nafate, comprising: 1) adsorbing cefamandole nafate with strongly acidic ion exchange resin, followed by eluting the resin and collecting the eluate, to provide a primary purified cefamandole acid after concentration under reduced pressure; 2) neutralizing the primary purified cefamandole acid with an aqueous solution of sodium hydroxide or an aqueous solution of basic salt of sodium, followed by adjusting the pH value and filtrating out the insoluble substances with heating, thereby providing a secondary purified aqueous solution of cefamandole nafate; and 3) adding ethanol in a volume ratio between ethanol and water of 4:6 into the aqueous solution, to allow recrystallization under controlling the temperature, to provide a tertiary purified cefamandole nafate. The refined cefamandole nafate product has a purity of no less than 99.5%, mostly no less than 99.6%, with significantly low content of heavy metals. | 11-14-2013 |
Patent application number | Description | Published |
20140005381 | NOVEL PROCESS FOR REFINING CEFMETAZOLE SODIUM | 01-02-2014 |
20140011994 | NOVEL PROCESS FOR PURIFYING CEFOTIAM HYDROCHLORIDE - A method for treating cefotiam hydrochloride, comprises the following steps: step 1), dissolving the raw material cefotiam hydrochloride in water, treating it with an acidic salt, then cooling it, and filtering the precipitate to obtain an aqueous filtrate; step 2), adding a water-immiscible solvent to the above aqueous solution for extraction, and then separating the organic phase containing impurities to obtain an aqueous solution containing cefotiam hydrochloride; step 3) adding to the aqueous solution a poor solvent of cefotiam hydrochloride and controlling the temperature for recrystallization, washing the educed crystals by centrifugation, and drying them to obtain purified cefotiam hydrochloride. The cefotiam content of the refined cefotiam hydrochloride obtained by the method of the present invention is not less than 86%, the content of polymeric impurities is less than 0.3%, and the content of insoluble microparticles in the injection prepared therefrom is quite low. | 01-09-2014 |
20140121369 | METHOD FOR PURIFYING CEFTIZOXIME SODIUM - A novel process for refining Ceftizoxime sodium compound, comprises the steps of: 1) dissolving crude Ceftizoxime sodium in water, and extracting with cyclohexane or ethyl acetate, followed by separating the organic phase containing impurities, producing an aqueous phase containing Ceftizoxime sodium; 2) adding ammonia or ammonium hydroxide into the above aqueous phase while stirring, followed by filtrating the precipitate, producing an aqueous filtrate containing Ceftizoxime sodium; 3) adding an alcoholic solvent in the aqueous solution and recrystallizing under controlled temperature, followed by centrifuging and washing the resultant crystals, producing the refined Ceftizoxime sodium after drying; and 4) optionally returning the mother liquid of the recrystallization process to step 3). | 05-01-2014 |
20140121370 | NOVEL METHOD FOR PREPARING CEFMENOXIME HYDROCHLORIDE COMPOUND - A novel process for purifying Cefmenoxime hydrochloride comprises: 1) adding a solvent wherein Cefmenoxime hydrochloride is insoluble at the temperature less than 30° C. filtering after vigorous stirring, washing the filter cake with a solvent wherein Cefmenoxime hydrochloride is insoluble at a temperature less 20° C., and drying; 2) placing the filter cake into ammonium hydroxide, controlling the pH value less than 9 with a gentle agitation to obtain Cefmenoxime acid solution in ammonium hydroxide, and then filtering out the precipitate; 3) adding hydrochloric acid at a concentration of 0.5-4 mol/L to Cefmenoxime acid solution in ammonium hydroxide slowly and controlling the temperature between 30-60° C. and the final pH between 0.5-3.0, and then cooling down to a minimum of 10° C. and standing still to allow crystallization, filtrating and vacuum drying. | 05-01-2014 |
20140275550 | LANSOPRAZOLE COMPOUND AND NOVEL PREPARATION METHOD THEREOF - A process for purifying lansoprazole comprises 1) loading crude lansoprazole material onto a macroporous resin column; 2) concentrating the eluate from the column in a crystallization vessel by vacuum; 3) seeding lansoprazole crystal; 4) crystallizing the lansoprazole; 5) separating the precipitated crystals. The process especially has large processing capacity, can be carried out continuously and therefore suitable for industrial production, improving the quality of formulated products and reducing side effects. | 09-18-2014 |
20150038740 | ALANYL GLUTAMINE COMPOUND AND PREPARATION METHOD THEREOF - A process for preparing a pure alanylglutamine comprises the steps of: 1) reacting N-(α-chloro)-propionyl-glutamine and hydrazine compound to obtain an alanylglutamine crude product; 2) mixing anhydrous methanol and the alanylglutamine crude product to provide a filter cake; 3) dissolving the filter cake in water, heating, adding ethanol, and cooling to yield the pure alanylglutamine. | 02-05-2015 |
Patent application number | Description | Published |
20140188722 | SELF-TRANSACTION AUTOMATIC OPTIMIZATION SERVICE CONTROL SYSTEM - A self-service transaction automatic optimization service control system is provided, which includes a time-slicing service mode generating module, a service interrupting signal generating module and a self-service terminal control module. Wherein, the time-slicing service mode generating module is configured to detect the current user queue of the self-service terminal and identify whether the user queue is in a long queue state, convert the self-service terminal from a general service mode to a time-slicing service mode if the user queue is in a long queue state, otherwise maintain the self-service terminal maintain in the general service mode, wherein the time-slicing service mode provides business service of specific time or specific number of times to the user currently in operation of the self-service terminal. | 07-03-2014 |
20140214672 | SELF-SERVICE TRANSACTION AND AUTOMATIC EMERGENCY HEDGE SYSTEM - A self-service transaction and automatic emergency hedge system, including an emergency signal generation module ( | 07-31-2014 |
20140327206 | ACCUMULATION DEVICE FOR PAPER-LIKE SHEETS - An accumulation device for paper-like sheets comprises a conveying part, a clamping part, a guiding part and an accumulating part, which are connected serially. The conveying part is used for conveying the paper-like sheet to the clamping part. The clamping part comprises a drive shaft and multiple banknote-stacking wheels fixed to the drive shaft, and every banknote-stacking wheel is provided with multiple wheel blades having the same curvature. The paper-like sheet can be clamped between any two adjacent wheel blades and rotatably conveyed to the guiding part. The guiding part receives the paper-like sheet conveyed by the clamping part and guides the paper-like sheet to the accumulating part. The accumulating part is used for accumulating the paper-like sheet conveyed by the guide part. The paper-like sheets are reliably collected among the wheel blades and prevented from scattering, and thus the paper-like sheets can be uniformly arranged in order and stacked on the accumulating part. | 11-06-2014 |
Patent application number | Description | Published |
20130069155 | Termination for Superjunction VDMOSFET - A termination for silicon superjunction VDMOSFET comprises heavily doped N-type silicon substrate which also works as drain region; drain metal is disposed on the back surface of the heavily doped N-type silicon substrate; an N-type silicon epitaxial layer is disposed on the heavily doped N-type silicon substrate; P-type silicon columns and N-type silicon columns are formed in the N-type silicon epitaxial layer, alternately arranged; a continuous silicon oxide layer is disposed on a part of silicon surface in the termination; structures that block the drift of mobile ions (several discontinuous silicon oxide layers arranged at intervals) are disposed on the other part of silicon surface in the termination. The structures that block the drift of mobile ions disposed in the termination region are able to effectively prevent movement of the mobile ions and improve the capability of the power device against the contamination induced by the mobile ions. | 03-21-2013 |
20140292380 | SEMICONDUCTOR DEVICE WITH A CURRENT SAMPLER AND A START-UP STRUCTURE - A semiconductor device with a current sampler and a start-up structure, comprises first, second and third high-voltage transistors, and a resistor, wherein: a drain terminal of the first transistor is respectively connected to a drain terminal of the second transistor, a drain terminal of the third transistor and one end of the resistor; a source terminal of the first transistor is grounded, and a gate terminal of the first transistor is connected to a gate terminal of the second transistor; the other end of the resistor is connected to a gate terminal of the third transistor; wherein the resistor is wound and formed in a common voltage withstand region of the first transistor, the second transistor and the third transistor, or in a voltage withstand region of the first transistor only, or in the voltage withstand region of the third transistor only. | 10-02-2014 |
20140362488 | SHORT-CIRCUIT PROTECTION STRUCTURE - A short-circuit protection structure comprises first and second high-voltage transistors, a control circuit, a first current sampling resistor for the first transistor and a second current sampling resistor for the second transistor. The control circuit controls switching period and duty cycle of the first transistor and the second transistor, a drain terminal of the first transistor is connected to a drain terminal of the second transistor, a source terminal of the first transistor is connected to the first current sampling resistor, and a source terminal of the second transistor is connected to the second current sampling resistor; a gate terminal of the first transistor and a gate terminal of the second transistor are connected to a driver stage of the control circuit. The size of the second transistor is smaller than the first transistor, and the current of the first transistor is sampled by the second transistor. | 12-11-2014 |
Patent application number | Description | Published |
20130114704 | Utilizing A Search Scheme for Screen Content Video Coding - A method, a device and computer readable storage media facilitate providing screen content including a plurality of video frames that are displayed by a computing device. During coding of the screen content, a suitable predictor is found that is used to code pixel blocks from one or more frames. The suitable predictor is found by selecting a pixel block of a current frame, conducting a direction based search by comparing pixel blocks within a search window of a reference frame with the selected pixel block of the current frame to determine whether a match exists, and, in response to a determination that no sufficient match has been found, conducting a feature oriented search by comparing pixel blocks of the reference frame with the selected pixel block of the current frame to find a suitable match based upon a common feature. | 05-09-2013 |
20130148721 | Reference Frame Management for Screen Content Video Coding Using Hash or Checksum Functions - Techniques are provided for reference frame management for screen content video coding using hash or checksum functions. A video data stream including a plurality of frames is received, each frame including a plurality of pixels that define content within the frame. A plurality of hash code values associated with partitioned portions of a current frame are determined, where each hash code value is determined as an output value from a hash or checksum function based upon an input value comprising pixel values for a corresponding partition within the current frame. The current frame is compared with a plurality of reference frames based upon a comparison of the hash code values of the current frame with hash code values of the reference frames. A reference frame is selected as a candidate reference frame for coding the current frame. | 06-13-2013 |
20130166650 | Efficient Frame Forwarding in Large Scale Real-Time Screen Content Sharing Meetings - Techniques are provided to improve user experience at endpoint devices that are participating in a multipoint screen content sharing session. A server in a multipoint communication system receives video frames from a sending endpoint device in the communication session that involves one or more other endpoint devices that are to receive video frames from the sending endpoint device. The video frames include key reference frames that use either intra-frame prediction or inter-frame prediction based only on other key reference frames. The server stores the key reference frames. When a new receiving endpoint device joins the communication session, the server sends all the stored key reference frames to the new receiving endpoint device. All video frames received from the sending endpoint device are forwarded to existing ordinary receiving endpoint devices. Key reference frames and some, but not all, non-key reference video frames are forwarded to existing low-capacity receiving endpoint devices. | 06-27-2013 |
Patent application number | Description | Published |
20080249884 | POS-centric digital imaging system - A POS-centric digital imaging system for installation at a retail point of sale (POS) station having a countertop surface. The POS-centric digital imaging system includes a system housing having at least one imaging window, and providing a cashier side and a customer side for the POS-centric digital imaging system. An omni-directional digital image capturing and processing subsystem is disposed in the system housing, for generating a 3D imaging volume adjacent the imaging window. A cashier/customer terminal is integrated within the system housing, for simultaneously supporting (i) cashier product scanning/imaging and checkout operations on said cashier side, and (ii) customer payment and other services on said customer side. | 10-09-2008 |
20080252985 | Tunnel-type digital imaging-based self-checkout system for use in retail point-of-sale environments - A tunnel-type digital imaging-based self-checkout system capable of generating and projecting coplanar illumination and imaging planes into a 3D imaging volume within a tunnel structure. The tunnel structure is supported above a package conveyor in a retail POS environment, and employs automatic package identification, profiling and tracking techniques during self-checkout operations. | 10-16-2008 |
20080283611 | Digital image capture and processing systems for supporting 3D imaging volumes in retail point-of-sale environments - Digital image capture and processing systems and methods for generating and projecting coplanar illumination and imaging planes and/or coextensive area-type illumination and imaging zones, through one or more imaging windows, and into a 3D imaging volume in a retail POS environments, while employing automatic object motion and/or velocity detection, real-time image analysis and other techniques to capture and processing high-quality digital images of objects passing through the 3D imaging volume, and intelligently controlling and/or managing the use of visible and invisible forms of illumination, during object illumination and imaging operations, that might otherwise annoy or disturb human operators and/or customers working and/or shopping in such retail environments. | 11-20-2008 |
20090101719 | Digital image capturing and processing system for automatically recognizing graphical intelligence graphically represented in digital images of objects - A digital image capturing and processing system including a system housing having an imaging window; illumination and imaging stations for generating and projecting illumination and imaging planes or zones through the imaging window, and into a 3D imaging volume definable relative to the imaging window, for digital imaging an object passing through the 3D imaging volume, and generating digital linear images of the object as the object intersects the illumination and imaging planes or zones during system operation. A digital image processor processes the digital images and automatically recognizes graphical intelligence (e.g. bar code symbols, alphanumeric characters etc) graphically represented in the digital images. | 04-23-2009 |
20090134221 | Tunnel-type digital imaging-based system for use in automated self-checkout and cashier-assisted checkout operations in retail store environments - A tunnel-type digital imaging-based system capable of generating and projecting coplanar and/or coextensive illumination and imaging planes or zones into a 3D imaging volume within a tunnel structure. The system includes a tunnel housing structure which is supported above a package conveyor in a retail environment, and employs automatic package detection, identification, profiling/dimensioning, weighing, tracking and correlating techniques during self-checkout and/or cashier-assisted operations for achieving increased levels of efficiency and productivity. | 05-28-2009 |
20140166755 | ENCODED INFORMATION READING TERMINAL WITH MULTIPLE IMAGING ASSEMBLIES - An encoded information reading (EIR) terminal can comprise a microprocessor, a communication interface, an image processing circuit communicatively coupled to the microprocessor, a plurality of imaging assemblies communicatively coupled to the image processing circuit, and one or more memory blocks communicatively coupled to the image processing circuit. Each imaging assembly of the plurality of imaging assemblies can be configured to output image frame data. The image processing circuit can be configured to receive the image frame data from at least one imaging assembly, buffer the image frame data received from at least one imaging assembly in at least one memory block, and/or process the image frame data received from at least one imaging assembly. The EIR terminal can be configured to output image frame data comprising decodable indicia and/or decoded message data corresponding to the decodable indicia. | 06-19-2014 |
20140166759 | PACKAGE-ON-PACKAGE BASED INTEGRATED CIRCUIT CHIP IMAGER - An apparatus for use in decoding a bar code symbol includes a first integrated circuit chip with a wafer level camera, at least one light source, and a plurality of contact pads on a surface of the chip and a second integrated circuit chip with a processor, memory, plurality of contact pads on a surface of the chip, and plurality of contact pads on another surface of the chip. The apparatus includes a PCB having a plurality of contact pads disposed on at least one surface of the PCB and wherein the first and second integrated circuit chips are vertically stacked on the PCB and the plurality of contact pads on the first and second integrated circuit chips interface with the contact pads of the second integrated circuit chip and PCB. The apparatus is operative for processing image signals generated by the WLC for attempting to decode the bar code symbol. | 06-19-2014 |
20140346233 | IMAGING BASED BARCODE SCANNER ENGINE WITH MULTIPLE ELEMENTS SUPPORTED ON A COMMON PRINTED CIRCUIT BOARD - An apparatus for use in decoding a bar code symbol may include an image sensor integrated circuit having a plurality of pixels, timing and control circuitry for controlling an image sensor, gain circuitry for controlling gain, and analog to digital conversion circuitry for conversion of an analog signal to a digital signal. The apparatus may also include a printed circuit board for receiving the image sensor integrated circuit. The connection between the image sensor integrated circuit and the printed circuit board characterized by a plurality of conductive adhesive connectors disposed between a plurality of electrode pads and a plurality of contact pads, where the conductive adhesive connectors provide electrical input/output and mechanical connections between the image sensor integrated circuit and the printed circuit board. The apparatus may be operative for processing image signals generated by the image sensor integrated circuit for attempting to decode the bar code symbol. | 11-27-2014 |
Patent application number | Description | Published |
20090161699 | Laser emitting material, method for making the same and use thereof - A solid-state laser emitting material for use in conjunction with a light source includes a polymer matrix functioning as host materials, containing laser dye of rhodamine 590 or rhodamine 610 as gain materials and nano-submicron particles as scatters therein. The lowest lasing threshold of the laser emitting material is approximately 5 mJ/cm | 06-25-2009 |
20100024376 | Method and apparatus for manufacturing slalom false twisting on ring yarn - In a process for manufacturing a singles ring yarn, a method and apparatus is invented which utilizes double belts as a false twist device and incorporates it in the conventional ring spinning machine for producing a singles ring yarn. In this invention, a double-belts is applied thus two twisting points, instead of one twisting point, are adopted for the yarn false twisting to improve the false twist efficiency. Accordingly, a ratio of the velocity of the belt to the delivery speed of the yarn is controlled and the wrapping angle of the yarn on the belts is adjusted in order to obtain the desired property of the final singles ring yarn. The said invention can enhance the strength of fiber strand at the spinning triangle and thus ensure the yarns spun in a normal condition at low twist multipliers, which is unable to be obtained by the conventional ring spinning machine. The method produces yarns with good strength, less hairiness and lower yarn residual torque at low twist level and endows the resultant fabric with softer handle, low spirality as well as clear and smooth surface appearance. The method and apparatus has the advantages of easy yarn piecing-up and doffing process, low spinning end-breakage when using ordinary raw materials and low cost of investment and maintenance, which not only is able to meet the commercial requirements of the large-scale production in the textile industry but also possesses a high false twist efficiency. | 02-04-2010 |
Patent application number | Description | Published |
20120151894 | Method And Apparatus For Reducing Residual Torque And Neps In Singles Ring Yarns - Method and apparatus for reducing residual torque in singles ring yarns, achieved by imparting two separate false twisting points on the traveling strand of fibers (or yarn) after the strand exits from the spinning triangle with a proper ratio between the belt speed and the strand feeding speed. In addition to reducing the residual torque, this double false twist technique also reduces yarn hairiness to the same level as achieved by more expensive compact spinning devices, reduces yarn twist by more than 20% and significantly enhances yarn and fabric softness. Furthermore, by combining the double false twist technique with a compact spinning device, the numbers of neps, thick and thin places are significantly reduced to produce high-quality yarns and fine-count yarns. | 06-21-2012 |
20130269172 | PROCESS FOR MANUFACTURING FABRIC PRESSURE SENSOR AND TOOL FOR MANUFACTURING FABRIC PRESSURE SENSOR - A process for manufacturing a fabric pressure sensor comprises cutting a sensing fabric to a pre-determined size, connecting a flexible electric wire with a wire of the sensing fabric by sewing, fixing the sensing fabric by means of a clamping positioner at a pre-determined tension, bonding a lower conversion layer with the sensing fabric by means of a lower conversion layer positioning box, bonding an adjustable column with the sensing fabric by means of an upper conversion layer positioning box, and bonding the upper conversion layer with the adjustable column by means of the upper conversion layer positioning box. A tool for manufacturing the sensor comprises an electrical property measuring device, a wire connecting tool, and a sensor structural component assembling tool. The present invention provides an easy and convenient way of manufacturing a fabric pressure sensor, monitoring the quality of manufacture, and enhancing the manufacturing precision and product yield. | 10-17-2013 |
Patent application number | Description | Published |
20080258273 | Package Structure With Flat Bumps For Electronic Device and Method of Manufacture the Same - The invention discloses an ultra thin package structure of leadless electronic device and the packaging method, and includes lead support base adjacent to the chip support base; chip mounted on the chip support base; wires bonded between chip and lead support base; the molded body encapsulating the top surface and side surface of the chip support base, small protrusions of the chip support base and lead support base below the molded body; in the individual package, the number of the chip support base island can be one or more, the lead pins can be arrayed at one side of the island, also can be arrayed at two sides or three sides of the island, one or two rows of lead pins can be located around the island. | 10-23-2008 |
20080285251 | Packaging Substrate with Flat Bumps for Electronic Devices and Method of Manufacturing the Same - A packaging substrate with fiat bumps for an electronic device and a method of manufacturing the same relate to the production of the packaging substrate for an electronic device, which comprises base islands and pins structurally and wherein the base islands and pins which all exhibit flat bump shape distribute on the front face of the substrate; the bottom side of the bumps, namely the rear faces of the base islands and pins are contiguous in the same substrate; in the packaging body of a single electronic device to be formed in later procedure, one or more base island may be included, the pins may arrange on one single side of the base island, also may arrange on the both sides or three sides of the base island, or may surround the base island so as to form the structure of one or more circuits of pins. The method includes that take a metal substrate is prepared, mask layers are adhered onto both sides of the metal substrate, the parts of the mask layers which need to be etched are removed, then half-etching is performed to form the recessed half-etching area, and then the residual mask layers on the metal substrate are removed to product the packaging substrate with flat bumps. | 11-20-2008 |
20080315412 | Package Structure with Flat Bumps for Integrate Circuit or Discrete Device and Method of Manufacture the Same - The invention discloses a novel package structure of integrate circuit or discrete device and packaging method, and includes the lead pins adjacent to the island; another metal layer formed at the bottom of the island; another metal layer formed at the bottom of lead pins; chip mounted on the island; wires bonded between the chip and the lead pins; the molded body encapsulating the top surface and side surface of the island and the lead pins, small protrusions of the island and the lead pins below the molded body; in the individual package, the number of the island can be one or more, lead pins can be arrayed at one side of the island, also can be arrayed at two sides or three sides of the island, one or two rows of lead pins can be located around the island. The invention provides strong welding, good quality, low cost, smooth production, wide applicability, flexible arrangement of the chips. | 12-25-2008 |
Patent application number | Description | Published |
20130224910 | METHOD FOR CHIP PACKAGE - Provided is a method for chip packaging, including the steps of: providing a semi-packaged wafer which has a cutting trail and a metal bonding pad of the chip; forming on the metal bonding pad a sub-ball metal electrode, using a selective formation process; forming a protective layer on the wafer in a region not including the sub-ball metal electrode, with the protective layer covering the cutting trail; forming a solder ball on the sub-ball metal electrode; dicing the wafer along the cutting trail. The present invention can prevent metal in the cutting trail from being affected during the production of the sub-ball metal electrode, and protect the lateral sides of a discrete chip after cutting. The process flow thereof is simple, and enhances the efficiency of the packaging as well as its yield. | 08-29-2013 |
20130280904 | METHOD FOR CHIP PACKAGING - Provided is a method for chip packaging, including the steps of: providing a semi-packaged wafer which has a cutting trail and a metal bonding pad of the chip; forming a first protective layer on the cutting trail; forming on the metal bonding pad a sub-ball metal electrode; forming a solder ball on the sub-ball metal electrode; dicing the wafer along the cutting trail. The first protective layer according to the present invention can prevent the metal in the cutting trail from being separated by electroplating, and protect the lateral sides of a discrete chip after cutting. The process flow thereof is simple, and enhances the efficiency of the packaging as well as its yield. | 10-24-2013 |
20130301228 | PACKAGING STRUCTURE - The present invention relates a packaging structure including: a carrier board and a cementing layer on the surface of the carrier board; chips and passive devices having functional side thereof attached to the cementing layer; and a sealing material layer for packaging and curing, the sealing material being formed on the carrier board on the side attached to the chips and the passive devices. The present invention integrates chips and passive devices and then packages the chips and the passive devices together, and is therefore a packaged product having not single-chip functionality but integrated-system functionality. The present invention is highly integrated, reduces interfering factors such as system-internal electric resistance and inductance, and accommodates growing demand for lighter, thinner, shorter, and smaller semiconductor packaging. | 11-14-2013 |
20130302947 | PACKAGING METHOD - The present invention relates to a packaging method including the steps: a cementing layer is formed on a carrier board; the functional sides of chips and passive devices are attached to the cementing layer; a sealing material layer is formed on the side of the carrier board to which the chips and the passive devices are attached, and packaging and curing are performed; and the carrier board and the cementing layer are removed. Compared to the prior art, the system-level fan-out wafer packaging method claimed by the present invention first integrates chips and passive devices and then packages the chips and the passive devices together, thereby forming a final packaged product having not single-chip functionality but integrated-system functionality. Compared to current system-level packaging, highly integrated wafer-level packaging reduces such interfering factors as system-internal electric resistance and inductance, and accommodates the growing demand for lighter, thinner, shorter, and smaller semiconductor packaging. | 11-14-2013 |
20130313699 | FAN-OUT HIGH-DENSITY PACKAGING METHODS AND STRUCTURES - A fan-out high-density packaging method includes providing a packaging substrate, forming a stripping film on the packaging substrate, and forming a first protection layer on the stripping film and pre-designed photolithography pattern openings on the first protection layer. The method also includes forming a metal redistribution layer on the surface of the first protection layer and in the photolithography pattern openings, forming a second protection layer on the first protection layer and partially exposing the metal redistribution layer, and forming at least one package layer on the second protection layer. Each of at least one package layer includes a straight mounting layer, a sealant layer, and a wiring layer formed in sequence, and the package layer connects the metal redistribution layer through the wiring layer. Further, the method includes forming at least one top-level package layer on top of the at least one package layer, removing the packaging substrate and the stripping film to expose the metal redistribution layer in the first protection layer, and planting metal solder balls on the exposed metal redistribution layer. | 11-28-2013 |
20130320533 | 3D SYSTEM-LEVEL PACKAGING METHODS AND STRUCTURES - A 3D system-level packaging method includes providing a packaging substrate having a first functional surface and a second surface with wiring arrangement within the packaging substrate and between the first functional surface and the second surface. The method also includes forming at least one flip package layer on the first functional surface of the packaging substrate and forming at least one wiring and package layer on the flip package layer. The flip package layer is formed by subsequently forming a flip mounting layer, an underfill, a sealant layer, and a wiring layer; and the wiring and package layer is formed by subsequently forming a straight mounting layer, a sealant layer, and a wiring layer. Further, the method includes planting connection balls on the second functional surface of the packaging substrate. | 12-05-2013 |
20130320534 | SYSTEM-LEVEL PACKAGING METHODS AND STRUCTURES - A system-level packaging method includes providing a packaging substrate having a first functional surface and a second surface with wiring arrangement within the packaging substrate and between the first functional surface and the second surface. The method also includes forming at least two package layers on the first functional surface of the packaging substrate, wherein each package layer is formed by subsequently forming a mounting layer, a sealant layer, and a wiring layer. Further, the method includes forming a top sealant layer and planting connection balls on the second functional surface of the packaging substrate. | 12-05-2013 |
20130320535 | THREE-DIMENSIONAL SYSTEM-LEVEL PACKAGING METHODS AND STRUCTURES - A 3D system-level packaging method includes providing a packaging substrate, forming a glue layer on the substrate, and attaching a first chip layer at an opposite side of a functional surface of the first chip layer on the packaging substrate through the glue layer. The method also includes forming a first sealant layer on the packaging substrate at a same side attached with the first chip layer and exposing bonding pads of the first chip layer. The method also includes forming first vias in the first sealant layer, forming first vertical metal wiring in the first vias, and forming a first horizontal wiring layer on the sealant layer interconnecting the first chip layer and the first vertical metal wiring. Further, the method includes forming a plurality of package layers on the first sealant layer, and each of the plurality of package layers includes a chip layer, a sealant layer covering the chip layer, and vertical metal wiring and a horizontal wiring layer interconnecting adjacent package layers. | 12-05-2013 |