Patent application number | Description | Published |
20090302753 | ORGANIC ELECTRO-LUMINESCENCE DISPLAY - An organic electro-luminescence display includes an organic electro-luminescence device array, a first passivation layer completely covering organic electro-luminescence device array, and a plurality of color filters disposed on the first passivation layer. The color filters include a plurality of red color filters, green color filters, or blue color filters. The organic electro-luminescence device array includes a white light organic electro-luminescence device array. The type of the organic electro-luminescence device array includes an active matrix array or a passive matrix array. | 12-10-2009 |
20090305597 | PROCESS OF FABRICATING ORGANIC ELECTRO-LUMINESCENCE DISPLAY - In a process of fabricating an organic electro-luminescence display, a substrate, a plurality of organic electro-luminescence devices, and a patterned separator structure are provided. The organic electro-luminescence devices and the patterned separator structure are disposed over the substrate. The patterned separator structure separates the organic electro-luminescence devices. A thickness of the patterned separator structure is greater than that of the organic electro-luminescence devices. A first passivation layer is then formed to completely cover the patterned separator structure and the organic electro-luminescence devices. A plurality of color filters are formed on the first passivation layer. The color filters are located above the organic electro-luminescence devices. | 12-10-2009 |
20100117529 | PIXEL STRUCTURE - A pixel structure driven by a scan line and a data line arranged on a substrate is provided. The pixel structure includes a control unit, an OEL unit and a semi-transparent reflector structure. The control unit driven by the scan line and the data line is arranged on the substrate. The OEL unit is arranged on the substrate and includes a transparent electrode, a light-emitting layer and a metal electrode. The transparent electrode is electrically connected with the control unit. The light-emitting layer is disposed on the transparent electrode. The metal electrode is disposed on the light-emitting layer. The semi-transparent reflector structure is sandwiched between the substrate and the OEL unit, and includes at least a plurality of first and second dielectric layers. The first and second dielectric layers are alternately stacked, and the refractive index of the first dielectric layers is different from that of the second dielectric layers. | 05-13-2010 |
20100119729 | METHOD FOR FABRICATING CARBON-ENRICHED FILM - A method for fabricating a carbon-enriched film includes the following steps. First, a substrate is provided. Next, a CF | 05-13-2010 |
Patent application number | Description | Published |
20100208598 | METHOD AND APPARATUS FOR SCANNING CHANNELS IN WIRELESS LOCAL AREA NETWORK - Instead of scanning all the channels at once, the present method separates a channel scanning procedure into multiple channel scanning operations. The method reduces a data loss rate during the operation by returning to the operating channel an associated access point operates on in accordance with a return period for transceiving blocked packets. | 08-19-2010 |
20100240333 | METHOD AND APPARATUS FOR PROGRESSIVELY SCANNING CHANNELS - A method for progressively scanning channels first checks whether all channel scanning tasks are completed so as to determine a channel that will be scanned first. During the scanning process, the method records a channel as a last scanned channel after completing a channel scanning task for the channel. In addition, the method scans a channel with a valid service set identifier to increase the possibility of detecting hidden access points. | 09-23-2010 |
20100265928 | METHOD FOR SELECTING AN ACCESS POINT AND APPARATUS FOR USING THE SAME - The method generates a candidate list in accordance with the contents of frames transmitted by access points and sequentially performs the handshaking operations with the access points on the candidate list to select a personal identification number (PIN) enabled access point. During the candidate list generating process, this method places Wi-Fi protected setup (WPS) PIN-enabled access points at high priority positions but eliminates non-WPS access points and WPS push button configuration enabled access points. | 10-21-2010 |
20100265930 | METHOD FOR SCANNING WIRELESS CHANNELS, APPARATUS AND SYSTEM FOR USING THE SAME - In order to obtain information related to operating channels of access points, the method receives lightweight beacons on a common channel. The method generates a channel scanning list in accordance with the content of the lightweight beacons and sequentially scans all the channels on the list. The method is capable of reducing the scanning time and the data loss rate during the scanning operation. | 10-21-2010 |
Patent application number | Description | Published |
20110057263 | ULTRA HIGH VOLTAGE MOS TRANSISTOR DEVICE - An ultra high voltage MOS transistor device includes a substrate having a first conductive type, a first well having a second conductive type and a second well having the first conductive type formed in the substrate, a drain region having the second conductive type formed in the first well, a source region having the second conductive type formed in the second well, a first doped region having the first conductive type formed between the second well and the substrate, an insulating layer formed in a first recess in the first well, a gate formed on the substrate between the source region and the first well, and a recessed channel region formed in the substrate underneath the gate. | 03-10-2011 |
20110080213 | SEMICONDUCTOR DEVICE AND METHOD FOR OPERATING THE SAME - A semiconductor device includes a lateral double diffused metal oxide semiconductor (LDMOS) , a junction field effect transistor (JFET) and an inner circuit. The lateral double diffused metal oxide semiconductor includes a first source, a common drain and a first gate. The junction field effect transistor includes a second source, the common drain and a second gate. The second source is electrically connected to the first gate. The inner circuit is electrically connected to the first source. | 04-07-2011 |
20120038414 | METHOD FOR OPERATING SEMICONDUCTOR DEVICE - A method for operating a semiconductor device including a lateral double diffused metal oxide semiconductor (LDMOS) with a first source, a common drain and a first gate, a junction field effect transistor (JFET) with a second source, the common drain and a second gate wherein the second source is electrically connected to the first gate and an inner circuit electrically connected to the first source is provided. The first source provides the inner circuit with an inner current to generate an inner voltage by means of the lateral double diffused metal oxide semiconductor, and the lateral double diffused metal oxide semiconductor turns off when the inner voltage is elevated substantially as high as the first gate voltage. | 02-16-2012 |
20120091526 | ULTRA HIGH VOLTAGE MOS TRANSISTOR DEVICE - An ultra high voltage MOS transistor device includes a substrate having a first conductivity type and a first recess formed thereon, a gate positioned on the first recess, and a pair of source region and drain region having a second conductivity type formed in two sides of the gate, respectively. | 04-19-2012 |
20130256789 | POWER SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF - A fabrication method of a power semiconductor device is provided. Firstly, a plurality of trenched gate structures is formed in the base. Then, a body mask is used for forming a pattern layer on the base. The pattern layer has at least a first open and a second open for forming at least a body region and a heavily doped region in the base respectively. Then, a shielding structure is formed on the base to fill the second open and line at least a sidewall of the first open. Next, a plurality of source doped regions is formed in the body region by using the pattern layer and the shielding structure as the mask. Then, an interlayer dielectric layer is formed on the base and a plurality of source contact windows is formed therein to expose the source doped regions. | 10-03-2013 |