Patent application number | Description | Published |
20120144499 | SYSTEM TO INFORM ABOUT TRADEMARKS SIMILAR TO PROVIDED INPUT - Various embodiments of the present invention generally relate to trademark searching and notification systems. More specifically, various embodiments of the present invention relate to systems and methods for informing requesters about trademarks similar to a provided input. Some embodiments of the present invention provide for a proactive system in which users are notified of similar trademarks before using specific term(s) and users proceed after understanding which trademarks actually exist and what areas those trademarks actually entail, and possibly being notified of newly applied trademarks and modified trademarks at later times that are similar to the specific term(s) being used. | 06-07-2012 |
20130254179 | SYSTEMS AND METHODS FOR BRAND ENFORCEMENT - Systems and methods for brand monitoring, protection, and expansion are provided. More specifically, various embodiments of the present invention relate to systems and methods for tracking and enforcing trademark rights and identifying domain names and websites of interest. Some embodiments use various techniques and methods for obtaining data pertaining to a domain name of interest. A GUI can be used for obtaining input from a user and displaying reports to the user. The user can submit a domain name and a list of key words, and the system can return a list of matching domain names, from which the user selects one or more domain names of interest. A watch can be placed on each domain name of interest. Various data about the domain name of interest is cached allowing for a historical analysis of the website which can be used to make better brand enforcement and expansion decisions. | 09-26-2013 |
20130275427 | SYSTEM TO INFORM ABOUT TRADEMARKS SIMILAR TO PROVIDED INPUT - Various embodiments of the present invention generally relate to trademark searching and notification systems. More specifically, various embodiments of the present invention relate to systems and methods for informing requesters about trademarks similar to a provided input. Some embodiments of the present invention provide for a proactive system in which users are notified of similar trademarks before using specific term(s) and users proceed after understanding which trademarks actually exist and what areas those trademarks actually entail, and possibly being notified of newly applied trademarks and modified trademarks at later times that are similar to the specific term(s) being used. | 10-17-2013 |
20130317904 | SYSTEMS AND METHODS FOR DETERMINING ADVERTISING COMPLIANCE - Systems and methods for determining advertising compliance are provided. More specifically, various embodiments of the present invention relate to systems and methods for tracking, ranking, and enforcing the placement of advertisements in websites in accordance with one or more advertising policies. Some embodiments provide for a system where a user can enter text advertising campaigns for evaluation. The results can be ranked and the user can determine if any disputes need to be submitted for the violation of advertising policies. | 11-28-2013 |
20130318177 | SYSTEMS AND METHODS FOR PORTFOLIO MONITORING - Systems and methods for determining portfolio monitoring are provided. More specifically, various embodiments of the present invention relate to systems and methods for monitoring a portfolio of domain names for expiration, availability, and collection of redirection analytics. In some embodiments, a portfolio monitoring system can provide change warnings about various domain names along with historical information (e.g., ownership, snapshots, valuation, redirection analytics, etc.) about the domains. This information can be used in making an automated or manual decision to purchase or renew the domain name. | 11-28-2013 |
20140372316 | SYSTEM TO INFORM ABOUT TRADEMARKS SIMILAR TO PROVIDED INPUT - Various embodiments of the present invention generally relate to trademark searching and notification systems. More specifically, various embodiments of the present invention relate to systems and methods for informing requesters about trademarks similar to a provided input. Some embodiments of the present invention provide for a proactive system in which users are notified of similar trademarks before using specific term(s) and users proceed after understanding which trademarks actually exist and what areas those trademarks actually entail, and possibly being notified of newly applied trademarks and modified trademarks at later times that are similar to the specific term(s) being used. | 12-18-2014 |
20150081527 | METHOD AND SYSTEM FOR PROVIDING ONLINE SERVICES AND SOFTWARE - A method and system provides online software and services via prepaid scratchcards. Users may pay for online software and services with prepaid scratchcards. For example, online services may include accounting, legal, and auditing services. For example, online software may include productivity and business software. For example, online services and software may be provided on a subscription basis. Use of scratchcards may improve availability of software and services to more users, protect user security, and facilitate gifting between users. | 03-19-2015 |
Patent application number | Description | Published |
20090124084 | FABRICATION OF SUB-RESOLUTION FEATURES FOR AN INTEGRATED CIRCUIT - A method for fabricating sub-resolution features on an integrated circuit comprises depositing a hard mask layer on a dielectric layer of a semiconductor substrate, patterning the hard mask layer to form hard mask structures that define trenches, etching trenches in the dielectric layer through the hard mask structures, thereby forming a first set of dielectric structures on the substrate, depositing a conformal layer on the substrate and the first set of dielectric structures, etching the conformal layer to form spacers adjacent to the first set of dielectric structures, depositing a second dielectric layer within the trenches, thereby forming a second set of dielectric structures on the substrate, and etching the spacers to form sub-resolution trenches between the dielectric structures of the first and second set. | 05-14-2009 |
20090170316 | Double patterning with single hard mask - In general, in one aspect, a method includes forming a hard mask on a semiconductor substrate. A first resist layer is patterned on the hard mask as a first plurality of lines separated by a first defined pitch. The hard mask is etched to a portion of formed thickness to create a first plurality of fins in alignment with the first plurality of lines and the first resist layer is removed. A second resist layer is patterned on the hard mask as a second plurality of lines separated by a second defined pitch. The second plurality of lines is patterned between the first plurality of lines. The hard mask is etched to the portion of the formed thickness to create a second plurality of fins in alignment with the second plurality of lines. The first plurality of hard mask fins and the second plurality of hard mask fins are interwoven and have same thickness. | 07-02-2009 |
20090263751 | Methods for double patterning photoresist - Embodiments of methods for double patterning photoresist are generally described herein. Other embodiments may be described and claimed. | 10-22-2009 |
Patent application number | Description | Published |
20120164837 | FEATURE SIZE REDUCTION - Methods for semiconductor device fabrication are provided. Features are created using spacers. Methods include creating a pattern comprised of at least two first features on the substrate surface, depositing a first conformal layer on the at least two first features, depositing a second conformal layer on the first conformal layer, partially removing the second conformal layer to partially expose the first conformal layer, and partially removing the first conformal layer from between the first features and the second conformal layer thereby creating at least two second features. Optionally the first conformal film is partially etched back before the second conformal film is deposited. | 06-28-2012 |
20140117488 | PATTERN DECOMPOSITION LITHOGRAPHY TECHNIQUES - Techniques are disclosed for realizing a two-dimensional target lithography feature/pattern by decomposing (splitting) it into multiple unidirectional target features that, when aggregated, substantially (e.g., fully) represent the original target feature without leaving an unrepresented remainder (e.g., a whole-number quantity of unidirectional target features). The unidirectional target features may he arbitrarily grouped such that, within a grouping, all unidirectional target features share a common target width value. Where multiple such groupings are provided, individual groupings may or may not have the same common target width value. In some cases, a series of reticles is provided, each reticle having a mask pattern correlating to a grouping of unidirectional target features. Exposure of a photoresist material via the aggregated series of reticles substantially (e.g., fully) produces the original target feature/pattern. The pattern decomposition techniques may be integrated into any number of patterning processes, such as litho-freeze-litho-etch and litho-etch-litho-etch patterning processes. | 05-01-2014 |
20140191372 | SPACER ASSISTED PITCH DIVISION LITHOGRAPHY - Spacer-based pitch division lithography techniques are disclosed that realize pitches with both variable line widths and variable space widths, using a single spacer deposition. The resulting feature pitches can be at or below the resolution limit of the exposure system being used, but they need not be, and may be further reduced (e.g., halved) as many times as desired with subsequent spacer formation and pattern transfer processes as described herein. Such spacer-based pitch division techniques can be used, for instance, to define narrow conductive runs, metal gates and other such small features at a pitch smaller than the original backbone pattern. | 07-10-2014 |
Patent application number | Description | Published |
20080231488 | BANDWIDTH MULTIPLICATION FOR A TEST AND MEASUREMENT INSTRUMENT USING NON-PERIODIC FUNCTIONS FOR MIXING - An acquisition apparatus for a test and measurement instrument including a splitter configured to split an input signal into a plurality of split signals, a plurality of oscillators, each oscillator configured to generate a periodic signal, a plurality of combiners, each combiner configured to combine an associated plurality of the periodic signals into an associated signal combination where at least one of the signal combinations is substantially non-periodic. The apparatus also includes a plurality of mixers, each mixer configured to mix an associated split signal and an associated signal combination into an associated mixed signal, a first digitizer configured to digitize an associated split signal, and a plurality of second digitizers, each second digitizer configured to digitize an associated mixed signal. | 09-25-2008 |
20080281542 | CALIBRATION OF A PARTIALLY SYMMETRIC FIXTURE - A method useful for the characterization of a fixture splits a partially symmetric THRU structure into portions which may then be mathematically removed from both ports of a 2-port measured structure, leaving only the desired device under test (DUT). | 11-13-2008 |
20100085362 | EQUALIZATION SIMULATOR WITH TRAINING SEQUENCE DETECTION FOR AN OSCILLOSCOPE - An equalization simulator with training sequence detection uses an oscilloscope to acquire digital samples of an analog waveform signal from a serial data link to produce a digitized waveform record. The equalization simulator has training sequence detection receiving the digitized waveform record and generates a training sequence, an equalization adapter receiving the digitized waveform record and the training sequence and generating equalizer taps, and an equalizer receiving the equalizer taps and the digitized waveform record and generating an equalized digitized waveform record. | 04-08-2010 |
Patent application number | Description | Published |
20120226727 | METHODS AND SYSTEMS FOR ANALYZING DECOMPOSED UNCORRELATED SIGNAL IMPAIRMENTS - Method and systems are described for estimating signal impairments, in particular jitter that includes uncorrelated, non-periodic signal impairments. One system may take the form of an oscilloscope. The estimates may take the form of a probability density function (PDF) for uncorrelated signal impairments that has been modified to replace low probability regions with a known approximation and an extrapolation of the known approximation. | 09-06-2012 |
20120320964 | METHODS AND SYSTEMS FOR PROVIDING OPTIMUM DECISION FEEDBACK EQUALIZATION OF HIGH-SPEED SERIAL DATA LINKS - Computationally efficient methods and related systems, for use in a test and measurement instrument, such as an oscilloscope, optimize the performance of DFEs used in a high-speed serial data link by identifying optimal DFE tap values for peak-to-peak based criteria. The optimized DFEs comply with the behavior of a model DFE set forth in the PCIE 3.0 specification. | 12-20-2012 |
20130093493 | ARBITRARY MULTIBAND OVERLAY MIXER APPARATUS ANDMETHOD FOR BANDWIDTH MULTIPLICATION - An apparatus and method for splitting a wide band input signal and overlaying multiple frequency bands on each path associated with one or more digitizers. All frequencies from the split signal on each path can be fed to a mixer. The local oscillator of each mixer receives a sum of signals, which can each be set to any arbitrary frequency, as long as an associated matrix determinant of coefficients is non-zero. Each oscillator signal is multiplied by a coefficient, which can represent phase and magnitude, prior to summing the oscillator signals together. Each mixer mixes a combined signal with the input, thereby generating a set of multiple overlaid frequency bands. The digitized signals are processed to substantially reconstruct the original input signal. Thus, the wide band input signal is digitized using multiple individual digitizers. In particular, a system can support two wide band signals using four digitizers of narrower bandwidth. | 04-18-2013 |
20130237170 | ARBITRARY MULTIBAND OVERLAY MIXER APPARATUS AND METHOD FOR BANDWIDTH MULTIPLICATION - An apparatus and method for splitting a wide band input signal and overlaying multiple frequency bands on each path associated with one or more digitizers. All frequencies from the split signal on each path can be fed to a mixer. The local oscillator of each mixer receives a sum of signals, which can each be set to any arbitrary frequency, as long as an associated matrix determinant of coefficients is non-zero. Each oscillator signal is multiplied by a coefficient, which can represent phase and magnitude, prior to summing the oscillator signals together. Each mixer mixes a combined signal with the input, thereby generating a set of multiple overlaid frequency bands. The digitized signals are processed to substantially reconstruct the original input signal. Thus, the wide band input signal is digitized using multiple individual digitizers. In particular, a system can support two wide band signals using four digitizers of narrower bandwidth. | 09-12-2013 |
20130332101 | SERIAL DATA LINK MEASUREMENT AND SIMULATION SYSTEM - A serial data link measurement and simulation system for use on a test and measurement instrument presents on a display device a main menu having elements representing a measurement circuit, a simulation circuit and a transmitter. The main menu includes processing flow lines pointing from the measurement circuit to the transmitter and from the transmitter to the simulation circuit. The main menu includes a source input to the measurement circuit and one or more test points from which waveforms may be obtained. The simulation circuit includes a receiver. The measurement and simulation circuits are defined by a user, and the transmitter is common to both circuits so all aspects of the serial data link system are tied together. | 12-12-2013 |
20130343442 | RE-SAMPLING S-PARAMETERS FOR SERIAL DATA LINK ANALYSIS - A device and method of re-sampling a plurality of S-parameters for serial data link analysis is disclosed. The method includes storing a plurality of S-parameters sets, each S-parameter set being associated with a subsystem and having associated impulse responses and a time interval. An increased time interval is determined based on the time interval associated with each S-parameter set. The impulse responses are zero filled in each S-parameter set to maintain any wrapped ripples and increase the time interval. A plurality of resampled S-parameter sets are generated with a finer frequency resolution to cover the increased time interval. | 12-26-2013 |
20140362901 | METHODS AND SYSTEMS FOR PROVIDING OPTIMUM DECISION FEEDBACK EQUALIZATION OF HIGH-SPEED SERIAL DATA LINKS - Computationally efficient methods and related systems, for use in a test and measurement instrument, such as an oscilloscope, optimize the performance of DFEs used in a high-speed serial data link by identifying optimal DFE tap values for peak-to-peak based criteria. The optimized DFEs comply with the behavior of a model DFE set forth in the PCIE 3.0 specification. | 12-11-2014 |
20150084655 | SWITCHED LOAD TIME-DOMAIN REFLECTOMETER DE-EMBED PROBE - A de-embed probe, including two inputs configured to connect to a device under test, a memory, a signal generator configured to output a signal, a plurality of load components, a plurality of switches, and a controller. Each load component is configured to provide a different load. A first switch of the plurality of switches is associated with the signal generator and the other switches of the plurality of switches are each associated with one load component. The controller is configured to control the plurality of switches to connect combinations of the loads from the plurality of load components and the signal from the signal generator across the two inputs. | 03-26-2015 |
20150084656 | TWO PORT VECTOR NETWORK ANALYZER USING DE-EMBED PROBES - A test and measurement system including a device under test, two de-embed probes connected to the device under test, and a test and measurement instrument connected to the two de-embed probes. The test and measurement instrument includes a processor configured to determine the S-parameter set of the device under test based on measurements from the device under test taken by the two de-embed probes. | 03-26-2015 |
Patent application number | Description | Published |
20100332868 | SQUELCH FILTRATION TO LIMIT FALSE WAKEUPS - Methods and apparatus relating squelch filtration to limit false wakeups are described. In one embodiment, a squelch logic generates a wakeup event for an agent based on occurrence of a number of pulses (originating from another agent) during a time period. Other embodiments are also disclosed. | 12-30-2010 |
20110060931 | POWER MEASUREMENT TECHNIQUES OF A SYSTEM-ON-CHIP (SOC) - A method and system to enable power measurements of a system-on-chip in various modes. In one embodiment of the invention, the system-on-chip has full controllability of its logic and circuitry to facilitate configuration of the system-on-chip into a desired mode of operation. This allows hooks or interfaces to access the system-on-chip externally for measurements. For example, in one embodiment of the invention, the hooks in the system-on-chip allow a backend tester to configure the system-on-chip into various modes easily to perform power consumption measurements of one or more individual components of the system-on-chip. The power consumption measurement of the individual components in the system-on-chip can be performed faster and can be more accurate. In addition, the overall yield of the SOC can be increased as it is easier to detect failure parts. | 03-10-2011 |
20110296216 | INTEGRATION OF PROCESSOR AND INPUT/OUTPUT HUB - Methods and apparatus for integration of a processor and an input/output hub are described. In one embodiment, a sideband signal may cause change in a power management state of a processor or an integrated I/O logic. A single integrated circuit die may include both the processor and the integrated I/O logic. Other embodiments are also disclosed. | 12-01-2011 |
20110296222 | DYNAMIC AND IDLE POWER REDUCTION SEQUENCE USING RECOMBINANT CLOCK AND POWER GATING - Methods and apparatus for dynamic and/or idle power reduction sequence using recombinant clock and/or power gating are described. In one embodiment, at least a portion of an Integrated Input/Output (IIO) logic is to enter a lower power consumption state based on a power reduction sequence. Other embodiments are also disclosed. | 12-01-2011 |
20130007573 | EFFICIENT AND SCALABLE CYCLIC REDUNDANCY CHECK CIRCUIT USING GALOIS-FIELD ARITHMETIC - Embodiments of the present disclosure describe methods, apparatus, and system configurations for cyclic redundancy check circuits using Galois-field arithmetic. | 01-03-2013 |
20140082451 | EFFICIENT AND SCALABLE CYCLIC REDUNDANCY CHECK CIRCUIT USING GALOIS-FIELD ARITHMETIC - Embodiments of the present disclosure describe methods, apparatus, and system configurations for cyclic redundancy check circuits using Galois-field arithmetic. | 03-20-2014 |
20140189212 | PRESENTATION OF DIRECT ACCESSED STORAGE UNDER A LOGICAL DRIVE MODEL - In accordance with embodiments disclosed herein, there are provided methods, systems, mechanisms, techniques, and apparatuses for presentation of direct accessed storage under a logical drive model; for implementing a distributed architecture for cooperative NVM Data protection; data mirroring for consistent SSD latency; for boosting a controller's performance and RAS with DIF support via concurrent RAID processing; for implementing arbitration and resource schemes of a doorbell mechanism, including doorbell arbitration for fairness and prevention of attack congestion; and for implementing multiple interrupt generation using a messaging unit and NTB in a controller through use of an interrupt coalescing scheme. | 07-03-2014 |
Patent application number | Description | Published |
20090085669 | Method and apparatus to enhance linearity and efficiency in an RF power amplifier - Dynamic biasing techniques are used to enhance both linearity and efficiency within a transistor power amplifier. In at least one embodiment, as the power level being processed by a transistor increases toward a saturation point, a transistor is moved from class B or class AB operation toward class A operation. This increases the linearity of operation (because class A operation is typically highly linear) without a corresponding decrease in efficiency (because efficiency typically peaks near saturation). Similarly, as the power level decreases from the saturation point, the transistor is moved from class A or class AB operation toward class B operation. This increases the efficiency (because class B operation is more efficient than class A or AB), while having little effect on linearity (because operation is moving away from saturation). | 04-02-2009 |
20090085689 | Digitally tuned, integrated baluns with enhanced linearity for multi-band radio applications - An integrated balun includes a low pass filter and a high pass filter that are formed on a semiconductor chip using tunable reactive elements. The outputs of the low pass filter and the high pass filter are tied together to form the single ended output of the balun. The inputs of the low pass filter and the high pass filter form the differential inputs of the balun. The low pass filter and the high pass filter each include a number of tunable networks for achieving the tunable reactive elements. Each tunable network includes at least one switching transistor and at least one fixed value reactive elements. In at least one embodiment, dynamic biasing circuitry may be provided to improve the linearity and reduce the insertion loss of the balun. | 04-02-2009 |
20090085818 | Digitally tuned, integrated RF filters with enhanced linearity for multi-band radio applications - An integrated, multi-band radio frequency (RF) filter is capable of modifying a filter response thereof in response to control information. Switching elements within the filter can be changed between on and off conditions to modify the filter response. In one implementation, the integrated, multi-band filter is integrated on a front end module chip to be used within a multi-radio wireless device. In at least one embodiment, linearity enhancement circuitry is provided within a multi-band filter to improve linearity and reduce insertion loss. | 04-02-2009 |