Patent application number | Description | Published |
20100258233 | CERAMIC SUBSTRATE, METHOD OF MANUFACTURING CERAMIC SUBSTRATE, AND METHOD OF MANUFACTURING POWER MODULE SUBSTRATE - Disclosed is a ceramic substrate including silicon in which the concentration of a silicon oxide and a silicon composite oxide in the surface thereof is less than or equal to 2.7 Atom %. | 10-14-2010 |
20100285331 | METHOD FOR MANUFACTURING POWER MODULE SUBSTRATE, POWER MODULE SUBSTRATE, AND POWER MODULE - A method for manufacturing a power module substrate, includes: preparing a ceramics substrate and a metal plate made of pure aluminum; a fusion step in which the ceramics substrate and the metal plate are stacked in layers with a brazing filler metal interposed therebetween, and a fused aluminum layer is formed at an interface between the ceramics substrate and the metal plate by fusing the brazing filler metal which is caused by heating; and a solidifying step in which the fused aluminum layer is solidified by cooling, and a crystal is grown so as to be arranged in a crystal orientation of the metal plate when the fused aluminum layer is solidified. | 11-11-2010 |
20110017496 | POWER MODULE SUBSTRATE HAVING HEATSINK, METHOD FOR MANUFACTURING THE SAME, POWER MODULE HAVING HEATSINK, AND POWER MODULE SUBSTRATE - A power module substrate having a heatsink, includes: a power module substrate having an insulating substrate having a first face and a second face, a circuit layer formed on the first face, and a metal layer formed on the second face; and a heatsink directly connected to the metal layer, cooling the power module substrate, wherein a ratio B/A is in the range defined by 1.55≦B/A≦20, where a thickness of the circuit layer is represented as A, and a thickness of the metal layer is represented as B. | 01-27-2011 |
20110067906 | POWER MODULE SUBSTRATE, POWER MODULE, AND METHOD FOR MANUFACTURING POWER MODULE SUBSTRATE - A power module substrate includes: a ceramics substrate composed of AlN, having a top face; a metal plate composed of pure aluminum and joined to the top face of the ceramics substrate with a brazing filler metal including silicon interposed therebetween; and a high concentration section formed at a joint interface at which the metal plate is joined to the ceramics substrate, having a silicon concentration that is more than five times the silicon concentration in the metal plate. | 03-24-2011 |
20110074010 | POWER MODULE SUBSTRATE, POWER MODULE, AND METHOD FOR MANUFACTURING POWER MODULE SUBSTRATE - A power module substrate includes: a ceramics substrate having a surface; and a metal plate connected to the surface of the ceramics substrate, composed of aluminum, and including Cu at a joint interface between the ceramics substrate and the metal plate, wherein a Cu concentration at the joint interface is in the range of 0.05 to 5 wt %. | 03-31-2011 |
20130232783 | CERAMIC SUBSTRATE, METHOD OF MANUFACTURING CERAMIC SUBSTRATE, AND METHOD OF MANUFACTURING POWER MODULE SUBSTRATE - Disclosed is a ceramic substrate including silicon in which the concentration of a silicon oxide and a silicon composite oxide in the surface thereof is less than or equal to 2.7 Atom %. | 09-12-2013 |
20140015140 | POWER MODULE SUBSTRATE, POWER MODULE, AND METHOD FOR MANUFACTURING POWER MODULE SUBSTRATE - A power module substrate includes: a ceramics substrate having a surface; and a metal plate connected to the surface of the ceramics substrate, composed of aluminum, and including Cu at a joint interface between the ceramics substrate and the metal plate, wherein a Cu concentration at the joint interface is in the range of 0.05 to 5 wt %. | 01-16-2014 |
20140071633 | POWER MODULE SUBSTRATE, POWER MODULE, AND METHOD FOR MANUFACTURING POWER MODULE SUBSTRATE - A power module substrate includes: a ceramics substrate composed of AlN, having a top face; a metal plate composed of pure aluminum and joined to the top face of the ceramics substrate with a brazing filler metal including silicon interposed therebetween; and a high concentration section formed at a joint interface at which the metal plate is joined to the ceramics substrate, having a silicon concentration that is more than five times the silicon concentration in the metal plate. | 03-13-2014 |
20140078684 | POWER MODULE SUBSTRATE, POWER MODULE, AND METHOD FOR MANUFACTURING POWER MODULE SUBSTRATE - A power module substrate includes: a ceramics substrate composed of AlN, having a top face; a metal plate composed of pure aluminum and joined to the top face of the ceramics substrate with a brazing filler metal including silicon interposed therebetween; and a high concentration section formed at a joint interface at which the metal plate is joined to the ceramics substrate, having a silicon concentration that is more than five times the silicon concentration in the metal plate. | 03-20-2014 |
20150022977 | POWER MODULE SUBSTRATE, POWER MODULE, AND METHOD FOR MANUFACTURING POWER MODULE SUBSTRATE - A power module substrate includes: a ceramics substrate having a surface; and a metal plate connected to the surface of the ceramics substrate, composed of aluminum, and including Cu at a joint interface between the ceramics substrate and the metal plate, wherein a Cu concentration at the joint interface is in the range of 0.05 to 5 wt %. | 01-22-2015 |
Patent application number | Description | Published |
20090064070 | SEMICONDUCTOR CIRCUIT DESIGN METHOD - This disclosure concerns a semiconductor circuit design method for designing a clock wiring structure supplying a clock to a flip-flop by using a computer. The semiconductor circuit design method comprises setting the flip-flop based on circuit information on a semiconductor integrated circuit; obtaining a control signal controlling the flip-flop; calculating a first evaluation value indicating a power consumption and a magnitude of a clock skew time when clock gating is applied to the flip-flop; setting a gated clock structure clock-gating the flip-flop when the first evaluation value is higher than a first threshold; calculating a second evaluation value indicating the power consumption and a magnitude of a cell area when a low power flip-flop lower in power consumption than the flip-flop is applied to the flip-flop; and replacing the flip-flop by the lower power flip-flop when the second evaluation value is higher than a second threshold. | 03-05-2009 |
20110010684 | SEMICONDUCTOR INTEGRATED CIRCUIT AND METHOD OF DESIGNING THE SAME - A semiconductor integrated circuit comprising: a clock gating cell to which an enable signal and a clock signal are input, so as to output a gated clock signal generated by output-controlling said clock signal according to said enable signal; a first flip-flop circuit to which a first input data signal and said gated clock signal are input, so as to retain and output said first input data signal as a first output data signal in synchronization with said gated clock signal; and a second flip-flop circuit to which a second input data signal is input, so as to retain and output said second input data signal as a second output data signal in synchronization with said clock signal if the logical values of said second input data signal and said second output data signal differ from each other, or so as to retain said second output data signal if the logical values of said second input data signal and said second output data signal are the same. | 01-13-2011 |
20110260764 | SEMICONDUCTOR INTEGRATED CIRCUIT, METHOD FOR DESIGNING SEMICONDUCTOR INTEGRATED CIRCUIT, AND COMPUTER READABLE RECORDING MEDIUM - A method for designing a semiconductor integrated circuit according to an embodiment includes: placing standard flip-flop circuits and low power-consumption flip-flop circuits; grouping the placed flip-flop circuits into clusters by using an evaluation function having indices including cell types; assigning a first clock buffer to each cluster formed only by standard flip-flop circuits; assigning a second clock buffer to each cluster including low power-consumption flip-flop circuits, the second clock buffer having a larger size than the first clock buffer; and performing clock wiring. | 10-27-2011 |
20140110771 | SOLID-STATE IMAGING DEVICE AND SEMICONDUCTOR DEVICE - According to one embodiment, a solid-state imaging device includes a semiconductor substrate including a pixel area and a peripheral circuit area, a first line provided in the peripheral circuit area and on a first principal surface of the semiconductor substrate, a second line provided in the peripheral circuit area and on a second principal surface of the semiconductor substrate, a first through electrode connected to one end of the first line and one end of the second line and passing through the semiconductor substrate, and a second through electrode connected to the other end of the first line and the other end of the second line and passing through the semiconductor substrate. | 04-24-2014 |