Patent application number | Description | Published |
20080307492 | SECURITY POLICY GENERATION - The invention provides security policy generation methods and devices for generating a security policy that is set up for an information processing apparatus comprises a step of generating an application model having a transmitter and a receiver of a message decided, for each of a plurality of messages that are communicated, a step of storing in advance a plurality of security patterns with a signer of electronic signature appended to the message as an undecided parameter, a step of selecting a security pattern that is a model of security policy to be setup for the transmitter or receiver of the message, corresponding to each of the plurality of messages included in the application model, and a step of substituting the identification information of the transmitter or receiver of each message included in the application model for the undecided parameter of the security pattern selected corresponding to the message. | 12-11-2008 |
20090009756 | Recognition Chip for Target Substance, and Detection Method and Device for the Same - A detection device comprising a substrate comprising a plurality of objects of which properties are changed due to the contact with a target substance, means for bringing the target substance into contact with the objects, and means for detecting a change in properties of the objects caused when the target substance is brought into contact with the objects, based on light output when the objects are irradiated with light, wherein the plurality of the objects are located in the direction in which the light for irradiation travels, and the detecting means is means for detecting the change in the properties based on the summation of light output from the plurality of the objects upon irradiation with light. | 01-08-2009 |
20090044248 | SECURITY POLICY GENERATION - The invention provides security policy generation methods and devices for generating a security policy that is set up for an information processing apparatus comprises a step of generating an application model having a transmitter and a receiver of a message decided, for each of a plurality of messages that are communicated, a step of storing in advance a plurality of security patterns with a signer of electronic signature appended to the message as an undecided parameter, a step of selecting a security pattern that is a model of security policy to be set up for the transmitter or receiver of the message, corresponding to each of the plurality of messages included in the application model, and a step of substituting the identification information of the transmitter or receiver of each message included in the application model for the undecided parameter of the security pattern selected corresponding to the message. | 02-12-2009 |
20090323935 | PSEUDO PUBLIC KEY ENCRYPTION - According to the present invention, a secret key cryptosystem and tamper-proof hardware are used to realize a pseudo-public key cryptosystem at a low cost. A trap-door one-way function is substantially realized with the use of tamper-proof hardware. Each user performs communication using equipment provided with hardware having the same capabilities described below. Such hardware retains association between an ID and a key. In response to a request from a user, the hardware issues and stores an ID, and it can perform decryption and generation of a MAC (message authentication code) with a key associated with the ID. A user publishes his ID. When performing encryption, a message sender encrypts a message using the published ID. A third person can perform decryption with the ID only by analyzing the mechanism in the hardware. However, the hardware has a capability of destroying itself when such an act is attempted. | 12-31-2009 |
20100216253 | Organic Material-Immobiling Structure and Method for Production of the Same, and Peptide and DNA Therefor - The invention provides an organic material-immobilizing structure employing new immobilization means, characterized in that at least a part of the surface of the substrate is comprised of one or more members containing silicon oxide, the organic material is bound to the surface of the substrate through a binding domain bound to the organic material and containing an amino acid sequence capable of binding to silicon oxide, selected from the group consisting of amino acid sequences of SEQ ID NOS: 1 and 2: Val-Ser-Pro-Met-Arg-Ser-Ala-Thr-Thr-His-Thr-Val; and Ile-Pro-Met-His-Val-His-His-Lys-His-Pro-His-Val, and derivatives thereof. | 08-26-2010 |
Patent application number | Description | Published |
20120241846 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - According to one embodiment, a nonvolatile semiconductor memory device comprises a first conductive layer, a second conductive layer, a first inter-electrode insulating film, and a third conductive layer stacked above the first conductive layer, a memory film, a semiconductor layer, an insulating member, and a silicide layer. The memory film and the semiconductor layer is formed on the inner surface of through hole provided in the second conductive layer, the first inter-electrode insulating film, and the third conductive layer. The insulating member is buried in a slit dividing the second conductive layer, the first inter-electrode insulating film, and the third conductive layer. The silicide layer is formed on surfaces of the second conductive layer and the third conductive layer in the slit. The distance between the second conductive layer and the third conductive layer along the inner surface of the slit is longer than that of along the stacking direction. | 09-27-2012 |
20130037776 | VARIABLE RESISTANCE MEMORY - A variable resistance memory according to an embodiment includes: a first wiring; a second wiring intersecting with the first wiring; a first electrode provided in an intersection region between the first wiring and the second wiring, the first electrode being connected to the first wiring; a second electrode connected to the second wiring, the second electrode facing to the first electrode; a variable resistance layer provided between the first electrode and the second electrode; and one of a first insulating layer and a first semiconductor layer formed at side portions of the second electrode. The one of the first insulating layer and the first semiconductor layer, and the second electrode form voids at the side portions of the second electrode. | 02-14-2013 |
20130062683 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - According to one embodiment, a method of manufacturing a semiconductor memory device is provided. In the method, a laminated body in which a first silicon layer, a first sacrificial layer, a second silicon layer, and a second sacrificial layer are laminated in turn is formed. A first insulating film is formed on the laminated body. A trench is formed in the laminated body and the first insulating film. A third sacrificial layer is formed into the trench. The third sacrificial layer is etched by wet etching to be retreated from a top surface of the third sacrificial layer, thereby etching end faces of the first sacrificial layer and the second sacrificial layer. | 03-14-2013 |
Patent application number | Description | Published |
20130070508 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - According to an embodiment, a method of manufacturing a semiconductor device including a memory array provided on a substrate, and a control circuit provided on a surface of the substrate between the substrate and the memory array, includes steps of forming, in an insulating layer covering a p-type semiconductor region and an n-type semiconductor region of the control circuit, a first contact hole communicating with the p-type semiconductor region; forming a contact plug, in contact with the p-type semiconductor region, within the first contact hole; forming, in the insulating layer, a second contact hole communicating with the n-type semiconductor region; and forming an interconnection contacting the contact plug and the n-type semiconductor region exposed within the second contact hole. | 03-21-2013 |
20140036567 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - According to an embodiment, a method of manufacturing a semiconductor device including a memory array provided on a substrate, and a control circuit provided on a surface of the substrate between the substrate and the memory array, includes steps of forming, in an insulating layer covering a p-type semiconductor region and an n-type semiconductor region of the control circuit, a first contact hole communicating with the p-type semiconductor region; forming a contact plug, in contact with the p-type semiconductor region, within the first contact hole; forming, in the insulating layer, a second contact hole communicating with the n-type semiconductor region; and forming an interconnection contacting the contact plug and the n-type semiconductor region exposed within the second contact hole. | 02-06-2014 |
Patent application number | Description | Published |
20130213525 | GRAIN ORIENTED ELECTRICAL STEEL SHEET AND METHOD FOR MANUFACTURING THE SAME - A grain oriented electrical steel sheet has a total length of cracks in a film on a steel sheet surface, of 20 μm or less per 10000 μm | 08-22-2013 |
20140255720 | ULTRATHIN ELECTROMAGNETIC STEEL SHEET - An electrical steel sheet has a component composition including, by mass %, C: 0.007% or less, Si: 4% to 10%, and Mn: 0.005% to 1.0%, the balance being Fe and incidental impurities, as well as a sheet thickness within a range of 0.01 mm or more to 0.10 mm or less, and a profile roughness. Pa of 1.0 μm or less. The electrical steel sheet exhibits excellent iron loss properties whereby the magnetic property is free from deterioration, and degradation of the stacking factor can be avoided, even when the steel sheet with a thickness of 0.10 mm or less has been subjected to siliconizing treatment to increase the Si content in the steel. | 09-11-2014 |
20150013850 | ELECTRICAL STEEL SHEET - An electrical steel sheet has a composition including C: less than 0.010 mass %, Si: 1.5˜10 mass % and the balance being Fe and incidental impurities, wherein a main orientation in a texture of a steel sheet is <111>//ND and an intensity ratio relative to randomly oriented specimen of the main orientation is not less than 5 and, preferably an intensity ratio relative to randomly oriented specimen of {111}<112> orientation is not less than 10, an intensity ratio relative to randomly oriented specimen of {310}<001> orientation is not more than 3 and Si concentration has a gradient that it is high at a side of a surface layer and low at a central portion in the thickness direction and a maximum value of the Si concentration is not less than 5.5 mass % and a difference between maximum and minimum values is not less than 0.5 mass %. | 01-15-2015 |
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20150187473 | METHOD FOR PRODUCING GRAIN-ORIENTED ELECTRICAL STEEL SHEET - A method for producing a grain-oriented electrical steel sheet includes hot rolling a raw steel material containing C: 0.002˜0.10 mass %, Si: 2.0˜8.0 mass % and Mn: 0.005˜1.0 mass % to obtain a hot rolled sheet, subjecting the sheet after or without hot band annealing to one or two or more stage cold rollings including an intermediate annealing to obtain a cold rolled sheet having a final sheet thickness, subjecting the rolled sheet to decarburization annealing and primary recrystallization annealing, applying an annealing separator to the sheet surface and subjecting to a final annealing, when rapid heating is performed at a rate of at least 50° C./s in a range of 200˜700° C. of the decarburization annealing, the rolled sheet is subjected to holding at any temperature of 250˜600° C. for 1˜10 seconds to produce a grain-oriented electrical steel sheet being low in the iron loss and small in the deviation of the iron loss value. | 07-02-2015 |
20150194247 | METHOD FOR PRODUCING GRAIN-ORIENTED ELECTRICAL STEEL SHEET - In a method for producing a grain-oriented electrical steel sheet by hot rolling a steel slab having a chemical composition including C: 0.001˜0.10 mass %, Si: 1.0˜5.0 mass %, Mn: 0.01˜0.5 mass %, Al: less than 0.0100 mass %, each of S, Se, O and N: not more than 0.0050 mass % and the remainder being Fe and inevitable impurities, subjecting the resulting hot rolled sheet to a single cold rolling or two or more cold rollings sandwiching an intermediate annealing therebetween to a final thickness, subjecting to a primary recrystallization annealing, applying an annealing separator thereto and then subjecting to a finish annealing, a zone of 550˜700° C. in a heating process of the primary recrystallization annealing is rapidly heated at an average heating rate of 40˜200° C./s, while any temperature zone of 250˜550° C. is kept at a heating rate of not more than 10° C./s for 1˜10 seconds, whereby secondary recrystallized grains are refined to obtain a grain-oriented electrical steel sheet stably realizing a low iron loss. | 07-09-2015 |