Patent application number | Description | Published |
20120304142 | DESIGN SUPPORT DEVICE OF THREE-DIMENSIONAL INTEGRATED CIRCUIT AND METHOD THEREOF - To provide a design support device of a three-dimensional integrated circuit capable of, in the case where a placement position of a through-via changes in the design phase of a three-dimensional integrated circuit composed of a plurality of semiconductor chips in layers, avoiding change of respective placement positions of other parts as much as possible. A design support device | 11-29-2012 |
20130019214 | THREE-DIMENSIONAL INTEGRATED CIRCUIT DESIGN DEVICE, THREE-DIMENSIONAL INTEGRATED CIRCUIT DESIGN, METHOD, AND PROGRAMAANM Morimoto; TakashiAACI OsakaAACO JPAAGP Morimoto; Takashi Osaka JPAANM Hashimoto; TakashiAACI FukuokaAACO JPAAGP Hashimoto; Takashi Fukuoka JP - A worst-case temperature calculation unit | 01-17-2013 |
20130033303 | INTEGRATED CIRCUIT - An integrated circuit is provided with a substrate, an electrode, two diffusion areas, and a resistance heater. The substrate includes a first surface and second surface that are substantially parallel to each other. The electrode is laminated onto the first surface. The two diffusion areas are disposed within the substrate in the vicinity of the electrode to form one transistor with the electrode. The resistance heater is located on an area of the second surface across the substrate from the electrode. The resistance heater produces heat by allowing electric current to flow. | 02-07-2013 |
20130037965 | THREE-DIMENSIONAL INTEGRATED CIRCUIT, PROCESSOR, SEMICONDUCTOR CHIP, AND MANUFACTURING METHOD OF THREE-DIMENSIONAL INTEGRATED CIRCUIT - One aspect of the present invention is a three-dimensional integrated circuit | 02-14-2013 |
20130089149 | IMAGE DECODING APPARATUS, IMAGE DECODING METHOD, INTEGRATED CIRCUIT, AND PROGRAM - An image decoding device is provided that decodes, without an increase in the circuit size, a coded video sequence including a large-size block. The image decoding apparatus includes: a block division unit which divides a current block that is to be decoded and is included in a picture of the coded video sequence, into sub-blocks; an image obtainment unit which obtains, for each of the sub-blocks, image data corresponding to the sub-block from a recording medium; a prediction unit which generates, for each of the sub-blocks, a predicted image of the sub-block, based on the image data obtained by the image obtainment unit; and a reconstruction unit which reconstructs each of the sub-blocks, by adding the predicted image generated for the sub-block to the sub-block. | 04-11-2013 |
20130121093 | MEMORY ACCESS CONTROL DEVICE AND MANUFACTURING METHOD - A memory access control device including: a bit position information storage unit storing bit position information indicating one or more bit positions in a bit sequence of a predetermined length; a reading unit configured to attempt to read a bit sequence from the range specified by the logical address received by the logical address receiving unit, thereby receiving a first bit sequence from the external memory in units of the predetermined length, the first bit sequence being composed of bits that are larger in number than bits stored in the range specified by the logical address; a bit sequence extracting unit configured to extract one or more bit sequences from the first bit sequence at the one or more bit positions indicated by the bit position information in units of the predetermined length. | 05-16-2013 |
20130127028 | THREE-DIMENSIONAL INTEGRATED CIRCUIT HAVING REDUNDANT RELIEF STRUCTURE FOR CHIP BONDING SECTION - A chip is layered on a rewiring member. A plurality of connecting members and a plurality of redundant connecting members are arranged in the chip, and electrically connect the chip to the rewiring member. Redundant circuits are embedded in each of the rewiring member and the chip. When one of the connecting members is faulty, the redundant circuits cause one of the redundant connecting members to transmit a signal between the rewiring member and the chip, instead of the faulty connecting member. The connecting members have first and second subsets arranged in first and second regions, respectively. A distance between the rewiring member and the chip exceeds a predetermined threshold value in the first region in contrast to the second region. The first subset has a higher proportion of connecting members that the redundant circuits can replace with a subset of the redundant connecting members than the second subset. | 05-23-2013 |
20130135004 | THREE-DIMENSIONAL INTEGRATED CIRCUIT AND TESTING METHOD FOR THE SAME - Each chip in a three-dimensional circuit includes a pair of connections, a test signal generation circuit, and a test result judgment circuit. The connections are electrically connected with an adjacent chip. The test signal generation circuit outputs a test signal to one of the connections. The test result judgment circuit receives a signal from the other of the connections and, from the state of the signal, detects the conducting state of the transmission path for the signal. Before layering the chips, a conductor connects the connections to form a series connection, and the conducting state of each connection is detected from the conducting state of the series connection. After layering the chips, the test signal generation circuit in one chip outputs a test signal, and the test result judgment circuit in another chip receives the test signal, and thus the conducting state of the connections between the chips is tested. | 05-30-2013 |
20140010311 | IMAGE DECODING APPARATUS, IMAGE CODING APPARATUS, IMAGE DECODING CIRCUIT, AND IMAGE DECODING METHOD - A decoding apparatus according to the present invention includes: a decoding unit which decodes identification information identifying an orthogonal transform basis for inverse orthogonal transform; an orthogonal transform basis accumulation unit accumulating orthogonal transform bases for inverse orthogonal transform; an orthogonal transform basis storage unit storing an orthogonal transform basis for inverse transform, from among the stored orthogonal transform bases; an inverse orthogonal transform unit which performs inverse orthogonal transform using the identified orthogonal transform basis; and an orthogonal transform basis transfer control unit which transfers the identified orthogonal transfer basis from the orthogonal transform basis accumulation unit to the orthogonal transfer basis storage unit only when the identified orthogonal transform basis is not yet stored therein. With this structure, it is possible to reduce the memory bandwidth for the memory storing the orthogonal transform basis and the memory access latency. | 01-09-2014 |
20140252606 | INTEGRATED CIRCUIT, MULTICORE PROCESSOR APPARATUS, AND METHOD FOR MANUFACTURING INTEGRATED CIRCUIT - The preferred embodiment of the invention provides a three-dimensional integrated circuit at a suppressed fabrication cost as a whole while a common mask is used for fabricating chips, each of which constitutes the three-dimensional integrated circuit, and especially common area of buffers for bumps is used. The integrated circuit of the invention is an integrated circuit constituted by a plurality of chips laminated, including a first chip and a second chip both having the same layout for through silicon vias. The first chip is connected to a board via one or more first bumps, and further, the through silicon vias in a first number in the chip are connected to one first bump, the first number being a natural number of 2 or more. | 09-11-2014 |