Patent application number | Description | Published |
20100012626 | WIRE ELECTRICAL DISCHARGE MACHINING APPARATUS - A wire electrical discharge machining apparatus includes a unit capable of separately opening and closing each of a high impedance path and a low impedance path, a unit that sets an open/close pattern in which a combination of closing one of the feeding paths and opening another one of the feeding paths is designated for switching power feeding between the high impedance path and the low impedance path, a unit that changes pulse energy per feeding pulse in a present feeding path to reduce a difference in discharge pulse energy applied to an inter-electrode gap from a machining power supply between at a time of high-impedance-path feeding and at a time of low-impedance-path feeding, and a unit that controls opening and closing of the path open/close unit in accordance with the changed open/close pattern. | 01-21-2010 |
20100084378 | WIRE ELECTRICAL DISCHARGE MACHINING APPARATUS - A machining-energy calculating unit accumulates a discharge current value for each discharge position to calculate a machining energy in a certain time period from the present time to the past time. An energy-distribution changing unit determines the presence or absence of imbalance in the energy by obtaining a machining energy distribution in an up-down direction of the machining gap based on the machining energy, and when there is imbalance, the energy-distribution changing unit produces a new open/close pattern in which a machining energy distribution that eliminates the imbalance. Power feeding is then performed based on the new open/close pattern. | 04-08-2010 |
20100224596 | WIRE ELECTRICAL DISCHARGE MACHINING APPARATUS - In a wire electrical discharge machining apparatus, an upper main-discharge power supply is connected between an upper conducting terminal and a workpiece using an upper main-feeder line capable of configuring outward and homeward paths, and a lower main-discharge power supply is connected between a lower conducting terminal and the workpiece using a lower main-feeder line capable of configuring outward and homeward paths. Moreover, a sub-discharge power supply is connected between the upper conducting terminal and the workpiece and between the lower conducting terminal and the workpiece using an upper and a lower sub-feeder lines that have higher impedances than the impedances of the upper and the lower main-feeder lines and can configure outward and homeward paths. | 09-09-2010 |
20100294743 | ELECTRIC DISCHARGE DEVICE - To provide an electric discharge device capable of performing an optimum process that achieves a high-quality process in a satisfactory quality of processing precision and the like. In an electric discharge device that processes a workpiece by electric discharge, a reserve electric-discharge pulse is applied by alternately switching between a positive polarity and a reverse polarity, and a current waveform shape of a main electric-discharge pulse is differentiated corresponding to a polarity of a reserve electric-discharge pulse, to a main electric-discharge pulse to be applied after detecting electric discharge following the reserve electric-discharge pulse. With this arrangement, a processing current shape can be optimized corresponding to an electric discharge characteristic, and thus a high-precision process can be performed. | 11-25-2010 |
20100308017 | ELECTRIC DISCHARGE MACHINING DEVICE - An electric discharge machining device that performs processing by applying a voltage pulse to space between the processing electrode and the workpiece and suitably switching the polarity of the voltage pulse attains both desired processing accuracy and desired controllability. The electric discharge machining device is provided with the first to fourth switching elements. The controlling unit that controls these switching elements, when setting a period time in which the first switching element is turned on, a period of time in which the fourth switching element is in an on-state in the same period, and, when setting a period time in which the second switching element is turned on, a period of time in which the third switching element is in an on-state in the same period so that a desired voltage pulse is applied to the space between the processing electrode and the workpiece. | 12-09-2010 |
20110000889 | ELECTRIC DISCHARGE MACHINING APPARATUS AND ELECTRIC DISCARGE MACHINING METHOD - In a waveform of switching signals, which is output from a full-bridge circuit formed of four switching elements, includes a normal polarity pulse group and a reversed polarity pulse group for controlling an output timing of voltage pulses. A duty cycle of the normal polarity pulse group containing a plurality of normal polarity pulses, which apply a positive power-supply polarity to a workpiece and apply a negative power-supply polarity to a machining-purpose electrode, is configured so as to be different from a duty cycle of the reversed polarity pulse group containing a plurality of reversed polarity pulses, which apply a negative power-supply polarity to the workpiece and apply a positive power-supply polarity to the machining-purpose electrode. | 01-06-2011 |
20140116989 | WIRE ELECTRIC DISCHARGE MACHINING APPARATUS AND COOLING CONTROL DEVICE - The present invention includes a post-cooling temperature sensor that measures a temperature of the machining fluid immediately after being cooled by a cooling device as a post-cooling fluid temperature, and an intra-tank temperature sensor that measures a temperature of the machining fluid in a work tank as an intra-tank fluid temperature, for a cooling control device that controls a fluid temperature of the machining fluid in a wire electric discharge machining apparatus, and the cooling control device has a first temperature-feedback control unit that feeds back the post-cooling fluid temperature into a cooling instruction value as an instruction value for the cooling device, and a second temperature-feedback control unit adjusts the cooling instruction value by feeding back the intra-tank fluid temperature to cause the intra-tank fluid temperature to follow a target temperature. | 05-01-2014 |
20140116990 | ELECTRIC DISCHARGE MACHINING APPARATUS - An electric discharge machining apparatus of the present invention includes a power supply, an electrode gap configured so as to be formed by an electrode and a workpiece, and an earth floating-capacitance current-suppressing coil configured to be inserted between the power supply and the electrode gap. Accordingly, the impedance in the charging path from the power supply to an interelectrode capacitance (an interelectrode parallel capacitor and an interelectrode parallel floating capacitance) can be decreased, and the impedance in the charging path to an earth floating capacitance can be increased, thereby enabling the electric current from the earth floating capacitance during discharge machining to be suppressed. | 05-01-2014 |
Patent application number | Description | Published |
20090037916 | PROCESSOR - The present invention provides a processor that cyclically executes a plurality of threads in accordance with an execution time allocated to each of the threads, comprising a reconfigurable integrated circuit. The processor stores circuit configuration information sets respectively corresponding to the plurality of threads, reconfigures a part of the integrated circuit based on the circuit configuration information sets, and sequentially executes each thread using the integrated circuit that has been reconfigured based on one of the configuration information sets that corresponds to the thread. While executing a given thread, the processor selects a thread to be executed next, and reconfigures a part of the integrated circuit where is not currently used for execution of the given thread, based on a circuit configuration information set corresponding to the selected thread. | 02-05-2009 |
20090051573 | VARIABLE-LENGTH-CODE DECODING DEVICE - A variable-length-code decoding device is operable to decode bit streams encoded in conformity with a plurality of coding systems. The device comprises a decoding unit ( | 02-26-2009 |
20090220009 | IMAGE DECODING DEVICE AND IMAGE DECODING METHOD - An image decoding device ( | 09-03-2009 |
20100100219 | FABRICATION SYSTEM OF SEMICONDUCTOR INTEGRATED CIRCUIT, FABRICATION DEVICE, FABRICATION METHOD, INTEGRATED CIRCUIT AND COMMUNICATION SYSTEM - A manufacturing system which can restrain the margin of a semiconductor integrated circuit. | 04-22-2010 |
20100128801 | IMAGE DECODING DEVICE, IMAGE DECODING SYSTEM, IMAGE DECODING METHOD, AND INTEGRATED CIRCUIT - A segment allocation determination unit | 05-27-2010 |
20100239024 | IMAGE DECODING DEVICE AND IMAGE DECODING METHOD - To decode coded pictures each of which has dependencies within the picture, using conventional decoding circuits and without deteriorating the efficiency in parallel processing. | 09-23-2010 |
20100266049 | IMAGE DECODING DEVICE - An image decoding apparatus pertaining to the present invention includes a plurality of decoders. The image decoding apparatus (i) divides image data to decode into a plurality of pieces of partial data, (ii) acquires attribute information pieces each affecting decoding processing time of a corresponding one of the plurality of pieces of partial data, (iii) determines which of the plurality of decoders is caused to decode which of the plurality of pieces of partial data based on the attribute information pieces on the plurality of pieces of partial data and (iv) causes two or more of the plurality of decoders to decode two or more corresponding pieces of the partial data in parallel. | 10-21-2010 |
20110131442 | TRACING APPARATUS AND TRACING SYSTEM - A tracing apparatus for tracing operational information that is output from a plurality of processing units in relation to data processing operations, the tracing apparatus comprising for each of the processing units: a counting unit configured to obtain and output a counter value for the corresponding processing unit, the counter value obtained by counting clock signals that are input to the processing unit at an operating frequency thereof; a counter value conversion unit configured to obtain and output a converted counter value for the corresponding processing unit, the converted counter value obtained by converting the counter value based on the assumption that the processing unit has a given reference operating frequency; and an adding unit configured to acquire an operational information set from the corresponding processing unit, and to add the converted counter value to the operational information set. | 06-02-2011 |
20110135285 | IMAGE CODING APPARATUS, METHOD, INTEGRATED CIRCUIT, AND PROGRAM - An image coding apparatus ( | 06-09-2011 |
20110138092 | ARBITRATION DEVICE, ARBITRATION SYSTEM, ARBITRATION METHOD, SEMICONDUCTOR INTEGRATED CIRCUIT, AND IMAGE PROCESSING DEVICE - Provided is a hierarchical arbitration device wherein an arbitration device at each level of the hierarchy selects a resource use request having the highest priority and a resource use request having the second highest priority, outputting these two resource use requests to the arbitration device that is one level higher. After outputting the memory use request having the highest priority to a resource control unit as the top priority resource use request, when the arbitration device at the highest level of the hierarchy receives a signal from the memory control unit indicating receipt of the resource use request, the arbitration device then selects the resource use request having the second highest priority and outputs this resource request as the next top priority resource use request. | 06-09-2011 |
20110235716 | DECODING APPARATUS, DECODING METHOD, PROGRAM AND INTEGRATED CIRCUIT - A decoding apparatus ( | 09-29-2011 |
20120063693 | IMAGE DECODING DEVICE, IMAGE ENCODING DEVICE, IMAGE DECODING CIRCUIT, AND IMAGE DECODING METHOD - A decoding apparatus ( | 03-15-2012 |
20120147959 | MOVING IMAGE DECODING APPARATUS, MOVING IMAGE CODING APPARATUS, MOVING IMAGE DECODING CIRCUIT, AND MOVING IMAGE DECODING METHOD - A moving image decoding apparatus which enables reduction in the memory bandwidth and the memory access latency for the motion compensation filter coefficients for use in inter-picture prediction involving motion compensation using variable coefficients includes: a decoding unit ( | 06-14-2012 |
Patent application number | Description | Published |
20100114479 | POSITION INFORMATION DETECTING APPARATUS, POSITION INFORMATION DETECTING METHOD, POSITION INFORMATION DETECTING PROGRAM AND STORAGE MEDIUM - The position information detecting apparatus obtains pinpoint information which coincides with the first address part of the inputted address information, and thereafter detects the pinpoint information which coincides with the second address part inputted. If the position information detecting apparatus can detect the pinpoint information, it determines the position information included in the detected pinpoint information as the detection-object position information. If the position information detecting apparatus cannot detect the pinpoint information, it searches for the range information which coincides with the first address part of the inputted address information. Then, the position information detecting apparatus estimates the position information corresponding to the inputted address information by using the searched range information and the searched pinpoint information. | 05-06-2010 |
20110167065 | DATA GENERATING APPARATUS, INFORMATION PROCESSING APPARATUS, DATA GENERATING METHOD, INFORMATION PROCESSING METHOD, DATA GENERATING PROGRAM INFORMATION PROCESSING PROGRAM AND RECORDING MEDIUM - A data generating apparatus includes an acquiring unit that acquires text data (name data) related to a name associated with position information; a classifying unit that using the acquired position data, classifies the name data according to given regions; an integrating unit that integrates neighboring regions such that the total data size of the name data included in regions to be integrated does not exceed a predetermined given data size; a storage unit that groups the name data according to integrated regions and stores the grouped name data as a name dictionary to be used in both a facility search process and a map display process; and an extracting unit that from the classified name data, extracts the name data common to regions of a given number or more, where the storage unit groups and stores the common name data as a common name dictionary different from the name dictionary. | 07-07-2011 |
20120041678 | POSITION INFORMATION DETECTING APPARATUS, POSITION INFORMATION DETECTING METHOD, POSITION INFORMATION DETECTING PROGRAM AND STORAGE MEDIUM - The position information detecting apparatus obtains pinpoint information which coincides with the first address part of the inputted address information, and thereafter detects the pinpoint information which coincides with the second address part inputted. If the position information detecting apparatus can detect the pinpoint information, it determines the position information included in the detected pinpoint information as the detection-object position information. If the position information detecting apparatus cannot detect the pinpoint information, it searches for the range information which coincides with the first address part of the inputted address information. Then, the position information detecting apparatus estimates the position information corresponding to the inputted address information by using the searched range information and the searched pinpoint information. | 02-16-2012 |
Patent application number | Description | Published |
20120304142 | DESIGN SUPPORT DEVICE OF THREE-DIMENSIONAL INTEGRATED CIRCUIT AND METHOD THEREOF - To provide a design support device of a three-dimensional integrated circuit capable of, in the case where a placement position of a through-via changes in the design phase of a three-dimensional integrated circuit composed of a plurality of semiconductor chips in layers, avoiding change of respective placement positions of other parts as much as possible. A design support device | 11-29-2012 |
20130019214 | THREE-DIMENSIONAL INTEGRATED CIRCUIT DESIGN DEVICE, THREE-DIMENSIONAL INTEGRATED CIRCUIT DESIGN, METHOD, AND PROGRAMAANM Morimoto; TakashiAACI OsakaAACO JPAAGP Morimoto; Takashi Osaka JPAANM Hashimoto; TakashiAACI FukuokaAACO JPAAGP Hashimoto; Takashi Fukuoka JP - A worst-case temperature calculation unit | 01-17-2013 |
20130033303 | INTEGRATED CIRCUIT - An integrated circuit is provided with a substrate, an electrode, two diffusion areas, and a resistance heater. The substrate includes a first surface and second surface that are substantially parallel to each other. The electrode is laminated onto the first surface. The two diffusion areas are disposed within the substrate in the vicinity of the electrode to form one transistor with the electrode. The resistance heater is located on an area of the second surface across the substrate from the electrode. The resistance heater produces heat by allowing electric current to flow. | 02-07-2013 |
20130037965 | THREE-DIMENSIONAL INTEGRATED CIRCUIT, PROCESSOR, SEMICONDUCTOR CHIP, AND MANUFACTURING METHOD OF THREE-DIMENSIONAL INTEGRATED CIRCUIT - One aspect of the present invention is a three-dimensional integrated circuit | 02-14-2013 |
20130089149 | IMAGE DECODING APPARATUS, IMAGE DECODING METHOD, INTEGRATED CIRCUIT, AND PROGRAM - An image decoding device is provided that decodes, without an increase in the circuit size, a coded video sequence including a large-size block. The image decoding apparatus includes: a block division unit which divides a current block that is to be decoded and is included in a picture of the coded video sequence, into sub-blocks; an image obtainment unit which obtains, for each of the sub-blocks, image data corresponding to the sub-block from a recording medium; a prediction unit which generates, for each of the sub-blocks, a predicted image of the sub-block, based on the image data obtained by the image obtainment unit; and a reconstruction unit which reconstructs each of the sub-blocks, by adding the predicted image generated for the sub-block to the sub-block. | 04-11-2013 |
20130121093 | MEMORY ACCESS CONTROL DEVICE AND MANUFACTURING METHOD - A memory access control device including: a bit position information storage unit storing bit position information indicating one or more bit positions in a bit sequence of a predetermined length; a reading unit configured to attempt to read a bit sequence from the range specified by the logical address received by the logical address receiving unit, thereby receiving a first bit sequence from the external memory in units of the predetermined length, the first bit sequence being composed of bits that are larger in number than bits stored in the range specified by the logical address; a bit sequence extracting unit configured to extract one or more bit sequences from the first bit sequence at the one or more bit positions indicated by the bit position information in units of the predetermined length. | 05-16-2013 |
20130127028 | THREE-DIMENSIONAL INTEGRATED CIRCUIT HAVING REDUNDANT RELIEF STRUCTURE FOR CHIP BONDING SECTION - A chip is layered on a rewiring member. A plurality of connecting members and a plurality of redundant connecting members are arranged in the chip, and electrically connect the chip to the rewiring member. Redundant circuits are embedded in each of the rewiring member and the chip. When one of the connecting members is faulty, the redundant circuits cause one of the redundant connecting members to transmit a signal between the rewiring member and the chip, instead of the faulty connecting member. The connecting members have first and second subsets arranged in first and second regions, respectively. A distance between the rewiring member and the chip exceeds a predetermined threshold value in the first region in contrast to the second region. The first subset has a higher proportion of connecting members that the redundant circuits can replace with a subset of the redundant connecting members than the second subset. | 05-23-2013 |
20130135004 | THREE-DIMENSIONAL INTEGRATED CIRCUIT AND TESTING METHOD FOR THE SAME - Each chip in a three-dimensional circuit includes a pair of connections, a test signal generation circuit, and a test result judgment circuit. The connections are electrically connected with an adjacent chip. The test signal generation circuit outputs a test signal to one of the connections. The test result judgment circuit receives a signal from the other of the connections and, from the state of the signal, detects the conducting state of the transmission path for the signal. Before layering the chips, a conductor connects the connections to form a series connection, and the conducting state of each connection is detected from the conducting state of the series connection. After layering the chips, the test signal generation circuit in one chip outputs a test signal, and the test result judgment circuit in another chip receives the test signal, and thus the conducting state of the connections between the chips is tested. | 05-30-2013 |
20140010311 | IMAGE DECODING APPARATUS, IMAGE CODING APPARATUS, IMAGE DECODING CIRCUIT, AND IMAGE DECODING METHOD - A decoding apparatus according to the present invention includes: a decoding unit which decodes identification information identifying an orthogonal transform basis for inverse orthogonal transform; an orthogonal transform basis accumulation unit accumulating orthogonal transform bases for inverse orthogonal transform; an orthogonal transform basis storage unit storing an orthogonal transform basis for inverse transform, from among the stored orthogonal transform bases; an inverse orthogonal transform unit which performs inverse orthogonal transform using the identified orthogonal transform basis; and an orthogonal transform basis transfer control unit which transfers the identified orthogonal transfer basis from the orthogonal transform basis accumulation unit to the orthogonal transfer basis storage unit only when the identified orthogonal transform basis is not yet stored therein. With this structure, it is possible to reduce the memory bandwidth for the memory storing the orthogonal transform basis and the memory access latency. | 01-09-2014 |
20140252606 | INTEGRATED CIRCUIT, MULTICORE PROCESSOR APPARATUS, AND METHOD FOR MANUFACTURING INTEGRATED CIRCUIT - The preferred embodiment of the invention provides a three-dimensional integrated circuit at a suppressed fabrication cost as a whole while a common mask is used for fabricating chips, each of which constitutes the three-dimensional integrated circuit, and especially common area of buffers for bumps is used. The integrated circuit of the invention is an integrated circuit constituted by a plurality of chips laminated, including a first chip and a second chip both having the same layout for through silicon vias. The first chip is connected to a board via one or more first bumps, and further, the through silicon vias in a first number in the chip are connected to one first bump, the first number being a natural number of 2 or more. | 09-11-2014 |