| Patent application number | Description | Published |
|---|
| 20080288967 | PROCEDURE CALLING METHOD, PROCEDURE CALLING PROGRAM, AND COMPUTER PRODUCT - In a shared-memory multiprocessor having plural processors that share a shared memory, each have an address space that is respectively independent in the shared memory and are configured to be capable of inter-processor communication using a bus, a first processor makes a procedure call to a second processor by specifying an address in the address space of the second processor. In response to the procedure call, by initiating and executing the procedure located at the address specified by the first processor, the second processor initiates the procedure at a high speed. | 11-20-2008 |
| 20090019259 | MULTIPROCESSING METHOD AND MULTIPROCESSOR SYSTEM - A multiprocessing method and a multiprocessor system capable of reducing time lost due to sequential waiting when procedures (program units) having dependencies are executed in which an order of execution of a plurality of program units in a sequential execution program and dependencies of the plurality of program units are registered, the execution states of the plurality of program units are managed based on the registered dependencies, executable program units are determined, and are assigned to server processors sequentially and executed are disclosed. | 01-15-2009 |
| 20100070739 | Multiprocessor system and control method thereof - A multiprocessor system according to an embodiment comprises a plurality of processors, an execution control unit to control processing by the plurality of processors and data transfer between the plurality of processors; and an internal data storage unit to store data dependence information indicating status of the data transfer. If control flow of processing by a processor is fixed after a preceding data transfer is registered for execution and another data transfer to a similar destination as the preceding data transfer is necessary, the execution control unit cancels the preceding data transfer based on the data dependence information. | 03-18-2010 |
| 20100107174 | SCHEDULER, PROCESSOR SYSTEM, AND PROGRAM GENERATION METHOD - A scheduler for conducting scheduling for a processor system including a plurality of processor cores and a plurality of memories respectively corresponding to the plurality of processor cores includes: a scheduling section that allocates one of the plurality of processor cores to one of a plurality of process requests corresponding to a process group based on rule information; and a rule changing section that, when a first processor core is allocated to a first process of the process group, changes the rule information and allocates the first processor core to a subsequent process of the process group, and that restores the rule information when a second processor core is allocated to a final process of the process group. | 04-29-2010 |
| 20110078378 | METHOD FOR GENERATING PROGRAM AND METHOD FOR OPERATING SYSTEM - An information processing apparatus sequentially selects a function whose execution frequency is high as a selected function that is to be stored in an internal memory, in a source program having a hierarchy structure. The information processing apparatus allocates the selected function to a memory area of the internal memory, allocates a function that is not the selected function and is called from the selected function to an area close to the memory area of the internal memory, and generates an internal load module. The information processing apparatus allocates a remaining function to an external memory coupled to a processor and generates an external load module. Then, a program executed by the processor having the internal memory is generated. By allocating the function with a high execution frequency to the internal memory, it is possible to execute the program at high speed, which may improve performance of a system. | 03-31-2011 |
| 20120088485 | INFORMATION PROCESSING SYSTEM, APPARATUS, AND METHOD - An information processing system includes a first apparatus including a position information transmission unit to transmit information on the position of the first apparatus; and a second apparatus including, a position information acquisition unit to acquire a position of the second apparatus; a position information receiving unit to receive the information on the position of the first apparatus; a relative-position information acquisition unit to acquire relative-position information of the second and the first apparatus on the basis of the information on the position of the second and the first apparatus; and a control unit to control a coupling mode of the second and the first apparatus on the basis of the relative-position information. | 04-12-2012 |
| 20130007490 | MULTICORE PROCESSOR SYSTEM, POWER CONTROL METHOD, AND COMPUTER PRODUCT - A multicore processor system having multiple cores, includes processors configured to measure bandwidth of a network; compare the measured bandwidth and a given threshold; determine among the cores and based on an obtained comparison result, a core adjustment number by which the number of cores executing a given process related to data communicated through the network is adjusted; calculate the number of executing cores after adjustment by the core adjustment number and based on the number of cores executing the given process before the adjustment and the determined core adjustment number; specify a core executing the given process among the cores and based on the calculated number of executing cores after the adjustment; and distribute the communicated data to the specified core executing the given process. | 01-03-2013 |
| 20130007765 | SOFTWARE CONTROL DEVICE, SOFTWARE CONTROL METHOD, AND COMPUTER PRODUCT - A software control device includes a processor configured to determine whether starting software and running software are accessing the same common resource; and control the running software to be temporarily suspended upon determining that the starting software and the running software are accessing the same common resource. | 01-03-2013 |
| 20130013892 | HIERARCHICAL MULTI-CORE PROCESSOR, MULTI-CORE PROCESSOR SYSTEM, AND COMPUTER PRODUCT - A hierarchical multi-core processor includes a core group for each hierarchy of a hierarchy group constituting a series of communication functions divided according to communication protocol, where a first core group of a given hierarchy among the hierarchy group is connected to a second core group of another hierarchy constituting a first communication function to be executed following a second communication function of the given hierarchy. | 01-10-2013 |
| 20130024589 | MULTI-CORE PROCESSOR SYSTEM, COMPUTER PRODUCT, AND CONTROL METHOD - A multi-core processor system includes a given configured to queue an interrupt process of a software interrupt request to the given core, and execute queued processes in the order of queuing at the given core; execute preferentially an interrupt process of a hardware interrupt request to the given core over a process under execution at the given core; determine whether the software interrupt request is a specific software interrupt request; and perform control to preferentially execute the interrupt process without queuing, upon determining that the software interrupt request is the specific software interrupt request. | 01-24-2013 |
| 20130047021 | MULTIPLE-CORE PROCESSOR SYSTEM, COMPUTER PRODUCT, AND CONTROL METHOD - A multiple-core processor system includes a memory unit storing the number of time intervals within a time bin, a time interval being a time interval between two consecutive operations; and a processor configured to: update the number of time intervals, specify a time stretch during which the number of time intervals stays above a threshold, and set, based on the number of time intervals, a power supply mode in which the multiple-core processor is supplied with power. | 02-21-2013 |
| 20130060974 | DATA TRANSFERRING APPARATUS AND DATA TRANSFERRING METHOD - A memory stores data generated by a processor and a transferring unit burst transfers the data from the memory unit to a processing unit. Based on an access capability of the processor when accessing the memory, a prescribed value for a burst width and information concerning the time that the processing unit consumes to process the data are set in advance at the data transferring apparatus. When the transferring unit performs data transfer, the time allowed for data transfer is calculated based on the information concerning the time that the processing unit consumes to process the data, and the burst width is determined as a value greater than or equal to the prescribed value for the burst width and is as close as possible to the prescribed value for the burst width within a range in which data transfer can be finished within the allowed time. | 03-07-2013 |
| 20130097384 | MULTI-CORE PROCESSOR SYSTEM, CACHE COHERENCY CONTROL METHOD, AND COMPUTER PRODUCT - A multi-core processor system includes a processor configured to establish coherency of shared data values stored in a cache memory accessed by a multiple cores; detect a first thread executed by a first core among the cores; identify upon detecting the first thread, a second thread under execution by a second core other than the first core and among the cores; determine whether shared data commonly accessed by the first thread and the second thread is present; and stop establishment of coherency for a first cache memory corresponding to the first core and a second cache memory corresponding to the second core, upon determining that no shared data commonly accessed is present. | 04-18-2013 |
| 20130097389 | MEMORY ACCESS CONTROLLER, MULTI-CORE PROCESSOR SYSTEM, MEMORY ACCESS CONTROL METHOD, AND COMPUTER PRODUCT - A memory access controller includes a semiconductor circuit configured to classify into a first group of cores having made an exclusive access request to shared memory and a second group of cores not having made an exclusive access request to the shared memory, multiple cores capable of accessing the shared memory; detect a core having completed the exclusive access among the first group of cores; and send to a core among the first group of cores and standing by for the exclusive access, a notification of release from a standby state, when detecting a core having completed the exclusive access. | 04-18-2013 |
| 20130097441 | MULTI-CORE PROCESSOR SYSTEM, POWER CONTROL METHOD, AND COMPUTER PRODUCT - A multi-core processor system includes a core configured to detect among multiple cores, a state of migration of first software from a first core to the core whose specific processing capacity value is lower than that of the first core; and set the processing capacity value of the first core at a time of the detection to be a processing capacity value that is lower than that before the migration when detecting the state of migration. | 04-18-2013 |
| 20130111078 | DATA TRANSFER CONTROL APPARATUS, DATA TRANSFER CONTROL METHOD, AND COMPUTER PRODUCT | 05-02-2013 |
| 20130111138 | MULTI-CORE PROCESSOR SYSTEM, COMPUTER PRODUCT, AND CONTROL METHOD | 05-02-2013 |
| 20130111158 | MULTI-CORE PROCESSOR SYSTEM, CONTROL PROGRAM, AND CONTROL METHOD | 05-02-2013 |
| 20130117347 | COMMUNICATION APPARATUS, COMMUNICATION METHOD, AND COMPUTER PRODUCT - A communication apparatus includes a processor configured to access memory of the communication apparatus; communicate with a second apparatus; detect an access request generated by the communication apparatus; determine whether an address of access targeted data indicated in the detected access request is an address allocated to the memory of the communication apparatus; and perform control for selecting and executing based on a determination result, any one among a process of accessing the memory of the communication apparatus based on the access request and a process of communicating with the second apparatus based on the access request. | 05-09-2013 |
| 20130117754 | MULTI-CORE SYSTEM AND SCHEDULING METHOD - A multi-core system includes multiple processor cores; a bus connected to the processor cores; multiple peripheral devices accessed by the processor cores via the bus; profile information including information concerning access of the peripheral devices by each task assigned to the processor cores; a monitor that based on the profile information, monitors access requests to the peripheral devices from tasks under execution at the processor cores and prohibits an access request that causes contention at the bus; and a scheduler that when the monitor prohibits an access request that causes contention at the bus, switches to a different task. | 05-09-2013 |
| 20130117762 | INFORMATION PROCESSING APPARATUS, INFORMATION PROCESSING METHOD, AND COMPUTER PRODUCT - An information processing apparatus includes a processor that is configured to detect a changeover request in a first mode in which a first OS executes a process that includes a second OS different from the first OS; and change the first mode over to a second mode in which the second OS executes a process that includes the first OS, upon detecting the changeover request. | 05-09-2013 |
| 20130117765 | MULTICORE PROCESSOR SYSTEM, COMMUNICATION CONTROL METHOD, AND COMMUNICATION COMPUTER PRODUCT - A multicore processor system is configured to cause among multiple cores, a second core to acquire from a first core that executes a first process, an execution request for a second process and a remaining period from a time of execution of the execution request until an estimated time of completion of the first process; and give notification of a result of the second process from the second core to the first core after an estimated completion time of the first process obtained by adding the remaining period to a start time of the second process. | 05-09-2013 |
| 20130124804 | DATA RESTORATION PROGRAM, DATA RESTORATION APPARATUS, AND DATA RESTORATION METHOD - A computer-readable recording medium stores a program that causes a computer capable of accessing a multicore processor equipped with volatile memories and a plurality of cores accessing the volatile memories, to execute a data restoration process. The data restoration process includes detecting a suspend instruction to any one of the cores in the multicore processor; and restoring, when the suspend instruction is detected, data stored in a volatile memory accessed by a core receiving the suspend instruction, the data being restored in a shared memory accessed by the cores in operation and based on parity data stored in the volatile memories accessed by the cores in operation other than the core receiving the suspend instruction. | 05-16-2013 |
| 20130125131 | MULTI-CORE PROCESSOR SYSTEM, THREAD CONTROL METHOD, AND COMPUTER PRODUCT - A multi-core processor system includes a first core configured to detect a state where a first thread that is allocated to a first core and a second thread that is allocated to a second core access a common resource; calculate, upon detecting the state and based on a first cycle for the first thread to be allocated to the first core and a second cycle for the second thread to be allocated to the second core, a contention cycle for the first and the second threads to cause access contention for the resource; and select a thread allocated at a time before or after the contention cycle of a core to which a given thread that is either the first or the second thread is allocated at the contention cycle; and a second core configured to switch the times at which the given thread and the selected thread are allocated. | 05-16-2013 |
| 20130132708 | MULTI-CORE PROCESSOR SYSTEM, COMPUTER PRODUCT, AND CONTROL METHOD - A multi-core processor system includes a first core that is of a multi-core processor and configured to detect preprocessing for access of shared resources by a second core that is of the multi-core processor excluding the first core, when the first core is accessing the shared resources shared by the multi-core processor; and switch a task being executed by the second core to another task upon detecting the preprocessing. | 05-23-2013 |
| 20130138849 | MULTICORE PROCESSOR SYSTEM, COMPUTER PRODUCT, ASSIGNING METHOD, AND CONTROL METHOD - A multicore processor system includes core configured to detect a process assignment instruction; acquire a remaining time obtained by subtracting a processing time of interrupt processing assigned to an arbitrary core of a multicore processor from a period that is from a calling time of the interrupt processing to an execution time limit of the interrupt processing, upon detecting the process assignment instruction; judge if the remaining time acquired at the acquiring is greater than or equal to a processing time of processing defined to limit an interrupt in the process; and assign the process to the arbitrary core, upon judging that the remaining time is greater than or equal to the processing time of the processing defined to limit an interrupt in the process. | 05-30-2013 |
| 20130138850 | INTERRUPT CONTROL METHOD AND MULTICORE PROCESSOR SYSTEM - In an interrupt control method of a multicore processor system including cores, a cache coherency mechanism, and a device, a first core detecting an interrupt signal from the device writes into an area prescribing an interrupt flag in the cache memory of the first core, first data indicating detection of the interrupt signal, and notifies the other cores of an execution request for interrupt processing corresponding to the interrupt signal, consequent to the cache coherency mechanism establishing coherency among at least cache memories of the other cores when the first data is written; and a second core different from the first core, maintaining the first data written as the interrupt flag, and notified of the execution request executes the interrupt processing, and writes over the area prescribing the interrupt flag written in the cache memory of the second core, with second data indicating no-detection of the interrupt signal. | 05-30-2013 |
| 20130138886 | SCHEDULER, MULTI-CORE PROCESSOR SYSTEM, AND SCHEDULING METHOD - A scheduler that causes a given core in a multi-core processor to determine if a priority level of a process that is to be executed by a core of the multi-core processor is greater than or equal to a threshold; save to a cache memory of each core that executes a process having a priority level greater than or equal to the threshold, data that is accessed by the process upon execution; save to a memory area different from the cache memory and to which access is relatively slower, data that is accessed by a process having a priority level not greater than or equal to the threshold; and save the data saved in the memory area, to a cache memory of a requesting core, when the requesting core issues an access request for the data saved in the memory area. | 05-30-2013 |
| 20130151882 | COMPUTER PRODUCT, CONTROL APPARATUS, AND CONTROL METHOD - A computer-readable recording medium stores a control program causing a processor of a first terminal to execute a process that includes detecting that a remaining battery level of the first terminal has become less than or equal to a first threshold while a task is under execution by the first terminal; suspending execution of the task upon detecting that the remaining battery level of the first terminal has become less than or equal to the first threshold; transmitting identification information of the task to a second terminal upon detecting that the remaining battery level of the first terminal has become less than or equal to the first threshold; receiving from the second terminal and after transmitting the identification information of the task, information related to a potential of executing the task; and transmitting to the second terminal, information corresponding to the information related to the potential of executing the task. | 06-13-2013 |
| 20130159397 | COMPUTER PRODUCT, INFORMATION PROCESSING APPARATUS, AND PARALLEL PROCESSING CONTROL METHOD - A computer-readable recording medium stores a parallel processing control program that causes a connection origin processor to execute a process. The process includes measuring a band between the connection origin apparatus and a connection destination apparatus; calculating, based on the measured band, an execution time period for each execution object for which parallel processing is executable by the connection origin processor in the connection origin apparatus and a connection destination processor in the connection destination apparatus, the execution objects having granularities of the parallel processing that differ from each other; selecting from among the execution objects and based on a length of each calculated execution time period, an execution object to be executed; and setting the selected execution object to be executable by the connection origin processor and the connection destination processor in cooperation with each other. | 06-20-2013 |
| 20130160023 | SCHEDULER, MULTI-CORE PROCESSOR SYSTEM, AND SCHEDULING METHOD - In an embodiment, a scheduler coordinates timings at which cores execute processes, for any two sequential processes to consecutively be executable. The processes are executed in order scheduled by the scheduler by concentrating on a specific core processes obstructing the consecutive execution such as an external interrupt and an internal interrupt. The scheduler does not always cause processes of another application to be executed during all standby time periods while the scheduler determines whether a length of a standby time period is shorter than a predetermined value, and does not cause any process of the other application to be executed when the length is shorter than that. | 06-20-2013 |
| 20130179666 | MULTI-CORE PROCESSOR SYSTEM, SYNCHRONIZATION CONTROL SYSTEM, SYNCHRONIZATION CONTROL APPARATUS, INFORMATION GENERATING METHOD, AND COMPUTER PRODUCT - A multi-core processor system includes a given core that includes a detecting unit that detects migration of a thread under execution by a synchronization source core to a synchronization destination core in the multi-core processor; an identifying unit that refers to a table identifying a combination of a thread and a register associated with the thread, and identifies a particular register corresponding to the thread for which migration was detected; a generating unit that generates synchronization control information identifying the synchronization destination core and the particular register; and a synchronization controller that, communicably connected to the multi-core processor, acquires from the given core, the synchronization control information, reads in from the particular register of the synchronization source core, a value of the particular register obtainable from the synchronization control information, and writes to the particular register of the synchronization destination core, the value. | 07-11-2013 |
| 20130185521 | MULTIPROCESSOR SYSTEM AND SCHEDULING METHOD - A multiprocessor system includes a master processor, at least one slave processor, and a synchronization unit. The master processor has a first flag indicating whether the master processor is in a task activation accepting state and a second flag reflective of a flag of a slave processor, iteratively updates the first flag at a frequency based on the volume of tasks processed by the master processor, and activates a task on the master processor or the slave processor based on the first flag and the second flag. Each slave processor has a third flag indicating whether the slave processor is in the task activation accepting state and iteratively updates the third flag at a frequency based on the volume of tasks processed by the slave processor. Tasks are allocated to the slave processor by the master processor. The synchronization unit synchronizes the third flag and the second flag. | 07-18-2013 |
| 20130198270 | DATA SHARING SYSTEM, TERMINAL, AND DATA SHARING METHOD - A data sharing system includes communicable terminals and selects a server-client system in which a first terminal is designated as a server and other terminals are designated as clients, when a sum of estimated time for transferring data to the first terminal from the other terminals, estimated time for performing, by the first terminal, arithmetic processing of the data in the first terminal, and estimated time for transferring arithmetically processed data from the first terminal to the other terminals satisfies a real time restriction, and power estimated to be consumed at a time of performing, by the first terminal, the arithmetic processing of the data in the first terminal is less than power estimated to be consumed at a time of performing the arithmetic processing by the other terminals. The data sharing system selects a peer-to-peer system, when the sum does not satisfy the real time restriction in any terminal. | 08-01-2013 |
| 20130198390 | COMPUTER PRODUCT, TERMINAL, SERVER, DATA SHARING METHOD, AND DATA DISTRIBUTION METHOD - A computer-readable recording medium stores a data sharing program that causes a processor of a first terminal to execute a process that includes detecting a communication bandwidth used between the first terminal and a second terminal that are communicably connected in an ad-hoc network; comparing the detected communication bandwidth and a bandwidth related to a storage apparatus of the first terminal; determining an operation scheme related to data sharing of data in the storage apparatus of the first terminal and data in a storage apparatus of the second terminal, based on a comparison result obtained at the comparing; notifying the second terminal of the determined operation scheme; and executing a mounting process that enables access of the storage apparatus of the first terminal by the second terminal, based on the determined operation scheme. | 08-01-2013 |
| 20130227579 | INFORMATION PROCESSING APPARATUS, COMPUTER PRODUCT, AND INFORMATION PROCESSING METHOD - An information processing apparatus includes a computer configured to set respectively a storage location for each value of a common variable among threads of a thread group having write requests to write the values of the common variable of the threads in a given process, from a specific storage location defined in the write requests, to the storage locations respectively set for the threads; store, for each thread of the thread group, a value of the common variable to the storage location set for the thread; and read out in order of execution of the threads of the thread group defined in the given process and when all the threads in the thread group have ended, each value of the common variable stored at the first storing, and in the order of execution, overwrite a value in the specific storage location with each read value of the common variable. | 08-29-2013 |
| 20130238882 | MULTI-CORE PROCESSOR SYSTEM, MONITORING CONTROL METHOD, AND COMPUTER PRODUCT - A multi-core processor system includes a given core among multiple cores, wherein the given core is configured to detect execution of a process by the cores; and generate upon detecting the execution of the process, a specific thread that saves state information indicating an executed state of the process and an executed state of each thread to be monitored of the process. | 09-12-2013 |
| 20130246670 | INFORMATION PROCESSING SYSTEM - An information processing system includes a CPU that is connected to a bus; a device that is connected to the bus; a memory that is accessed by the CPU or the device; and a power mode control circuit that sets a power consumption mode. The power mode control circuit sets the power consumption mode based on first information that indicates a cache hit or a cache miss of a cache memory in the CPU and second information that indicates an activated state or a non-activated state of the device. | 09-19-2013 |
| 20130254598 | ACCESS METHOD AND MULTI-CORE PROCESSOR SYSTEM - An access method is executed by a multi-core processor system. The access method includes activating a driver that corresponds to a first CPU, based on a start of execution of a first application; starting measurement of an access time period, based on access of a peripheral device; outputting, when the access time period exceeds a predetermined time period, a detection signal to reset the driver; and prohibiting, when the access time period exceeds a predetermined time period, writing into a register retaining data to be written into the peripheral device from the first CPU. | 09-26-2013 |
| 20130262905 | INFORMATION PROCESSING APPARATUS, COMPUTER PRODUCT, AND INFORMATION PROCESSING METHOD - An information processing apparatus includes a processor configured to detect an unexecuted first thread and an unexecuted second thread; calculate standby power consumption of the first thread in a case of executing the second thread followed by the first thread, based on an execution period of the second thread and standby power consumption per unit time of the first thread; calculate standby power consumption of the second thread in a case of executing the first thread followed by the second thread, based on an execution period of the first thread and standby power consumption per unit time of the second thread; and determine an order of execution of the first thread and the second thread, based on comparison of the standby power consumption of first thread and the standby power consumption of the second thread. | 10-03-2013 |
| 20130275790 | MULTICORE PROCESSOR SYSTEM AND POWER CONTROL METHOD - A multicore processor system includes multiple processors; a device; a memory that stores information of voltage and clock frequency for minimizing power consumption in connection with a number of the processors accessing to the device; and a power control unit that controls the voltage and the clock frequency of the processors on the basis of the information stored in the memory if the number of the processors accessing to the device changes. | 10-17-2013 |
| 20130275996 | SYNCHRONIZATION METHOD - A synchronization method of multiple threads is executed by a computer. The synchronization method includes determining a type of a synchronization process of a first thread performing the synchronization process for synchronization with a second thread; starting time measurement when the type of the synchronization process of the first thread is a first type; performing the synchronization process of the first thread and a synchronization process of the second thread based on a synchronization process history of the second thread when the measured time exceeds a permitted response period of the first thread; and updating the permitted response period and performing the synchronization processes of the first thread and the second thread based on the synchronization process history of the second thread, when another processing request is received. | 10-17-2013 |
| 20130297888 | SCHEDULING METHOD AND MULTI-CORE PROCESSOR SYSTEM - A scheduling method of a scheduler that manages threads is executed by a computer. The scheduling method includes selecting a CPU of relatively less load, when a second thread is generated from a first thread to be processed; determining whether the second thread operates exclusively from the first thread; copying a first storage area assessed by the first thread onto a second storage area managed by the CPU, when the second thread operates exclusively; calculating based on an address of the second storage area and a predetermined value, an offset for a second address for the second thread to access the first storage area; and notifying the CPU of the offset for the second address to convert a first address to a third address for accessing the second storage area. | 11-07-2013 |
| 20130298132 | MULTI-CORE PROCESSOR SYSTEM AND SCHEDULING METHOD - A multi-core processor system includes plural processors; and a scheduler that assigns applications to the processors. The scheduler upon receiving a startup request for a given application and based on start times of the applications executed by the processors, selects a processor that is to execute the given application. | 11-07-2013 |
| 20130298137 | MULTI-TASK SCHEDULING METHOD AND MULTI-CORE PROCESSOR SYSTEM - A multi-task scheduling method includes assigning a first thread to a first processor; detecting a second thread that is executed after the first thread; calculating based on a load of a processor that is assigned a third thread that generates the second thread, a first time that lasts until a start of the second thread; calculating a second time that lasts until completion of execution of the first thread; and changing a first time slice of the first processor to a second time slice when the second time is greater than the first time. | 11-07-2013 |
| 20130303221 | SCHEDULING METHOD - A scheduling method includes acquiring first information, second information, and third information from a first terminal located in a service area of a first base station; determining based on the first information, the second information, and the third information, whether a first process assigned to the first terminal is to be collected; and assigning the first process to a second terminal located in the service area of the first base station, when at the determining the first process is determined to be collected. | 11-14-2013 |
| 20130305257 | SCHEDULING METHOD AND SCHEDULING SYSTEM - A scheduling method is executed by a given CPU among multiple CPUs. The scheduling method includes subtracting for each of the CPUs, a number of processes assigned to the CPU from a maximum number of speculative processes that can be assigned to each of the CPUs; summing results yielded at the subtracting to yield a total number of speculative processes; and assigning to the CPUs, speculative processes of a number is less than or equal to the total number of speculative processes. | 11-14-2013 |
| 20130311727 | MEMORY CONTROL METHOD AND SYSTEM - A memory control method includes assigning based on a table to which an allocated device that executes a first process in a first application is registered, the first process in the first application to the allocated device registered; notifying a port connector of identification information of a port of memory, the port to be used by the first application, and registering a number of the port into the table; and allocating a storage area to the port and registering an address of the storage area into the table. | 11-21-2013 |
| 20130311751 | SYSTEM AND DATA LOADING METHOD - A system includes plural processors; memory that stores a program currently under execution by the processors; and a pre-loader that pre-loads into a fragment area of the memory, a target program that is to be executed and is a program other than the program currently under execution by the processors. | 11-21-2013 |
| 20130318310 | PROCESSOR PROCESSING METHOD AND PROCESSOR SYSTEM - A processor processing method is executed by a memory controller, and includes determining based on a log of access of a shared resource by a first application, whether the first application running on a first processor operates normally; and causing a second processor to run a second application other than the first application upon the first application being determined to not be operating normally. | 11-28-2013 |
| 20130318375 | PROGRAM EXECUTING METHOD - A program executing method is executed by a computer and includes calculating a first power consumption for execution of a first program described by first code; calculating a second power consumption for execution of a second program of a function identical to that of the first program and described by second code; and converting the first program into the second program and executing the second program, if the second power consumption is less than the first power consumption. | 11-28-2013 |
| 20130326527 | SCHEDULING METHOD, SYSTEM DESIGN SUPPORT METHOD, AND SYSTEM - A scheduling method is executed by a processor, and includes detecting a transition from a first process to a second process; acquiring from memory, an operating frequency and a CPU count for executing the second process; suspending a CPU under operation or starting a suspended CPU, based on the CPU count; and assigning the operating frequency to a CPU that is to execute the second process. | 12-05-2013 |
| 20130331108 | COMMUNICATION APPARATUS AND COMMUNICATION METHOD - A communication apparatus includes a first CPU that is capable of executing a communication process at a first processing speed; a measuring unit that measures a first transmission speed when the communication process is executed with a base station; a collecting unit that collects from at least one other apparatus, a second transmission speed between the base station and the apparatus, and a second processing speed of a second CPU included in the other apparatus based on the first transmission speed; a determining unit that determines whether the communication process is to be transferred to the other apparatus, based on the second transmission speed and the second processing speed; and a transferring unit that transfers the communication process to the other apparatus based on a determination result. | 12-12-2013 |
| 20130339632 | PROCESSOR MANAGEMENT METHOD - A processor management method includes setting a master mechanism in a given processor among multiple processors, where the master mechanism manages the processors; setting a local master mechanism and a virtual master mechanism in each of processors other than the given processor among the processors, where the local master mechanism and the virtual master mechanism manage each of the processors; and notifying by the master mechanism, the processors of an offset value of an address to allow a shared memory managed by the master mechanism to be accessed as a continuous memory by the processors. | 12-19-2013 |
| 20140006666 | TASK SCHEDULING METHOD AND MULTI-CORE SYSTEM | 01-02-2014 |
| 20140007131 | SCHEDULING METHOD AND SCHEDULING SYSTEM | 01-02-2014 |
| 20140007135 | MULTI-CORE SYSTEM, SCHEDULING METHOD, AND COMPUTER PRODUCT | 01-02-2014 |
| 20140012921 | FILE SHARING METHOD AND TERMINAL - A file sharing method executed by a first terminal, and including selecting from among multiple terminals including the first terminal and based on a remaining battery level of the terminals and a processing time of a shared process, a second terminal to execute the shared process for sharing multiple files among the terminals; and assigning the shared process to the second terminal. | 01-09-2014 |
| 20140019710 | ENDIAN CONVERSION METHOD AND SYSTEM - An endian conversion method is executed by a CPU, and includes executing a program that includes endian conversion setting; and performing, when accessing an address of a main memory indicated in the endian conversion setting, endian conversion of data specified by the address of the main memory. | 01-16-2014 |
| 20140019717 | SYNCHRONIZATION METHOD, MULTI-CORE PROCESSOR SYSTEM, AND SYNCHRONIZATION SYSTEM - A synchronization method is executed by a multi-core processor system. The synchronization method includes registering based on a synchronous command issued from a first CPU, CPUs to be synchronized and a count of the CPUs into a specific table; counting by each of the CPUs and based on a synchronous signal from the first CPU, an arrival count for a synchronous point, and creating by each of the CPUs, a second shared memory area that is a duplication of a first shared memory area accessed by processes executed by the CPUs; and comparing the first shared memory area and the second shared memory area when the arrival count becomes equal to the count of the CPUs, and based on a result of the comparison, judging the processes executed by the CPUs. | 01-16-2014 |
| 20140019989 | MULTI-CORE PROCESSOR SYSTEM AND SCHEDULING METHOD - A multi-core processor system includes plural CPUs; memory that is shared among the CPUs; and a monitoring unit that instructs a change of assignment of threads to the CPUs based on a first process count stored in the memory and representing a count of processes under execution by the CPUs and a second process count representing a count of processes assigned to the CPUs, respectively. | 01-16-2014 |
| 20140025903 | MULTI-CORE PROCESSOR SYSTEM - A multi-core processor system includes CPUs; memory; and a memory protect controller that is disposed between the plurality of CPUs and the memory, and that accesses a first memory area consequent to an access request of the CPUs upon application execution and further accesses a second memory area established when the system is booted. | 01-23-2014 |
| 20140026143 | EXCLUSIVE ACCESS CONTROL METHOD AND COMPUTER PRODUCT - An exclusive access control method is executed by a computer having an operating system that when an excluded thread accesses a shared resource, executes a first exclusive access control process of prohibiting the excluded thread from attempting to access the shared resource until exclusive access control is released, the exclusive access control process being executed according to a number of attempts, by the excluded thread, to access the shared resources. The exclusive access control method includes counting by at least one second thread, including the excluded thread and different from a first thread, the number of attempts to access the shared resource, when the first thread executes a second exclusive access control process of allowing the excluded thread to attempt to access the shared resource until the excluded thread is permitted access; and storing to a memory area by the second thread, the counted number of attempts. | 01-23-2014 |
| 20140032700 | DATA PROCESSING METHOD AND MOBILE TERMINAL - A data processing method is executed by a first device, and includes suspending execution of a first process by the first device that belongs to a first device group that includes plural devices; saving based on a request for execution of a second process from a second device that belongs to a second device group that includes plural devices, process information of the first process to shared memory that is set in each of the devices of the first device group and shared by the devices of the first device group; and releasing the saving of the process information of the first process consequent to completion of the execution of the second process. | 01-30-2014 |
| 20140033215 | SCHEDULING METHOD AND SCHEDULING SYSTEM - A scheduling method that is executed by a first device includes acquiring in response to a process request received by the first device, any one among a device count of peripheral devices near the first device and a device count of the peripheral devices near the first device, including the first device; and determining, by a CPU of the first device, a scheduling method for scheduling a process corresponding to the process request, based on the device count. | 01-30-2014 |
| 20140045512 | SCHEDULING METHOD AND TASK PROCESSING METHOD - A scheduling method is executed by a first apparatus among a plurality of apparatuses. The scheduling method includes assigning a process to at least one apparatus among the apparatuses based on a first table that includes each communication strength of the apparatuses; receiving an execution result of the process and a communication strength from the at least one apparatus; and creating the first table based on the received communication strength. | 02-13-2014 |
| 20140053162 | THREAD PROCESSING METHOD AND THREAD PROCESSING SYSTEM - A thread processing method is executed by a specific apparatus included among a plurality of apparatuses, and includes assigning one thread among a plurality of threads to the apparatuses, respectively; acquiring first time information that indicates a time at which the specific apparatus receives an execution result of a corresponding thread from each of the apparatuses; and setting a priority level of an access right to access shared memory that is shared by the apparatuses and the specific apparatus, the setting being based on the first time information and second time information that indicates a time at which reception of execution results of the threads from the apparatuses ends. | 02-20-2014 |
| 20140053163 | THREAD PROCESSING METHOD AND THREAD PROCESSING SYSTEM - A thread processing method that is executed by a multi-core processor, includes supplying a command to execute a first thread to a first processor; judging a dependence relationship between the first thread and a second thread to be executed by a second processor; comparing a first threshold and a frequency of access of any one among shared memory and shared cache memory by the first thread; and changing a phase of a first operation clock of the first processor when the access frequency is greater than the first threshold and upon judging that no dependence relationship exists. | 02-20-2014 |
| 20140282588 | SYSTEM AND SCHEDULING METHOD - A system includes a CPU; an accelerator; a comparing unit that compares a first value that is based on a first processing time period elapsing until the CPU completes a first process and a second processing time period elapsing until the accelerator completes the first process, and a second value that is based on a state of use of a battery driving the CPU and the accelerator; and a selecting unit that selects any one among the CPU and the accelerator, based on a result of comparison by the comparing unit. | 09-18-2014 |
| 20150081942 | MULTI-CORE PROCESSOR SYSTEM, COMPUTER PRODUCT, AND CONTROL METHOD - A multi-core processor system includes a given configured to queue an interrupt process of a software interrupt request to the given core, and execute queued processes in the order of queuing at the given core; execute preferentially an interrupt process of a hardware interrupt request to the given core over a process under execution at the given core; determine whether the software interrupt request is a specific software interrupt request; and perform control to preferentially execute the interrupt process without queuing, upon determining that the software interrupt request is the specific software interrupt request. | 03-19-2015 |
