Patent application number | Description | Published |
20090097148 | Head test apparatus and head test analysis system - A head test apparatus includes a loading section that installs the head; a head operation section that causes the head installed in the loading section to execute a test access; a test section that examines the head by judging whether a test access signal obtained from the head when the test access is executed satisfies a predetermined reference; a signal output section that obtains the test access signal and outputs the obtained test access signal to an exterior of the head test apparatus; and a reference output section that outputs a reference signal which is used for taking, in the exterior of the head test apparatus, the test access signal that the signal output section outputs in synchronism with an acquisition of the head test access. | 04-16-2009 |
20110057681 | SEMICONDUCTOR TESTING CIRCUIT, SEMICONDUCTOR TESTING JIG, SEMICONDUCTOR TESTING APPARATUS, AND SEMICONDUCTOR TESTING METHOD - A signal processing section included in a semiconductor testing circuit supplies a test signal inputted from a tester via a signal line to a plurality of DUTs and generates a test result by synthesizing response signals transmitted from the plurality of DUTs on the basis of the test signal. A test result output section included in the semiconductor testing circuit makes a voltage level of the test result differ from a voltage level of the test signal inputted and outputs the test result to the tester via the signal line. | 03-10-2011 |
20140042308 | OPTICAL ROTARY ENCODER AND CORRECTION METHOD THEREFOR - An optical rotary encoder includes a light source, a rotation body including a reflecting diffraction grating, a light receiving unit including a plurality of light receiving elements, a synthetic unit that combines output signals output from the plurality of light receiving elements to obtain a signal, which represents a fringe pattern component at a certain cycle, included in a light reflected by the reflecting diffraction grating and, and a detection unit that detects a direction based on a first signal and a second signal, the direction being a direction in which a distance between the rotation body and the light receiving unit varies, the first signal and the second signal being obtained by the synthetic unit, the first signal indicating a fringe pattern component having a cycle shorter than the certain cycle, the second signal indicating a fringe pattern component having a cycle longer than the certain cycle. | 02-13-2014 |
Patent application number | Description | Published |
20080240191 | SEMICONDUCTOR OPTICAL DEVICE AND MANUFACTURING METHOD THEREOF - In a p-type clad layer, not only a p-type dopant Zn but also Fe is doped. Its Zn concentration is 1.5×10 | 10-02-2008 |
20080291952 | OPTICAL SEMICONDUCTOR DEVICE - An optical semiconductor device with a semiconductor laser formed over a semiconductor substrate, and a modulator formed over the semiconductor substrate and continuously arranged with the semiconductor laser, wherein the semiconductor laser includes a first region having a diffraction grating with a phase shift, a second region arranged between the first region and the modulator, and in which the diffraction grating is not formed, and a common active layer formed over the first region and the second region, a first electrode injecting a current into the common active layer. | 11-27-2008 |
20080315182 | Optical semiconductor device and method for manufacturing the same - There is provided an optical semiconductor device having a first optical semiconductor element including an InP substrate, a lower cladding layer formed on the InP substrate, a lower optical guide layer which is formed on the lower cladding layer and is composed of AlGaInAs, an active layer which is formed on the lower optical guide layer and has a multiple quantum well structure where a well layer and a barrier layer that is formed of AlGaInAs are alternately stacked, an upper optical guide layer which is formed on the active layer and is composed of InGaAsP, and an upper cladding layer formed on the upper optical guide layer. | 12-25-2008 |
20090052487 | OPTICAL SEMICONDUCTOR DEVICE - An optical semiconductor device includes an active layer, a first semiconductor layer formed above the active layer and made from a semiconductor material containing Al, a second semiconductor layer formed above the first semiconductor layer and made from a semiconductor material which does not contain any one of Al and P and whose band gap is greater than that of the active layer, and a third semiconductor layer formed above the second semiconductor layer and made from a semiconductor material which does not contain Al but contains P. The second semiconductor layer is formed such that the first semiconductor layer and the third semiconductor layer do not contact with each other. | 02-26-2009 |
20100040100 | SEMICONDUCTOR LASER - A semiconductor laser includes an active layer, a first GaAs layer formed on the active layer, the first GaAs layer including a plurality of recessed portions periodically arranged, each of the recessed portions including a bottom surface of a (100) crystal surface and a slope including a (111) A crystal surface at least in parts, the recessed portion being disposed in contact with each other or with a minimal gap between each of adjacent ones of the recessed portions, the width of the bottom surface being greater than the minimal gaps, an InGaP layer formed on the recessed portion, and a second GaAs layer formed on the InGaAs layer over the recessed portion. | 02-18-2010 |
20120083058 | Optical semiconductor device and method for manufacturing the same - There is provided an optical semiconductor device having a first optical semiconductor element including an InP substrate, a lower cladding layer formed on the InP substrate, a lower optical guide layer which is formed on the lower cladding layer and is composed of AlGaInAs, an active layer which is formed on the lower optical guide layer and has a multiple quantum well structure where a well layer and a barrier layer that is formed of AlGaInAs are alternately stacked, an upper optical guide layer which is formed on the active layer and is composed of InGaAsP, and an upper cladding layer formed on the upper optical guide layer. | 04-05-2012 |
Patent application number | Description | Published |
20100246107 | INFORMATION TERMINAL DEVICE - An information terminal device includes a first case; a second case electrically connected to the first case with a cable, the second case being movable relative to the first case; and a cable-containing section that allows movement of an extra-length portion of the cable, the extra-length portion being disposed so as to have a spiral shape, the movement of the extra-length portion being caused by movement of one of the first case and the second case, wherein the cable-containing section is disposed in one of the first case and the second case. | 09-30-2010 |
20100246110 | INFORMATION TERMINAL DEVICE - An information terminal device includes a first housing and a second housing slidably connected to each other with a connecting mechanism and that is changeable in state between a closed state in which the two housings overlap each other and an open state in which the two housings overlap each other by an area smaller than in the closed state. The information terminal device includes an elastic sheet component attached to a surface of the second housing that faces the first housing and having a protrusion protruding towards the first housing, and a biasing component that biases the protrusion towards the first housing so as to cause the biased protrusion to be elastically in contact with the first housing when the information terminal device is in the closed state. | 09-30-2010 |
20120275128 | ELECTRONIC COMPONENT AND ELECTRONIC COMPONENT ASSEMBLY APPARATUS - An electronic component includes a wiring substrate having a first surface and a second surface, an electronic component body mounted on a first surface side of the wiring substrate, an external electrode formed on a second surface side of the wiring substrate which is opposite to the first surface side, the external electrode being electrically connected to the electronic component body, a heat generating member having a conductive property and having a higher resistivity than the external electrode, and a heat insulating layer disposed between the electronic component body and the heat generating member, the heat insulating layer having an insulating property and being formed of a material different from an other material of the wiring substrate. | 11-01-2012 |
20150113799 | ELECTRONIC COMPONENT ASSEMBLY APPARATUS - An electronic component includes a wiring substrate having a first surface and a second surface, an electronic component body mounted on a first surface side of the wiring substrate, an external electrode formed on a second surface side of the wiring substrate which is opposite to the first surface side, the external electrode being electrically connected to the electronic component body, a heat generating member having a conductive property and having a higher resistivity than the external electrode, and a heat insulating layer disposed between the electronic component body and the heat generating member, the heat insulating layer having an insulating property and being formed of a material different from an other material of the wiring substrate. | 04-30-2015 |
Patent application number | Description | Published |
20110134876 | Wireless Communication System, Wireless Communication Device, and Wireless Resource Management Method - It is provided a base station for providing a wireless communication area, which is coupled to a core network via a gateway, including: an interface for receiving settings of availability of allocation to terminals located in a border area of the wireless communication area and availability of allocation to terminals located in an area other than the border area for each of radio resource blocks which are defined by dividing radio resources available for use in the wireless communication area provided by the base station into predetermined units; and a plurality of profiles for defining scheduling limitations on the radio resources in the number of the profiles of patterns, being set via the interface, in which the base station applies scheduling limitations defined by the profile designated with the identifier and allocates the radio resources upon designation of one of the plurality of profiles with an identifier. | 06-09-2011 |
20110182196 | NETWORK SYSTEMS, NETWORK INTERCONNECTION DEVICES, AND DATA TRANSMISSION SCHEME - A network system includes one or more terminals which transmit acquired data to a first network, a network interconnection device which is connected to the terminal via the first network and which receives the data from the terminal, and a management server which is connected to the network interconnection device via a second network and which receives the data from the network interconnection device; the terminal transmits the same data to the network interconnection device via the first network by a frequency corresponding to redundancy; the data contains the priority according to the contents of the data; and the network interconnection device acquires the communication quality of the second network and instructs the terminal to transmit the data according to redundancy determined based upon the acquired communication quality and the priority. | 07-28-2011 |
20110287791 | Wireless Communication System and Communication Control Method - It is provided a wireless communication system comprising base stations that communicate with a terminal. Each of the base station has antennas. Each of the base stations transmits a first reference signal unique to each of the antennas which does not overlap with another antenna among the base stations at least in a vicinity thereof. The terminal receives the first reference signal and estimates a received power of the first reference signal for each of the antennas, selects antennas suitable for communication from among the antennas based on a result of estimating the received power, and transmits a result of selecting the antennas to the each of the base stations. The each of the base stations refers the result of selecting the antennas transmitted from the terminal, assigns the selected antennas belonging to different cells to the terminal, and notifies the terminal of a result of assigning the antennas. | 11-24-2011 |
20110287798 | Base Station and Wireless Communication System - It is provided a wireless communication system comprising base stations that transmit data to a terminal with cooperation by the base stations. The terminal communicates with the base stations. The terminal periodically transmits, to one of the base stations, information necessary for data transmission from a single base station out of the base stations. Each of the base stations determines whether the terminal needs data transmission through a cooperation among the base stations, and transmits a cooperation information transmission instruction to the terminal, which includes information necessary to execute the data transmission in order to cooperate among the base stations in the case where it is determined that the terminal needs the data transmission through the cooperation among the base stations. The terminal transmits the cooperation information to the base stations in a case of receiving the cooperation information transmission instruction. | 11-24-2011 |
20120317278 | COMMUNICATION APPARATUS, COMMUNICATION METHOD AND REMOTE MONITORING SYSTEM - In a remote monitoring system including a monitoring center, a sensing information collecting station, and one or more sensing terminals, the sensing information collecting station collects measurement results measured by the sensing terminals, classifies the collected measurement results into priority information and general information, and transmits priority information and general information to the monitoring center. The monitoring center transmits response information to received priority information to the sensing information collecting station. The sensing information collecting station estimates network condition from a delay time based on the response information and decreases the transmission rate of general information when the estimated network condition is more congested. Thereby, even if the network condition fluctuates, desired information such as statistical information on measurement results and measurement results meeting a predetermined condition is communicated stably at low delay. | 12-13-2012 |
20120320928 | MONITORING SYSTEM, DEVICE, AND METHOD - Provided is a monitoring system which can perform priority control in accordance with the wideband limitation. A priority/filter type selection processing unit ( | 12-20-2012 |
20130121238 | RELAY COMMUNICATION APPARATUS AND MULTISTAGE RELAY COMMUNICATION SYSTEM - A multistage relay communication system | 05-16-2013 |
20130185417 | REMOTE MONITORING SYSTEM, NETWORK INTERCONNECTION DEVICE AND COMMUNICATION CONTROL METHOD - Even though a network with communication rate large fluctuations is applied to a remote monitoring system, data communication delay time is kept smaller for which a shorter communication delay time is demanded and a high throughput is implemented. A sensor equipped terminal sends measurement data to a network interconnection device. A priority level determining unit of the device sorts the data into first data necessary to be delivered to a monitoring center within requested communication delay time and second data not necessarily to be delivered to the center within requested communication delay time. A transmission buffer unit is a buffer storing the first and second data accumulated in first and second data accumulating units in sending the data to a wide area network by FIFO. A transmission control unit dynamically controls a rate in causing the data to come in the transmission buffer unit based on a network communication rate. | 07-18-2013 |
Patent application number | Description | Published |
20090020588 | Method for manufacturing product involving solder joining, solder joining apparatus, soldering condition verification method, reflow apparatus, and solder joining method - A method for manufacturing a product involving solder joining wherein components placed on a board on which the components are to be mounted are solder-joined to the board by subjecting the board to reflow heating under prescribed heating conditions, the method comprising: calculating, at each designated site on the board, a component volume that is occupied by the components mounted within a given area; determining the heating conditions in accordance with the calculated component volume; and performing the reflow heating based on the determined heating conditions. | 01-22-2009 |
20100214741 | ELECTRONIC COMPONENT MOUNTING STRUCTURE AND ELECTRONIC COMPONENT MOUNTING METHOD - An electronic component mounting structure includes a first substrate on which a first component is mounted and a second substrate connected to the first substrate. The second substrate is bent toward the first component. | 08-26-2010 |
20110007482 | PRINTED CIRCUIT BOARD UNIT AND ELECTRONIC DEVICE - A printed circuit board unit includes a printed circuit board including through holes arranged in a grid array on which an integrated circuit is mounted; and a flexible substrate provided on a back side of the printed circuit board, covering the through holes. First lands to which the integrated circuit is connected are formed on a front side of the printed circuit board. Second lands to which the flexible substrate is connected are formed on the back side of the printed circuit board. The first lands and the second lands are connected to first ends and second ends of the through holes, respectively. Third lands are formed on a front side of the flexible substrate so as to face the second lands of the printed circuit board. Fourth lands are formed on a back side of the flexible substrate. The fourth lands are electrically connected to the third lands. | 01-13-2011 |
20110031628 | SEMICONDUCTOR DEVICE MODULE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE MODULE - A semiconductor device module includes a first substrate layer on which a first semiconductor device is surface-mounted, a second substrate layer that is a layer laminated on a side of the first substrate layer on which the first semiconductor device is not surface-mounted, a second semiconductor device being surface-mounted on a surface of the second substrate layer and not on a side of the first substrate layer, and a hollow section that is a space sandwiched between the first substrate layer and the second substrate layer and formed on back sides of areas on which the first semiconductor device and the second semiconductor device are surface-mounted. | 02-10-2011 |
20110240719 | METHOD OF REMOVING PART HAVING ELECTRODE ON THE BOTTOM - In the initial state, a part having a bottom electrode such as a BGA is attached to a substrate. A heat transfer material such as low melting point solder is allowed to fill a gap between the substrate and the part having the bottom electrode, and the heat transfer material and the BGA serving as the bottom electrode are heated. The heat transfer material and the BGA are melted by the heating so that the part having the bottom electrode is removed from the substrate. | 10-06-2011 |
20120024512 | HEAT SINK DEVICE AND METHOD OF REPAIRING SEMICONDUCTOR DEVICE - A method of repairing a semiconductor device includes turning a press member to apply pressure on an electronic component which is mounted on a substrate. A heat sink which is provided on the electronic component via a bonding layer is thus displaced with respect to the electronic component in a transverse direction. The heat sink is removed from the electronic component by shearing the bonding layer with the press member. | 02-02-2012 |
20120083151 | METHOD OF DETACHMENT OF CONNECTOR, CONNECTOR DETACHMENT TOOL, AND CONNECTOR - A method of detachment of a connector which is provided with a housing having connector pins to be inserted into a board and with a first member which is arranged between the housing and the board and through which the connector pins are inserted, the method including a process of pulling out the connector pins from the board. This process utilizes the lever principle, which uses the first member as a fulcrum and which uses any point on the housing as a point of action, so as to pull out the connector pins from the board. | 04-05-2012 |
Patent application number | Description | Published |
20140281059 | ARITHMETIC PROCESSING APPARATUS AND CONTROL METHOD OF ARITHMETIC PROCESSING APPARATUS - In a multicore system in which a plurality of CPUs each including a cache memory share one main memory, a write buffer having a plurality of stages of buffers each holding data to be written to the main memory and an address of a write destination is provided between the cache memory and the main memory, and at the time of a write to the write buffer from the cache memory, an address of a write destination and the addresses stored in the buffers are compared, and when any of the buffers has an agreeing address, data is overwritten to this buffer, and the buffer is logically moved to a last stage. | 09-18-2014 |
20140282435 | PERFORMANCE PROFILING APPARATUS AND PERFORMANCE PROFILING METHOD - A performance profiling apparatus includes: a plurality of counters provided for a routine included in a program; a storage section configured to store an instruction of the program and an identification information indicating the routine of the program; a processor configured to read the instruction from the storage section and to execute a process according to the instruction; and a counter controller configured to, at the time of reading the instruction of the processor, receive the identification information of the instruction which is output from the storage section with the instruction and to instruct a first counter designated by the identification information to count up. | 09-18-2014 |
20140297963 | PROCESSING DEVICE - When an invalidation request is inputted from another processing device, a cache controller registers a set of an invalidation request address which the invalidation request has and an identifier of the other processing device which outputted the invalidation request in an invalidation history table. When a central processing unit attempts to read data at a first address not stored in a cache memory, if the first address is registered in the invalidation history table, the cache controller outputs a coherent read request containing the first address to the other processing device indicated by the identifier of the other processing device which outputted the invalidation request corresponding to the first address, or if the first address is not registered in the invalidation history table, the cache controller outputs a coherent read request containing the first address to all other processing devices. | 10-02-2014 |
20140337584 | CONTROL APPARATUS, ANALYSIS APPARATUS, ANALYSIS METHOD, AND COMPUTER PRODUCT - A cache controller receives a reference request from a CPU executing a program in which information indicative of a reference request specifying in shared memory, an area not having an update request and information indicative of a snoop reference request are distinguished from one another. When the reference request specifying an area not having the update request is received, the cache controller acquires from the shared memory and without performing a snoop process, information stored in the specified area. The cache controller stores the information acquired from the shared memory to the cache memory of the CPU executing the program. | 11-13-2014 |
20150205648 | INFORMATION PROCESSING APPARATUS AND METHOD OF COLLECTING PERFORMANCE ANALYSIS DATA - An information processing apparatus includes a packet preprocessing unit configured to generate a packet process request when a packet is received; a CPU core configured to process the packet in response to the packet process request; a hardware element configured to generate a message including information identifying a predetermined event, in response to the predetermined event occurring in accordance with the processing of the packet, the hardware element being provided in the CPU core; and a message recording unit configured to record the message generated by the hardware element together with a count value of a timer. | 07-23-2015 |