Patent application number | Description | Published |
20090085624 | FLIP-FLOP CIRCUIT AND DUTY RATIO CORRECTION CIRCUIT USING THE SAME - A flip-flop circuit includes a first unit configured to receive a reference clock signal and a reset signal, and a second unit configured to change an output node to a first level in response to the reference clock signal and change the output node to a second level by precharging the output node in response to a signal output from the first unit according to the reset signal. | 04-02-2009 |
20090121701 | BANDGAP REFERENCE GENERATING CIRCUIT - A bandgap reference generating circuit includes an operational amplifier configured to generate a bandgap reference voltage; and a gain controller configured to control a gain of the operational amplifier with different values in a normal mode and a low power mode. | 05-14-2009 |
20090128208 | APPARATUS AND METHOD FOR DETECTING DUTY RATIO OF SIGNALS IN SEMICONDUCTOR DEVICE CIRCUIT - Apparatus for detecting duty ratio of signals in semiconductor device circuit includes a circuit for detecting a duty ratio of signals in a semiconductor device includes a comparing unit which compares a duty cycle of first and second input clock signals input differentially and generates a first output signal and a second output signal, a latching unit which stores the first and second output signals and generates a detected signal corresponding to the first and second output signals, and an adjusting unit which receives the first and the second output signals, and transmits the first and the second output signals to the latching unit based on a voltage level difference of the first and second output signals. | 05-21-2009 |
20090168944 | LOW PASS FILTER AND LOCK DETECTOR CIRCUIT - A low pass filter includes a driver unit configured to output a voltage proportional to an input pulse width, a charge/discharge unit configured to charge the output voltage of the driver unit, a comparator unit configured to compare an output voltage of the charge/discharge unit with a reference value to output a square wave signal, and a switching unit configured to switch the charge/discharge unit to an operation state, based on a bandwidth expansion signal. | 07-02-2009 |
20090175116 | CLOCK SYNCHRONIZATION CIRCUIT AND OPERATION METHOD THEREOF - A semiconductor memory device with a clock synchronization circuit capable of performing a desired phase/frequency locking operation, without the jitter peaking phenomenon and the pattern jitter of an oscillation control voltage signal using injection locking. The device includes a phase-locked loop that detects a phase/frequency difference between a feedback clock signal and a reference clock signal to generate an oscillation control voltage signal corresponding to the detected phase/frequency difference, and generates the feedback clock signal corresponding to the oscillation control voltage signal. An injection locking oscillation unit sets up a free running frequency in response to the oscillation control voltage signal and generates an internal clock signal which is synchronized with the reference clock signal. | 07-09-2009 |
20090256610 | Quadrature phase correction circuit - A quadrature phase correction circuit includes an N-bit code counter configured to generate an N-bit code value according to a detected phase difference when a quadrature phase correction is carried out; a storage configured to store N-bit code values according to a plurality of detected phase differences; and a controller configured to share the N-bit code counter, control the generation of the N-bit code values according to the plurality of detected phase differences, and control the storing of the N-bit code values in an allocated space of the storage. | 10-15-2009 |
20090302891 | OUTPUT DRIVER - There is provided an output driver, which includes a pre-driver configured to generate a main driving control signal in response to a data signal, a main driver configured to drive an output terminal in response to the main driving control signal, an auxiliary driving control signal generator configured to generate an auxiliary driving control signal having an activation interval corresponding to the data signal and an interval control signal, and an auxiliary driver configured to drive the output terminal in response to the auxiliary driving control signal. | 12-10-2009 |
20090322394 | RING OSCILLATOR AND MULTI-PHASE CLOCK CORRECTION CIRCUIT USING THE SAME - A ring oscillator including a plurality of buffer units, each of which has a cross-coupled structure, for generating clock signals using a bias voltage having a predetermined voltage level applied thereto, wherein the clock signals have a swing width corresponding to the bias voltage. | 12-31-2009 |
20090322399 | CLOCK GENERATING CIRCUIT AND CLOCK GENERATING METHOD THEREOF - A clock generating circuit, including a pulse generating unit to generate a plurality of pulse signals based on a reference clock, the pulse signals each having the same period, a phase difference between the adjacent pulse signals being a first phase difference; and a multi-phase clock generating unit to generate a plurality of multi-phase clocks, a phase difference between the adjacent multi-phase clocks being equal to a second phase difference between pulse signals of a pulse signal pair, based on a plurality of unit-phase clock generating units receiving the pulse signal pairs. | 12-31-2009 |
20100007375 | TERMINATION RESISTANCE CIRCUIT - A termination resistance circuit includes a control signal generator for generating a control signal whose logical value changes when a calibration code has a predetermined value, a plurality of parallel resistors which are respectively turned on/off in response to the calibration code, and a resistance value changing unit for changing the total resistance value of the termination resistance circuit in response to the control signal. | 01-14-2010 |
20100013535 | LATCH CIRCUIT - A latch circuit includes a data input/output unit configured to form a current path through a first node in response to an input data to output an output data, a holding unit configured to form a current path through a second node in response to the output data to store the output data, and a clock input unit coupled to the first and second nodes in parallel in response to a clock. | 01-21-2010 |
20100061157 | DATA OUTPUT CIRCUIT - A data output circuit includes a serial data output unit for outputting a plurality of parallel data as serial data according to an operation mode, an internal information output unit for outputting internal information data according to the operation mode, and a buffering unit for receiving the serial data and the internal information data through an identical input end and buffering the received data. | 03-11-2010 |
20100109923 | SEMICONDUCTOR DEVICE - A semiconductor device includes a plurality of synchronization blocks configured to sequentially synchronize a plurality of input signals swinging in a complementary metal oxide semiconductor (CMOS) region with multi-phase clock signals to output a plurality of output signals swinging in a current mode logic (CML) region, a plurality of first swing region converting blocks configured to convert the plurality of output signals to a plurality of converted output signals swinging in the CMOS region, a serialization block configured to serialize a plurality of converted output signals, thereby outputting a serialized signal swinging in the CML region, and a second swing region converting block configured to convert the serialized signal to a serialized output signal swinging in the CMOS region. | 05-06-2010 |
20100237922 | CLOCK GENERATING CIRCUIT AND CLOCK GENERATING METHOD THEREOF - A clock generating circuit, including a pulse generating unit to generate a plurality of pulse signals based on a reference clock, the pulse signals each having the same period, a phase difference between the adjacent pulse signals being a first phase difference; and a multi-phase clock generating unit to generate a plurality of multi-phase clocks, a phase difference between the adjacent multi-phase clocks being equal to a second phase difference between pulse signals of a pulse signal pair, based on a plurality of unit-phase clock generating units receiving the pulse signal pairs. | 09-23-2010 |
20110121860 | SEMICONDUCTOR DEVICE - A semiconductor device includes a swing level shifting unit configured to use a first power supply voltage as a power supply voltage, receive a CML clock swinging around a first voltage level, and shift a swing reference voltage level of the CML clock to a second voltage level lower than the first voltage level, and a CML clock transfer buffering unit configured to use a second power supply voltage as a power supply voltage and buffer the CML clock, which is transferred from the swing level shifting unit and swings around the second voltage level. | 05-26-2011 |
20110140768 | INTERNAL VOLTAGE GENERATOR - An internal voltage generator includes: a detection unit configured to detect a level of an internal voltage in comparison to a reference voltage; a first driving unit configured to discharge an internal voltage terminal, through which the internal voltage is outputted, in response to an output signal of the detection unit; a current detection unit configured to detect a discharge current flowing through the first driving unit; and a second driving unit configured to charge the internal voltage terminal in response to an output signal of the current detection unit. | 06-16-2011 |
20110181332 | RING OSCILLATOR FOR GENERATING OSCILLATING CLOCK SIGNAL - A ring oscillator including a plurality of buffer units, each of which has a cross-coupled structure, for generating clock signals using a bias voltage having a predetermined voltage level applied thereto, wherein the clock signals have a swing width corresponding to the bias voltage. | 07-28-2011 |
20110291759 | RAIL-TO-RAIL AMPLIFIER - A rail-to-rail amplifier includes an NMOS type amplification unit configured to perform an amplification operation on differential input signals in a domain in which DC levels of the differential input signals are higher than a first threshold value, a PMOS type folded-cascode amplification unit configured to perform an amplification operation on the differential input signals in a domain in which the DC levels of the differential input signals are lower than a second threshold value which is higher than the first threshold value, the PMOS type folded-cascode amplification unit being cascade-coupled to the NMOS type amplification unit, and an adaptive biasing unit configured to interrupt a current path of the PMOS type folded-cascode amplification unit in a domain in which the DC levels of the differential input signals are higher than the second threshold value in response to the differential input signals. | 12-01-2011 |
20120262323 | BUFFER CONTROL CIRCUIT AND INTEGRATED CIRCUIT INCLUDING THE SAME - A buffer control circuit includes a current supply unit configured to supply current and adjust the current in response to codes, an amplifying buffer configured to operate using the current and output a value obtained by comparing a reference potential and the reference potential, a second buffer configured to buffer an output of the first buffer, and a code generation unit configured to generate the codes in response to an output of the second buffer. | 10-18-2012 |
20130070512 | NON-VOLATILE MEMORY DEVICE - A non-volatile memory device includes a memory cell including a resistance variable device and a switching unit for controlling a current flowing through the resistance variable device; a read reference voltage generator configured to generate a reference voltage according to a skew occurring in the switching unit; and a sense amplifier configured to sense a voltage corresponding to the current that flows through the resistance variable device based on the reference voltage. | 03-21-2013 |
20130147517 | SEMICONDUCTOR DEVICE AND OPERATION METHOD THEREOF - A semiconductor device includes a clock delay unit configured to delay a source clock by a given delay amount and generate a delayed source clock, a driving signal generation unit configured to decide logic levels of first and second driving signals based on a value of input data, to select one of the source clock and the delayed source clock based on current logic levels of the first and second driving signals, which are detected based on the source clock, and to use a selected clock as a reference of an operation for determining next logic levels of the first and second driving signals, and an output pad driving unit configured to drive a data output pad with a first voltage in response to the first driving signal, and to drive the data output pad with a second voltage in response to the second driving signal. | 06-13-2013 |
20130162311 | FILTERING CIRCUIT, PHASE IDENTITY DETERMINATION CIRCUIT AND DELAY LOCKED LOOP - A filtering circuit includes a clock selection unit configured to transfer a first clock or a second clock having a frequency lower than the first clock as an operating clock in response to a frequence signal, and a filter configured to filter an input signal and generate a filtered signal in synchronization with the operating clock. | 06-27-2013 |
20130216017 | COUNTING CIRCUIT, DELAY VALUE QUANTIZATION CIRCUIT, AND LATENCY CONTROL CIRCUIT - A counting circuit includes: a clock division unit configured to divide a reference clock signal at a preset division ratio and generate a divided clock signal, a counting unit configured to count the divided clock signal, and a counting control unit configured to enable the counting unit during an enable period corresponding to the division ratio. | 08-22-2013 |
20140132339 | FILTERING CIRCUIT, PHASE IDENTITY DETERMINATION CIRCUIT AND DELAY LOCKED LOOP - A filtering circuit includes a clock selection unit configured to transfer a first clock or a second clock having a frequency lower than the first clock as an operating clock in response to a frequence signal, and a filter configured to filter an input signal and generate a filtered signal in synchronization with the operating clock. | 05-15-2014 |
20140133214 | RESISTIVE MEMORY DEVICE AND METHOD FOR DRIVING THE SAME - A resistive memory device includes a plurality of memory cells, each of which is configured to store a normal data, a first reference data corresponding to a first resistance state and a second reference data corresponding to a second resistance state, a data copy unit configured to temporarily store the normal data read from a selected memory cell and generate a copied cell current based on the stored normal data, a mirroring block configured to temporarily store the first and second reference data read from the selected memory cell, and to generate a first reference current and a second reference current based on the stored first and second reference data, respectively, and a sensing unit configured to sense the stored normal data based on the copied cell current and the first reference current and the second reference current. | 05-15-2014 |
20140176197 | SEMICONDUCTOR DEVICE AND OPERATING METHOD THEREOF - A semiconductor device includes a plurality of driving units configured to drive an output node based on an input signal and be on/off controlled based on driving force control codes, respectively, a slew rate control signal generation block configured to generate a slew rate control signal based on the driving force control codes, and a plurality of signal delay units configured to delay the input signal by respectively different delay amounts, transfer resultant signals to the plurality of driving units, and be respectively controlled in their delay amounts based on the slew rate control signal. | 06-26-2014 |
20140312953 | EQUALIZER CIRCUIT AND RECEIVER CIRCUIT INCLUDING THE SAME - An equalizer circuit includes an input terminal, a pull-up driving unit suitable for pull-up driving an output terminal based on a signal of the input terminal, a pull-down driving unit suitable for pull-down driving the output terminal, and a capacitor connected between the input terminal and the output terminal. | 10-23-2014 |
20140368248 | FLIP-FLOP CIRCUIT AND DUTY RATIO CORRECTION CIRCUIT USING THE SAME - A flip-flop circuit includes a first unit configured to receive a reference clock signal and a reset signal, and a second unit configured to change an output node to a first level in response to the reference clock signal and change the output node to a second level by precharging the output node in response to a signal output from the first unit according to the reset signal. | 12-18-2014 |
20150043702 | COUNTING CIRCUIT, DELAY VALUE QUANTIZATION CIRCUIT, AND LATENCY CONTROL CIRCUIT - A counting circuit includes: a clock division unit configured to divide a reference clock signal at a preset division ratio and generate a divided clock signal, a counting unit configured to count the divided clock signal, and a counting control unit configured to enable the counting unit during an enable period corresponding to the division ratio. | 02-12-2015 |