Patent application number | Description | Published |
20080291198 | METHOD OF PERFORMING 3D GRAPHICS GEOMETRIC TRANSFORMATION USING PARALLEL PROCESSOR - Provided is a method of performing three-dimensional (3D) graphics geometric transformation using a parallel processor having a plurality of Processing Elements (PEs). The method includes performing model/view transformation and projection transformation on a first group of vertex vectors using the parallel processor; calculating a value used for quaternion correction of the first group of vertex vectors using a general-use processor, and simultaneously performing model/view transformation and projection transformation on a second group of vertex vectors; performing quaternion correction and screen mapping on the first group of vertex vectors, and simultaneously calculating a value used for quaternion correction of the second group of vertex vectors using the general-use processor; and performing quaternion correction and screen mapping on the second group of vertex vectors. | 11-27-2008 |
20080292001 | APPARATUS AND METHOD FOR CALCULATING SUM OF ABSOLUTE DIFFERENCES FOR MOTION ESTIMATION OF VARIABLE BLOCK - Provided are an apparatus and method for calculating a Sum of Absolute Differences (SAD) for motion estimation of a variable block capable of parallelly calculating SAD values with respect to a plurality of current frame macroblocks at a time. The apparatus includes a PE array unit including at least one Processing Element (PE) that is aligned in the form of a matrix, and parallelly calculating a SAD value of at least one pixel provided in a plurality of serial current frame macroblocks, a local memory including current frame macroblock data, reference frame macroblock data, and reference frame search area data, and transmitting the data to each PE that is provided in the PE array unit, and a controller for making a command for the data that are provided in the local memory to be transmitted corresponding to at least one pixel, on which each PE provided in the PE array unit performs calculation. | 11-27-2008 |
20080294875 | PARALLEL PROCESSOR FOR EFFICIENT PROCESSING OF MOBILE MULTIMEDIA - Provided is a parallel processor for supporting a floating-point operation. The parallel processor has a flexible structure for easy development of a parallel algorithm involving multimedia computing, requires low hardware cost, and consumes low power. To support floating-point operations, the parallel processor uses floating-point accumulators and a flag for floating-point multiplication. Using the parallel processor, it is possible to process a geometric transformation operation in a 3-dimensional (3D) graphics process at low cost. Also, the cost of a bus width for instructions can be minimized by a partitioned Single-Instruction Multiple-Data (SIMD) method and a method of conditionally executing instructions. | 11-27-2008 |
20090138645 | SOC SYSTEM - Provided is a System on Chip (SoC) system for a multimedia system enabling high-speed transfer of a large amount of multimedia data and a processor to rapidly control a peripheral device. The SoC system includes a processor; a plurality of peripheral devices; a plurality of physically divided memories; a control bus for transferring a control signal from the processor to the peripheral devices and the memories; a data bus for transferring data between the processor, the peripheral devices and the memories; a bridge for coupling the control bus and the data bus to the processor; a plurality of memory controllers coupled to the control bus and controlling each of the memories; a Direct Memory Access (DMA) controller coupled to the data bus and the control bus and controlling data transfer between the peripheral devices and the memories; and a matrix switch coupled between the DMA controller and the memory controllers and enabling simultaneous multiple memory access. | 05-28-2009 |
20090144523 | MULTIPLE-SIMD PROCESSOR FOR PROCESSING MULTIMEDIA DATA AND ARITHMETIC METHOD USING THE SAME - A multiple-single instruction multiple data (SIMD) processor and an arithmetic method using the same are disclosed. When various arithmetic operations should be individually carried out by SIMD arithmetic units, control right is sub-divided to perform the arithmetic operations, such that the time of the arithmetic operations can be shortened and the efficiency thereof can be raised. When sub-divided control is not required, the control right is withdrawn and the arithmetic operations are carried out using a minimum number of program memories and a minimum number of SIMD arithmetic units, such that memory and power consumption thereof can be reduced. | 06-04-2009 |
20090150471 | RECONFIGURABLE ARITHMETIC UNIT AND HIGH-EFFICIENCY PROCESSOR HAVING THE SAME - Provided are a reconfigurable arithmetic unit and a processor having the same. The reconfigurable arithmetic unit can perform an addition operation or a multiplication operation according to an instruction by sharing an adder. The reconfigurable arithmetic unit includes a booth encoder for encoding a multiplier, a partial product generator for generating a plurality of partial products using the encoded multiplier and a multiplicand, a Wallace tree circuit for compressing the partial products into a first partial product and a second partial product, a first Multiplexer (MUX) for selecting and outputting one of the first partial product and a first addition input according to a selection signal, a second MUX for selecting and outputting one of the second partial product and a second addition input according to the selection signal, and a Carry Propagation Adder (CPA) for adding an output of the first MUX and an output of the second MUX to output an operation result. The arithmetic unit can operate as an adder or a multiplier according to an instruction, and thus can increase the degree of use of entire hardware. | 06-11-2009 |
20090282223 | DATA PROCESSING CIRCUIT - Provided is a data processing circuit. A control unit outputs an operation control signal and a memory control signal. A plurality of program memories each outputs a command in response to the memory control signal. A plurality of arithmetic sections each selectively performs any one of the commands from the plurality of program memories in response to the operation control signal. Operation modes of the data processing circuit can be flexibly changed according to operation environments. | 11-12-2009 |
20100017544 | DIRECT MEMORY ACCESS CONTROLLER AND DATA TRANSMITTING METHOD OF DIRECT MEMORY ACCESS CHANNEL - Provided is a direct memory access (DMA) controller. The DMA controller includes a plurality of channel groups and a channel group controller. Each of the channel groups has a plurality of DMA channels, and the channel group controller controls enablement of the DMA channels in units of channel groups. Herein, the channel group controller enables the DMA channels of at least one of the channel groups in data transmission. | 01-21-2010 |
20100019321 | MULTIPLE-GATE MOS TRANSISTOR USING Si SUBSTRATE AND METHOD OF MANUFACTURING THE SAME - Provided are a multiple-gate MOS (metal oxide semiconductor) transistor and a method of manufacturing the same. The transistor includes a single crystalline active region having a channel region having an upper portion of a streamlined shape (∩) obtained by patterning an upper portion of a bulk silicon substrate with an embossed pattern, and having a thicker and wider area than the channel region; a nitride layer formed at both side surfaces of the single crystalline active region to expose an upper portion of the single crystalline active region at a predetermined height; and a gate electrode formed to be overlaid with the exposed upper portion of the single crystalline active region of the channel region. | 01-28-2010 |
20100126548 | THERMOELECTRIC DEVICE, THERMOELECTIC DEVICE MODULE, AND METHOD OF FORMING THE THERMOELECTRIC DEVICE - Provided are a thermoelectric device, a thermoelectric device module, and a method of forming the thermoelectric device. The thermoelectric device includes a first conductive type first semiconductor nanowire including at least one first barrier region; a second conductive type second semiconductor nanowire including at least one second barrier region; a first electrode connected to one end of the first semiconductor nanowire; a second electrode connected to one end of the second semiconductor nanowire; and a common electrode connected to the other end of the first semiconductor nanowire and the other end of the second semiconductor nanowire. The first barrier region is greater than the first semiconductor nanowire in thermal conductivity, and the second barrier region is greater than the second semiconductor nanowire in thermal conductivity. | 05-27-2010 |
20100135396 | IMAGE PROCESSING DEVICE - Provided is an image processing device. The image processing device includes: a plurality of operation units; and a controller unit storing an occurred bit amount to calculate a rate-distortion cost value and transmitting the occurred bit amount to each of the plurality of operation units, wherein at least one of the plurality of operation units calculates each distortion value with respect to a plurality of encoding modes and calculates each rate-distortion cost value with respect to the plurality of encoding modes using the calculated each distortion value and occurred bit amount. | 06-03-2010 |
20100146219 | MEMORY ACCESS DEVICE INCLUDING MULTIPLE PROCESSORS - Provided is a memory access device including multiple processors accessing a specific memory. The memory access device includes first and second processors, first and second transaction controllers, a memory access switch, and a memory controller. The first and second transaction controllers are connected respectively to the first and second processors. The memory access switch is connected to the first and second transaction controllers. The memory controller is connected to the memory access switch to control a memory device. Herein, if the first and second processors simultaneously access the memory device, the second processor stores an address or data in the second transaction controller while the first processor is accessing the memory device. Accordingly, the memory access device enables multiple processors, which are to simultaneously access a specific memory, to perform other operations during the standby time taken to access the specific memory. | 06-10-2010 |
20100155703 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - Provided are a semiconductor device and a method of fabricating the same. The semiconductor device includes: a single electron box including a first quantum dot, a charge storage gate on the first quantum dot, and a first gate electrode on the charge storage gate, the charge storage gate exchanging charges with the first quantum dot, the first gate electrode adjusting electric potential of the first quantum dot; and a single electron transistor including a second quantum dot below the first quantum dot, a source, a drain, and a second gate electrode below the second quantum dot, the second quantum dot being capacitively coupled to the first quantum dot, the source contacting one side of the second quantum dot, the drain contacting the other side facing the one side, the second gate electrode adjusting electric potential of the second quantum dot. | 06-24-2010 |
20100156680 | METHOD OF DRIVING BIT STREAM PROCESSOR - Provided is a bit stream processor using a reduced table lookup. The bit stream processor includes a bit stream exclusive register in a general purpose register in order to process data of a variable length effectively. Additionally, the bit stream processor an instruction of a table lookup method to which a prefix method is applied and a bit stream exclusive instruction in order to reduce an entire memory size. | 06-24-2010 |
20100161849 | MULTI CHANNEL DATA TRANSFER DEVICE - Provided is a multi channel data transfer device. The multi channel data transfer device includes: a plurality of channel control unit connected to a plurality of peripheral devices, respectively; a plurality of control registers storing setting data for controlling an operation of each of the plurality of channel controllers; and a common register controller delivering common setting data to all or part of the plurality of control registers, the common setting data being applied in common to all or part of the plurality of channel controllers. | 06-24-2010 |
20100162016 | LOW POWER CONSUMPTION PROCESSOR - Provided is a low power consumption processor. The processor includes: a plurality of blocks; a memory storing instructions that control each of the plurality of blocks; and a multi power controller generates a signal that activates at least one of the plurality of blocks according to an address storing the instruction, and provides a normal power voltage or a reduction power voltage in response to the activation signal. | 06-24-2010 |
20110022647 | APPARATUS FOR CALCULATING ABSOLUTE DIFFERENCE - Provided is an apparatus for calculating an absolute difference capable of efficiently performing an absolute difference using an adder. The apparatus for calculating an absolute difference includes a comparator comparing values of two integers, first and second selectors each selecting and outputting one of the two integers according to the comparison results of the comparator, an inverter complementing the result value selected by the second selector; and an adder adding up the result value selected by the first selector, the value complemented by the inverter, and 1. | 01-27-2011 |
20110022767 | DMA CONTROLLER WITH INTERRUPT CONTROL PROCESSOR - Provided is a direct memory access (DMA) controller having an interrupt control processor that can process DMA transmission-related interrupts according to a control program modifiable by a user. The DMA controller includes the interrupt control processor that can process a DMA transmission-related interrupt and a DMA request interrupt transmitted from peripheral devices and control the DMA channel through the control program that can be modified by the user, so that DMA channel control and relevant interrupt processing loads caused by a plurality of DMA data transmissions are reduced, and the flexibility of DMA channel control and interrupt processing in control of the DMA controller is provided to the user. | 01-27-2011 |
20110135191 | APPARATUS AND METHOD FOR RECOGNIZING IMAGE BASED ON POSITION INFORMATION - According to the present invention, the amount of computation required for image recognition processing can be reduced by extracting only image recognition learning information for an object that may appear in a region having the geographical property of a current position and comparing the image recognition learning information with ambient-image information. | 06-09-2011 |
20110142345 | APPARATUS AND METHOD FOR RECOGNIZING IMAGE - Provided are an apparatus and method for recognizing an image. In the apparatus and method for recognizing an image, various features can be extracted by a Haar-like filter using 1 | 06-16-2011 |
20110144859 | APPARATUS AND METHOD FOR PREVENTING COLLISION OF VEHICLE - The present invention provides an apparatus and method for predicting a moving direction of another vehicle running on a carriageway adjacent to a user's vehicle using periodically acquired image information around the user's vehicle, and performing a control process of preventing collision of the user's vehicle when a moving direction of the user's vehicle crosses the moving direction of the other vehicle. | 06-16-2011 |
20110145549 | PIPELINED DECODING APPARATUS AND METHOD BASED ON PARALLEL PROCESSING - An apparatus and method for decoding moving images based on parallel processing are provided. The apparatus for decoding images based on parallel processing can improve operational performance by pipelining massive-data transmission between processors while performing context-adaptive variable length decoding (CAVLD), inverse quantization (IQ), inverse transformation (IT), motion compensation (MC), intra prediction (IP) and deblocking filter (DF) operations in parallel in units of pluralities of macroblocks (MBs). | 06-16-2011 |
20110153878 | MEMORY SYSTEM AND INTEGRATED MANAGEMENT METHOD FOR PLURALITY OF DMA CHANNELS - Provided are a memory system and an integrated management method for a plurality of direct memory access (DMA) channels. The memory system includes a memory controller exchanging data with a memory and having a plurality of channels physically separated from each other, and a DMA controller having a plurality of DMA channels physically separated from each other and in contact with the plurality of channels of the memory controller, and exchanging data with the memory via the plurality of DMA channels and the memory controller. | 06-23-2011 |
20120076408 | METHOD AND SYSTEM FOR DETECTING OBJECT - Provided are a system and method for detecting an object. The method includes selecting a macroscopic scan mode in which there are a small number of divided regions or a microscopic scan mode in which there are a large number of divided regions according to complexity of a background including an object to be detected, dividing an input image into one or more regions according to the selected scan mode, merging adjacent regions having similar characteristics among the divided regions, extracting a search region by excluding a region having a high probability that the object to be detected does not exist from the divided or merged regions, extracting feature data including a feature vector for detecting the object in the search region, and detecting the object in the search region using the extracted feature data. | 03-29-2012 |
20120081542 | OBSTACLE DETECTING SYSTEM AND METHOD - The obstacle detecting system includes a first image acquiring unit which acquires first image information by selectively receiving a laser beam emitted from at least one laser source toward a road surface at a target distance; a second image acquiring unit which acquires an image of actual surroundings as second image information; an image recognizing unit which recognizes an image of an obstacle by performing 3-D image recognition signal processing on line information of the laser beam using the first image information, and recognizes a pattern of the obstacle by performing pattern recognition signal processing on the second image information; and a risk determining unit which determines a possibility of collision due to presence of the obstacle within the target distance by classifying the recognized obstacles according to whether or not the image-recognized obstacle is matched with the pattern-recognized obstacle. | 04-05-2012 |
20120092489 | IMAGE RECOGNIZING METHOD AND IMAGE RECOGNIZING DEVICE - Provided is an image recognizing method. The image recognizing method includes selecting a partial data from a standard image data, recognizing image based on the selected data, reduction-converting the selected data, and recognizing image based on the reduction-converted data. | 04-19-2012 |
20120095947 | VECTOR CLASSIFIER AND VECTOR CLASSIFICATION METHOD THEREOF - Provided is a vector classifier and a vector classification method. The vector classifier includes a vector compressor configured to compress an input vector; a support vector storage unit configured to store a compressed support vector; and a support vector machine operation unit configured to receive the compressed input vector and the compressed support vector and perform an arithmetic operation according to a classification determining equation. | 04-19-2012 |
20120099790 | OBJECT DETECTION DEVICE AND SYSTEM - Provided are an object detection device and system. The object detection device includes an outline image extraction unit, a feature vector calculation unit, and an object judgment unit. The outline image extraction unit extracts an outline image from an input image. The feature vector calculation unit calculates a feature vector from the outline image by using histogram of oriented gradients (HOG) representing a frequency distribution of gradient vectors with respect to pixels of the outline image, and pixel coordinate information varying according to a spatial distribution of the gradient vectors. The object judgment unit judges a target object corresponding to the feature vector with reference to pre-learned data. | 04-26-2012 |
20120148164 | IMAGE MATCHING DEVICES AND IMAGE MATCHING METHODS THEREOF - Provided is an image matching method of matching at least two images. The image matching method extracts feature points of a reference image and feature points of a target image, changes a feature point, selected from among the feature points of the reference image, to a reference point in the target image, sets a matching candidate region on the basis of the reference point, in the target image, and performs a similarity operation between the selected feature point in the reference image and a plurality of feature points included in the matching candidate region among the feature points of the target image. The image matching method decreases the number of similarity operations performed in the image matching operation, thereby guaranteeing a high-speed operation. | 06-14-2012 |
20120152296 | THERMOELECTRIC DEVICE, THERMOELECTIC DEVICE MODULE, AND METHOD OF FORMING THE THERMOELECTRIC DEVICE - Provided are a thermoelectric device, a thermoelectric device module, and a method of forming the thermoelectric device. The thermoelectric device includes a first conductive type first semiconductor nanowire including at least one first barrier region; a second conductive type second semiconductor nanowire including at least one second barrier region; a first electrode connected to one end of the first semiconductor nanowire; a second electrode connected to one end of the second semiconductor nanowire; and a common electrode connected to the other end of the first semiconductor nanowire and the other end of the second semiconductor nanowire. The first barrier region is greater than the first semiconductor nanowire in thermal conductivity, and the second barrier region is greater than the second semiconductor nanowire in thermal conductivity. | 06-21-2012 |
20120158248 | VEHICLE SAFETY SENSOR CONTROL DEVICE - A vehicle safety sensor control device is provided. The vehicle safety sensor control device may include a slope sensor portion sensing a slope of vehicle; a safety sensor portion sensing running safety information for a vehicle safety running; a sensing control angle generation portion sensing a sensing control angle from the sensed slope; and a safety sensor control portion controlling up and down direction angles of the safety sensor on the basis of a horizontal plane of vehicle depending on the sensing control angle. | 06-21-2012 |
20120159015 | DIRECT MEMORY ACCESS CONTROLLER AND OPERATING METHOD THEREOF - Disclosed is an operating method of a direct memory access (DMA) controller having first and second DMA channels. The operating method includes iteratively performing a DMA transfer operation of the first DMA channel based upon loop information and transfer information of the first DMA channel; iteratively performing a DMA transfer operation of the second DMA channel based upon loop information and transfer information of the second DMA channel; reconfiguring the transfer and loop information of the first and second DMA channels; and again performing the iteratively performing a DMA transfer operation of the first DMA channel and the iteratively performing a DMA transfer operation of the first DMA channel based upon the reconfigured transfer and loop information of the first and second DMA channels. | 06-21-2012 |
20120226831 | MEMORY SYSTEM AND INTEGRATED MANAGEMENT METHOD FOR PLURALITY OF DMA CHANNELS - Provided are a memory system and an integrated management method for a plurality of direct memory access (DMA) channels. The memory system includes a memory controller exchanging data with a memory and having a plurality of channels physically separated from each other, and a DMA controller having a plurality of DMA channels physically separated from each other and in contact with the plurality of channels of the memory controller, and exchanging data with the memory via the plurality of DMA channels and the memory controller. | 09-06-2012 |
20120314940 | IMAGE RECOGNITION DEVICE AND METHOD OF RECOGNIZING IMAGE THEREOF - An image recognition device in accordance with the inventive concept may include an input vector extraction part extracting an input vector from an input image; a compression vector conversion part converting the input vector into a compression vector using a projection vector; a training parameter generation part receiving a training vector to generate a training parameter using a projection vector obtained through a folding operation of the training vector; and an image classification part classifying the compression vector using the training vector to output image recognition data. | 12-13-2012 |
20130057424 | ANALOG-DIGITAL CONVERTER AND CONVERTING METHOD USING CLOCK DELAY - The present inventive concept relates to an analog-digital converter. The analog-digital converter includes a clock generating unit generating a clock signal; a clock delay adjusting unit outputting one of a first clock signal to a Kth clock signal according to a control signal; a capacitive digital-analog converting unit outputting a difference between the analog signal and a reference signal; a comparison unit judging whether an output of the capacitive digital-analog converting unit is 0, a positive number, or a negative number, in response to an output of the clock delay adjusting unit; and an SAR logic unit transferring an output of the comparison unit to the capacitive digital-analog converting unit in response to an output of the clock delay adjusting unit and performing a successive approximation operation to output the N-bit digital signal. | 03-07-2013 |
20130099868 | SOUND DETECTING CIRCUIT AND AMPLIFIER CIRCUIT THEREOF - Disclosed is a sound detecting circuit which includes a sensing unit configured to generate an AC signal in response to a sound pressure level of a sound signal; an amplification unit configured to amplify the AC signal; and a bias voltage generating unit configured to generate a bias voltage to be provided to the amplification unit. The bias voltage generating unit comprises a current source configured to provide a power current; and a current-voltage converting circuit configured to convert the power current into the bias voltage and to reduce a noise due to the power current. | 04-25-2013 |
20130103620 | FEATURE VECTOR CLASSIFICATION DEVICE AND METHOD THEREOF - Disclosed is a feature vector classification device which includes an initial condition setting unit; a variable calculating unit configured to receive a training vector and to calculate an error and a weight according to setting of the initial condition setting unit; a loop deciding unit configured to determine whether re-calculation is required, based on a comparison result between the calculated error and an error threshold; and a hyperplane generating unit configured to generate a hyperplane when an end signal is received from the loop deciding unit. | 04-25-2013 |
20130148456 | VOLTAGE REGULATOR WITH IMPROVED LOAD REGULATION AND VOLTAGE REGULATING METHOD - Provided is a voltage supply circuit using a charge pump. The voltage supply circuit enhances charge pump output voltage fluctuation characteristics depending on load variation of a charge pump voltage generator (load regulation characteristics) when receiving an operation power supply voltage of the charge pump through a regulator. The voltage supply circuit is configured to feed back fluctuation of a charge pump output voltage to a charge pump voltage regulator. The fluctuation of the charge pump output voltage is compensated through fluctuation of an output voltage of the charge pump to active enhance the load regulation characteristics. | 06-13-2013 |
20130154527 | HALL SENSOR SIGNAL GENERATING DEVICE - Disclosed is a hall sensor signal generating device which includes a rotor which has a magnetic property and rotates on the basis of a rotary axis; a hall sensor unit which is disposed to be spaced apart from a stator disposed outside the rotor; and a clock synchronization unit which receives a driving clock, performs synchronization between the driving clock and a hall sensor signal output from the hall sensor unit, and outputs the synchronized driving clock and the synchronized hall sensor signal. | 06-20-2013 |
20130156069 | PROCESS INDEPENDENT TEMPERATURE SENSOR BASED ON OSCILLATOR - The inventive concept discloses a new temperature sensor structure based on oscillator which is insensitive to a process change and improves an error rate of temperature output. The temperature sensor based on oscillator compares an oscillator circuit structure insensitive to a temperature change with an oscillator circuit structure having a frequency change in proportion to a temperature change to output a relative difference between the two oscillator circuit structures and thereby it is compensated itself. In the temperature sensor based on oscillator, a problem of performance reduction due to an external environment and a process deviation of temperature sensor is improved and an output distortion and temperature nonlinearity are effectively improved. Thus, since the temperature sensor based on oscillator has a structure of high performance, low power and low cost, it can be variously used in a detection equipment of temperature environment. | 06-20-2013 |
20130156319 | FEATURE VECTOR CLASSIFIER AND RECOGNITION DEVICE USING THE SAME - Provided are a feature vector extractor and a recognition device using the same. The feature vector classifier includes a feature vector extractor configured to generate a feature vector and a normalized value from an input image and output the feature vector and the normalized value; and a feature vector classifier configured to normalize the feature vector based on the normalized value and classify the normalized feature vector to recognize the input image. Thus, during extraction and classification of a feature vector, time required for the extraction and classification and the size of hardware required are significantly reduced. | 06-20-2013 |
20130156336 | IMAGE REGISTRATION DEVICE AND METHOD THEREOF - Disclosed is an image registration device which includes an image input unit which receives an image; an image information generating unit which generates a homography matrix from the input image; and a warping unit which registers an image based on the homography matrix. The registration information generating unit comprises a distance information generator which generates distance information on subjects of the input image; a distance information modeler which approximates the generated distance information; an overlap information generator which generates overlap information from the approximated distance information; a matching pair determiner which determines a matching pair from the overlap information; and a homography matrix generator which generates a homography matrix from the matching pair. | 06-20-2013 |
20130166801 | BUS BRIDGE APPARATUS - Disclosed is a bus bridge apparatus may prevent a transfer performance from being lowered due to bus protocol performance mismatch between interconnections. The bus bridge apparatus is used to transfer data to a slave device of a network-based interconnection from a master device of a bus-based interconnection, data of the master device may be buffered by an internal buffer, and may then be transferred to the slave device. At this time, lowering of a transfer efficiency may be prevented by converting a transfer timing of addresses and data to be optimized to a transfer protocol of the network-based interconnection through a protocol converter. | 06-27-2013 |
20130265414 | VEHICLE CRASH PREVENTION APPARATUS AND METHOD - The present invention relates to a vehicle accident prevention apparatus comprising a camera unit which photographs an image of a front view, an image recognition unit which processes the image of the front view to detect the registration number of a vehicle driving in front of the vehicle from a license plate of the vehicle driving in front of the vehicle, a wireless communication unit which receives accident prevention information containing an identifier and speed of the vehicle driving in front of the vehicle, a speed sensing unit which senses the speed of the vehicle equipped with the apparatus of the present invention, and a determining and control unit which identifies the vehicle driving in front of the vehicle by matching the registration number and the identifier of the vehicle driving in front of the vehicle, and generates a control signal for preventing vehicle accident by performing a speed comparison. | 10-10-2013 |
20130268467 | TRAINING FUNCTION GENERATING DEVICE, TRAINING FUNCTION GENERATING METHOD, AND FEATURE VECTOR CLASSIFYING METHOD USING THE SAME - Provided is a training function generating method. The method includes: receiving training vectors; calculating a training function from the training vectors; comparing a classification performance of the calculated training function with a predetermined classification performance and recalculating a training function on the basis of a comparison result, wherein the recalculating of the training function includes: changing a priority between a false alarm probability and a miss detection probability of the calculated training function; and recalculating a training function according to the changed priority. | 10-10-2013 |
20140079254 | MEMS MICROPHONE USING NOISE FILTER - An MEMS microphone is provided which includes a reference voltage/current generator configured to generate a DC reference voltage and a reference current; a first noise filter configured to remove a noise of the DC reference voltage; a voltage booster configured to generate a sensor bias voltage using the DC reference voltage the noise of which is removed; a microphone sensor configured to receive the sensor bias voltage and to generate an output value based on a variation in a sound pressure; a bias circuit configured to receive the reference current to generate a bias voltage; and a signal amplification unit configured to receive the bias voltage and the output value of the microphone sensor to amplify the output value. The first noise filter comprises an impedance circuit; a capacitor circuit connected to a output node of the impedance circuit; and a switch connected to both ends of the impedance circuit. | 03-20-2014 |
20140085122 | SUCCESSIVE APPROXIMATION REGISTER ANALOG-TO-DIGITAL CONVERTER - A successive approximation register analog-to-digital converter is provided which includes first and second capacitor arrays configured to generate first and second level voltages, respectively; a comparator configured to compare the first and second level voltages to output a comparison signal; SAR logic configured to generate a digital signal in response to the comparison signal; and a variable common mode selector configured to compare a first analog input voltage and a common mode voltage and to supply one of the first analog input voltage and the common mode voltage to top plates of the first and second capacitor arrays according to a comparison result. | 03-27-2014 |
20140132326 | PULSE NOISE SUPPRESSION CIRCUIT AND PULSE NOISE SUPPRESSION METHOD THEREOF - Provided is a pulse noise suppression circuit. The pulse noise suppression circuit includes a filter circuit converting an input signal of a pulse type into an increasing or decreasing filter signal, a level reset circuit resetting the filter signal in response to the input signal and an output signal and an output circuit converting the filter signal into the output signal of a pulse type, wherein the level reset circuit resets the filter signal to have a high level when the input signal and the output signal all have a high level, and resets the filter signal to have a low level when the input signal and the output signal all have a low level. | 05-15-2014 |
20140222320 | OPERATING METHOD OF ROAD GUIDE SYSTEM AND ROAD GUIDE METHOD OF PORTABLE DEVICE - Provided is an operating method of a road guide system including collecting traffic information around a portable device through the portable device; delivering, to a server, the traffic information collected from the portable device and travel path information; updating the delivered travel path information based on the delivered traffic information; and feeding back the updated travel path information from the server to the portable device. | 08-07-2014 |
20140286577 | IMAGE REGISTRATION DEVICE AND OPERATION METHOD OF THE SAME - Provided is an image registration device including a first feature vector magnitude calculating unit calculating magnitudes of feature vectors corresponding to any one first feature point among feature points of a reference image to create a first magnitude value, a second feature vector magnitude calculating unit calculating magnitudes of feature vectors corresponding to any one second feature point among feature points of a target image to create a second magnitude value, a magnitude difference calculating unit receiving the first and second magnitude values and calculating a difference between the received first and second magnitude values to create a third magnitude value, a first threshold value creating unit creating a first threshold value on the basis of the first magnitude value and a magnitude ratio, and a magnitude difference determining unit receiving the third magnitude value and the first threshold value, and determining a magnitude difference. | 09-25-2014 |