Patent application number | Description | Published |
20140162452 | BORDERLESS CONTACTS FOR SEMICONDUCTOR TRANSISTORS - Embodiments of the invention include methods of forming borderless contacts for semiconductor transistors. Embodiments may include providing a transistor structure including a gate, a spacer on a sidewall of the gate, a hard cap above the gate, a source/drain region adjacent to the spacer, and an interlevel dielectric layer around the gate, forming a contact hole above the source/drain region, forming a protective layer on portions of the hard cap and of the spacer exposed by the contact hole; deepening the contact hole by etching the interlevel dielectric layer while the spacer and the hard cap are protected by the protective layer, so that at least a portion of the source/drain region is exposed by the deepening of the contact hole; removing the protective layer; and forming a metal contact in the contact hole. | 06-12-2014 |
20150108589 | EMBEDDED INTERLEVEL DIELECTRIC BARRIER LAYERS FOR REPLACEMENT METAL GATE FIELD EFFECT TRANSISTORS - A semiconductor structure may be formed by forming a sacrificial gate above a substrate covered by a hard mask, depositing a first interlevel dielectric (ILD) layer above the sacrificial gate, recessing the first ILD layer to a thickness less than the height of the sacrificial gate, depositing an etch barrier layer above the first ILD layer, depositing a second ILD layer above the etch barrier layer, planarizing the second ILD layer and the etch barrier layer to expose the hard mask using the hard mask as a planarization stop, removing the hard mask and sacrificial gate to form a gate cavity, forming a replacement metal gate in the gate cavity, removing the second ILD layer, and planarizing the replacement metal gate using the etch barrier layer as a planarization stop. A supplementary electrode layer may be formed above the replacement metal gate prior to planarizing the replacement metal gate. | 04-23-2015 |
20150111373 | REDUCING GATE HEIGHT VARIATION IN RMG PROCESS - A method of forming transistors is provided. The method includes forming a plurality of transistor structures to have a plurality of dummy gates on a substrate. Each dummy gate is surrounded by sidewall spacers of a height, which is less than the dummy gate and is different for different transistor structures resulting in divots of different depths above the sidewall spacers. The method then deposits a conformal dielectric layer on top of the dummy gates and inside the divots of the plurality of transistor structures with the conformal dielectric layer having a thickness of at least half of a width of the divots, removes only a portion of the conformal dielectric layer that is on top of the dummy gates to expose the dummy gates; and replaces the dummy gates with a plurality of high-k metal gates. | 04-23-2015 |
Patent application number | Description | Published |
20140124841 | METHODS OF FORMING REPLACEMENT GATE STRUCTURES ON SEMICONDUCTOR DEVICES AND THE RESULTING DEVICE - One method includes forming first sidewall spacers adjacent opposite sides of a sacrificial gate structure and a gate cap layer, removing the gate cap layer and a portion of the first sidewall spacers to define reduced-height first sidewall spacers, forming second sidewall spacers, removing the sacrificial gate structure to thereby define a gate cavity, whereby a portion of the gate cavity is laterally defined by the second sidewall spacers, and forming a replacement gate structure in the gate cavity, wherein at least a first portion of the replacement gate structure is positioned between the second sidewall spacers. A device includes a gate structure positioned above the substrate between first and second spaced-apart portions of a layer of insulating material and a plurality of first sidewall spacers, each of which are positioned between the gate structure and on one of the first and second portions of the layer of insulating material. | 05-08-2014 |
20140134836 | DIELECTRIC CAP LAYER FOR REPLACEMENT GATE WITH SELF-ALIGNED CONTACT - Embodiments of the present invention provide a method of forming borderless contact for transistors. The method includes forming a sacrificial gate structure embedded in a first dielectric layer, the sacrificial gate structure including a sacrificial gate and a second dielectric layer surrounding a top and sidewalls of the sacrificial gate; removing a portion of the second dielectric layer that is above a top level of the sacrificial gate to create a first opening surrounded directly by the first dielectric layer; removing the sacrificial gate exposed by the removing of the portion of the second dielectric layer to create a second opening surrounded by a remaining portion of the second dielectric layer; filling the second opening with one or more conductive materials to form a gate of a transistor; and filling the first opening with a layer of dielectric material to form a dielectric cap of the gate of the transistor. | 05-15-2014 |
20140242797 | SEMICONDUCTOR FABRICATION METHOD USING STOP LAYER - A method of making a semiconductor assembly including the steps of: (i) providing an initial-state assembly including: (a) a fin layer, and (b) a hard mask layer located on top of at least a portion of the fin layer; (ii) performing a first material removal on the initial-state assembly, by CMP, to yield a second-state assembly; and (iii) performing a second material removal on the second-state assembly to yield a third-state assembly. In the first material-removal step: (i) any remaining portion of the soft sacrificial layer is removed, (ii) a portion of the fin layer is removed, and (iii) the lower portion of the hard mask layer is used as a stop layer for the second material removal. | 08-28-2014 |
20150076606 | SEMICONDUCTOR DEVICE WITH LOW-K SPACER - A semiconductor device includes gates and a low-k spacer. The low-k spacer includes low-k spacer portions formed upon the gate sidewalls and a low-k spacer portion formed upon a top surface of an underlying substrate adjacent to the gates. When a structure has previously undergone a gate processing fabrication stage, the gates and at least a portion of the top surface of the substrate may be exposed thereby allowing the formation of the low-k spacer. This exposure may include removing any original gate spacers, removing an original liner formed upon the original spacers, and removing any original fill material formed upon the liner. | 03-19-2015 |
20150206844 | INTEGRATED CIRCUITS HAVING GATE CAP PROTECTION AND METHODS OF FORMING THE SAME - Integrated circuits and methods of forming integrated circuits are provided. An integrated circuit includes a gate electrode structure overlying a base substrate. The gate electrode structure includes a gate electrode, with a cap disposed over the gate electrode and sidewall spacers disposed adjacent to sidewalls of the gate electrode structure. A source and drain region are formed in the base substrate aligned with the gate electrode structure. A first dielectric layer is disposed adjacent to the sidewall spacers. The sidewall spacers and the cap have recessed surfaces below a top surface of the first dielectric layer, and a protecting layer is disposed over the recessed surfaces. A second dielectric layer is disposed over the first dielectric layer and the protecting layer. Electrical interconnects are disposed through the first dielectric layer and the second dielectric layer, and the electrical interconnects are in electrical communication with the respective source and drain regions. | 07-23-2015 |
Patent application number | Description | Published |
20150255543 | STRAINED FinFET BY EPITAXIAL STRESSOR INDEPENDENT OF GATE PITCH - A semiconductor device fabrication process includes forming a fin and a plurality of gates upon a semiconductor substrate, forming sacrificial spacers upon opposing gate sidewalls, forming a mask upon an upper surface of the fin between neighboring gates, removing the sacrificial spacers, recessing a plurality of regions of the fin to create a dummy fin and fin segments, removing the mask, and epitaxially merging the dummy fin and fin segments. The fins may be partially recessed prior to forming the sacrificial spacers. The device may include the substrate, gates, fin segments each associated with a particular gate, the dummy fin between a fin segment pair separated by the wider pitch, and merged epitaxy connecting the dummy fin and the fin segment pair. The dummy fin may serve as a filler between the fin segment pair and may add epitaxial growth planes to allow for epitaxial merging within the wider pitch. | 09-10-2015 |
20150255556 | SEMICONDUCTOR DEVICE WITH LOW-K GATE CAP AND SELF-ALIGNED CONTACT - A semiconductor device includes at least a gate formed upon a semiconductor substrate, a contact trench self aligned to the gate, and a multilayered gate caps comprising a first gate cap formed upon each gate and a low-k gate cap formed upon the first gate cap. The multilayered gate cap may electrically isolate the gate from a self aligned contact formed by filling the contact trench with electrically conductive material. The multilayered gate cap reduces parasitic capacitance formed between the source-drain region, gate, and multilayered gate cap that may adversely impact device performance and device power consumption. | 09-10-2015 |
20150349123 | STRAINED FinFET BY EPITAXIAL STRESSOR INDEPENDENT OF GATE PITCH - A semiconductor device is fabricated by forming a fin and a plurality of gates upon a semiconductor substrate, forming sacrificial spacers upon opposing gate sidewalls, forming a mask upon an upper surface of the fin between neighboring gates, removing the sacrificial spacers, recessing a plurality of regions of the fin to create a dummy fin and fin segments, removing the mask, and epitaxially merging the dummy fin and fin segments. The fins may be partially recessed prior to forming the sacrificial spacers. The device may include the substrate, gates, fin segments each associated with a particular gate, the dummy fin between a fin segment pair separated by the wider pitch, and merged epitaxy connecting the dummy fin and the fin segment pair. The dummy fin may serve as a filler between the fin segment pair and may add epitaxial growth planes to allow for epitaxial merging within the wider pitch. | 12-03-2015 |
20150364361 | SHALLOW TRENCH ISOLATION REGIONS MADE FROM CRYSTALLINE OXIDES - A method of manufacturing a semiconductor device that involves etching a trench in a semiconductor substrate, epitaxially growing a crystalline structure in the trench and forming semiconductor structures on either side of the crystalline structure. Crystalline oxides may include rare earth oxides, aluminum oxides or Perovskites. | 12-17-2015 |
Patent application number | Description | Published |
20150023252 | METHOD TO USE EXISTING NAS SIGNALING CONNECTION FOR PENDING UPLINK SIGNALING/ DATA AFTER TAU ACCEPT - A method and system to use existing Non-access stratum (NAS) signaling connection for pending uplink signaling/data after Tracking Area Update Procedure (TAU) complete is disclosed. The proposed method handles the EPS Session Management (ESM), Short Message Service (SMS) or voice call or data when a User Equipment (UE) is waiting for TAU accept. The method allows UE to inform the network with specific Information Element (IE) in TAU complete message, so that the network will take the next action. This will help to provide quick services to the user. Using the “CONN REQ TYPE” IE, in TAU complete, to handle all abnormal Cases for Circuit Switches (CS) services/data services in E-UTRAN (Evolved UTRAN) network. | 01-22-2015 |
20150126189 | METHOD AND SYSTEM FOR OPTIMIZING CLOSED SUBSCRIBER GROUP (CSG) SELECTION IN WIRELESS COMMUNICATION - The various embodiments herein provide a method and system for optimizing Closed Subscriber Group (CSG) selection in wireless communication. The method comprising steps of initiating, by a user equipment (UE), a manual CSG selection, verifying if a manual CSG selection request is new, storing a registered public land mobile network (RPLMN) and a corresponding public land mobile network (PLMN) Selection mode if the CSG selection request is new, changing a PLMN selection mode and the CSG selection mode to MANUAL, registering the UE on to a user selected CSG cell, storing one or more parameters associated with the user selected CSG cell if the registration is successful irrespective of CSG cell belonging to RPLMN or different PLMN and selecting the user selected CSG cell using a stored PLMN ID and a CSG ID combination in the current PLMN selection mode during power off and power on. | 05-07-2015 |
20150264604 | METHOD AND APPARATUS FOR PROCESSING A CIRCUIT-SWITCHED (CS) CALL WHILE CAMPED ON A CSG CELL - A method and an apparatus are provided for processing a Circuit-Switched (CS) call by User Equipment (UE) that is camped on a CSG cell, when a manually selected CSG cell is in a Public Land Mobile Network (PLMN), which is different from a Registered PLMN (RPLMN). The method includes registering, by the UE, with a manually selected Closed Subscriber Group (CSG) cell of a Public Land Mobile Network (PLMN), which is different from a Registered PLMN (RPLMN) of the UE; detecting the CS call; and processing the CS call in a non-CSG cell, when the manually selected CSG cell is unable to process the CS call. | 09-17-2015 |
20150289114 | METHOD AND SYSTEM FOR OPTIMIZED SCANNING IN MOBILE COMMUNICATION TERMINAL WITH SINGLE/MULTI SIM CARDS WITH SINGLE RF - A method and user equipment for handling a Public Land Mobile Network (PLMN) selection in a mobile communication network is provided. The method includes obtaining, by a User Equipment (UE), a PLMN list of one or more Radio Access Technologies (RATs) comprising a list of available PLMNs, when the UE performs a Manual Closed Subscriber Group (CSG) selection, initiating a PLMN list validation timer, and reusing the previously obtained PLMN list, when at least one predefined event is triggered and the PLMN list validation timer is running. The at least one predefined event comprises at least one of Home Public Land Mobile Network (HPLMN) timer expiration, a manual PLMN selection, the manual CSG selection, and autonomous CSG selection. | 10-08-2015 |
20150351023 | APPARATUS AND METHOD OF SELECTING PLMN IN MOBILE COMMUNICATION SYSTEM - An apparatus and a method of selecting Public Land Mobile Networks (PLMNs) in a manual PLMN selection mode are provided. The method includes selecting a PLMN as a network that the terminal will be attached to in a manual PLMN selection mode, storing the selected PLMN in a user selection PLMN list, and selecting, when the terminal attempts recovery to receive normal services in a limited service state, a PLMN to be attached to a network based on at least one PLMN included in the stored user selection PLMN list. | 12-03-2015 |
20150358862 | METHOD AND SYSTEM TO REDUCE DELAY IN CIRCUIT SWITCH FALLBACK (CSFB) PROCEDURES WHILE OPERATING WITH MULTI/DUAL SIMS - A method of reducing delay in Circuit Switched FallBack (CSFB) in a Radio Access Technology (RAT) communications network. The method includes initiating, by a terminal, a combined attach procedure by sending an attach request message to the RAT communications network, receiving, by the terminal, an attach accept message along with Location Area Identification (LAI) information from the network in response to the attach request message, checking, by the terminal, network identifier information in a RAT information table based on the received LAI, and selecting a mobile network based on the network identifier information to trigger establishment of a circuit-switched call. | 12-10-2015 |