Surdeanu
Mihai Surdeanu, Tucson, AZ US
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20140180934 | Systems and Methods for Using Non-Textual Information In Analyzing Patent Matters - Aspects of the present invention comprise using non-textual information in analyses of patent matters. In embodiments, patent matter similarity may comprise a combination of two or more metrics: (a) a metric that measures the textual similarity between an input patent portfolio and patent matters; (b) a metric that measures the behavior between portfolio patents and other patent matters at issue (e.g., which patents are asserted in the same proceeding with portfolio patents); (c) a metric that measures the textual similarity between the textual description and patent matters; and (d) a metric that inspects which patent matters are placed at issue by peer companies. In embodiments, patent matter similarity may be determined using textual similarity in combination with non-textual information. | 06-26-2014 |
20140279583 | Systems and Methods for Classifying Entities - Presented herein are systems and method for generating and/or using a classifier that can identify or classify entities, such as (by way of illustration and not limitation) whether an entity in a contested proceeding is a patent monetizing entity (PME). In embodiments, using features extracted from various sources such as, by way of example and not limitation, the entities' litigation behavior, the patents they asserted, and their presence on the web, a classifier can correctly separates PMEs from operating companies with a reasonable degree of accuracy. In embodiments, one or more classifier may be trained to classify or label entities into one of a plurality of classes. Such classifiers can be useful tools for policy makers and others, allowing them to gain a clearer picture of contested proceedings filed to date and assessing newly filed cases in real time. | 09-18-2014 |
Radu Surdeanu, Leuven BE
Patent application number | Description | Published |
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20150357407 | APPARATUSES AND METHODS INCLUDING A SUPERJUNCTION TRANSISTOR - Aspects of the present disclosure are directed toward apparatuses, methods, and systems that include at least two regions of a first semiconductor material and at least two regions of second semiconductor material that are alternatively interleaved. Additionally, the apparatuses, methods, and systems include a first electrode and a second electrode that can operate both as a source and drain. The apparatuses, methods, and systems also include a first gate electrode having multiple portions on the first semiconductor material and a second gate electrode having multiple portions on the second semiconductor material that bidirectionally control current flow between the first electrode and the second electrode. | 12-10-2015 |
Radu Catalin Surdeanu, Heverlee BE
Patent application number | Description | Published |
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20110309457 | Method for Forming a Notched Gate Insulator for Advanced MIS Semiconductor Devices and Devices Thus Obtained - Methods of providing a semiconductor device with a control electrode structure having a controlled overlap between control electrode and first and second main electrode extensions without many spacers are disclosed. A preferred method provides a step of etching back an insulating layer performed after amorphizing and implanting the main electrode extensions. Preferably, the step that amorphizes the extensions also partly amorphizes the insulating layer. Because etch rates of amorphous insulator and crystalline insulator differ, the amorphized portion of the insulating layer may serve as a natural etch stop to enable even better fine-tuning of the overlap. Corresponding semiconductor devices are also provided. | 12-22-2011 |