Patent application number | Description | Published |
20120101609 | Audio Auditioning Device - Accurate “Mixing” of a sound signal has hitherto required a recording studio environment. Currently, both professional music producers facing budgetary limitations and amateur music makers without access to such meet a difficulty in producing music which has been correctly “Mixed” and “Auditioned”. We therefore propose a “Mixing” and “Mix Audition” tool, which can use standard headphones as the method of reproducing the direct sound, together with a DSP system that can be used with a computer based music production system to simulate specific listening experiences. The present invention therefore provides an audio auditioning device comprising a sound input, a sound output, a digital signal processor, and a library of stored digital signal processor effects, wherein the digital signal processor is adapted to apply a chosen effect from the library to a sound signal provided to the device via the sound input and deliver this to the output, and the library includes a plurality of digital signal processor effects representing the effect on a sound signal of reproduction in different environments. The digital signal processor applies the chosen effect in real time. The effects can include a home stereo, a home multi channel cinema, a large cinema, a concert hall, a car interior, and a radio receiver, or the like. The audio auditioning device can be combined with a computing device which includes a stored sound signal, mixing software adapted to adjust the mix of the stored sound signal, and a sound output connected to the sound input of the audio auditioning device. | 04-26-2012 |
Patent application number | Description | Published |
20110109378 | Method and Device For Supplying Power to a Microelectronic Chip - A method and a device for supplying power to one or more microelectronic chips. The method comprises the steps of reading a process characteristic parameter associated with the chip from a non-volatile storage, wherein the process characteristic parameter represents a manufacturing process characteristics of the chip; determining a minimal voltage (VDD_min) based on the parameter; and supplying electric power to the chip ( | 05-12-2011 |
20120130657 | MEASURING POWER CONSUMPTION IN AN INTEGRATED CIRCUIT - A method for determining power consumption of a power domain within an integrated circuit is presented. In a first step, a local power supply impedance profile (Z(f)) of this power domain is determined. Subsequently, a local time-resolved power supply voltage (U(t)) is measured while a well-defined periodic activity is executed in power domain. A set of time-domain measured voltage data (U(t)) is thus accumulated and transformed into the frequency domain to yield a voltage spectrum (U(f)). A current spectrum I(t) is calculated from this voltage profile (U(f)) by using the power supply impedance profile Z(f) of this power domain as I(t)=F | 05-24-2012 |
20120147559 | INTEGRATED CIRCUIT PACKAGE CONNECTED TO AN OPTICAL DATA TRANSMISSION MEDIUM USING A COOLANT - An integrated circuit coupling device includes an integrated circuit package; and an optical data transmission medium connected to the integrated circuit package, and comprising a movable coolant, adapted to remove heat from the integrated circuit package, in operation. | 06-14-2012 |
20120148187 | INTEGRATED CIRCUIT PACKAGE CONNECTED TO A DATA TRANSMISSION MEDIUM - An integrated circuit coupling device includes an integrated circuit package with N integrated circuit layers (L | 06-14-2012 |
Patent application number | Description | Published |
20120013353 | Method And System For Impedance Measurement In An Integrated Circuit - A method for determining a power supply impedance profile (|Z(f)|) at a predetermined load location within an electronic system. A repetitive activity (such as a modulated clock tree signal) is applied in the load location, and the local power supply voltage (U(t)) caused by this repetitive activity is measured. Rather than measuring the corresponding current consumption (I(t)) caused by the repetitive activity, the current consumption is calculated analytically. The local power supply impedance profile (|Z(f)|) is calculated as the ratio of the frequency-domain voltage and current consumption magnitudes (|U(f)|, |I(f)|) of the measured power supply voltage (U(t)) and the calculated current consumption (I(t)). | 01-19-2012 |
20120013356 | Method And System For Performing Self-Tests In An Electronic System - A method and system for performing a self-test of power supply quality for an integrated circuit chip within an electronic system. The electronic system is subjected to a well-defined repetitive activity, such as by using an amplitude modulated system clock tree. With the repetitive activity causing current consumption within the chip, time-domain local power supply voltage (U(t)) is measured for a location on the chip. A set of time-domain measured voltage data (U(t)) is accumulated and transformed into the frequency domain to yield a local voltage profile (U(f)). The local voltage profile (U(f)) is compared with a reference voltage profile (U | 01-19-2012 |
20120105144 | Optimized Semiconductor Packaging in a Three-Dimensional Stack - A mechanism is provided for optimizing semiconductor packing in a three-dimensional (3D) very-large-scale integration (VLSI) device. The 3D VLSI device comprises a processor layer coupled, via a first set of coupling devices, to at least one signaling and input/output (I/O) layer. The 3D VLSI device further comprises a power delivery layer coupled, via a second set of coupling devices, to the processor layer. In the 3D VLSI device the power delivery layer is dedicated to only delivering power and does not provide data communication signals to the elements of the three-dimensional VLSI device, and the at least one signaling and input/output (I/O) layer is dedicated to only transmitting the data communication signals to and receiving the data communications signals from the processor layer and does not provide power to the elements of the processor layer. | 05-03-2012 |
20120105145 | Thermal Power Plane for Integrated Circuits - A mechanism is provided for a thermal power plane that delivers power and constitutes minimal thermal resistance. The mechanism comprises a processor layer coupled, via a first set of coupling devices, to a signaling and input/output (I/O) layer and a power delivery layer coupled, via a second set of coupling devices, to the processor layer. In the mechanism, the power delivery layer is dedicated to only delivering power and does not provide data communication signals to the elements of the mechanism. In the mechanism, the power delivery layer comprises a plurality of conductors, a plurality of insulating materials, one or more ground planes, and a plurality of through laminate vias. In the mechanism, the signaling and input/output (I/O) layer is dedicated to only transmitting the data communication signals to and receiving the data communications signals from the processor layer and does not provide power to the elements of the processor layer. | 05-03-2012 |
20120106074 | Heat Sink Integrated Power Delivery and Distribution for Integrated Circuits - A mechanism is provided for integrated power delivery and distribution via a heat sink. The mechanism comprises a processor layer coupled to a signaling and input/output (I/O) layer via a first set of coupling devices and a heat sink coupled to the processor layer via a second set of coupling devices. In the mechanism, the heat sink comprises a plurality of grooves on one face, where each groove provides either a path for power or a path for ground to be delivered to the processor layer. In the mechanism, the heat sink is dedicated to only delivering power and does not provide data communication signals to the elements of the mechanism and the signaling and I/O layer is dedicated to only transmitting the data communication signals to and receiving the data communications signals from the processor layer and does not provide power to the elements of the processor layer. | 05-03-2012 |
20120189243 | TRANSFERRING HEAT THROUGH AN OPTICAL LAYER OF INTEGRATED CIRCUITRY - An integrated circuitry structure includes at least first and second regions. An optical layer includes optical waveguides. A heat-conductive material transfers heat from at least the second region through the optical layer to a heat sink. | 07-26-2012 |
20120290999 | Optimized Semiconductor Packaging in a Three-Dimensional Stack - A mechanism is provided for optimizing semiconductor packing in a three-dimensional (3D) very-large-scale integration (VLSI) device. The 3D VLSI device comprises a processor layer coupled, via a first set of coupling devices, to at least one signaling and input/output (I/O) layer. The 3D VLSI device further comprises a power delivery layer coupled, via a second set of coupling devices, to the processor layer. In the 3D VLSI device the power delivery layer is dedicated to only delivering power and does not provide data communication signals to the elements of the three-dimensional VLSI device, and the at least one signaling and input/output (I/O) layer is dedicated to only transmitting the data communication signals to and receiving the data communications signals from the processor layer and does not provide power to the elements of the processor layer. | 11-15-2012 |
20130343200 | NETWORK POWER FAULT DETECTION - Network power fault detection. At least one first network device is instructed to temporarily disconnect from a power supply path of a network, and at least one characteristic of the power supply path of the network is measured at a second network device connected to the network while the at least one first network device is temporarily disconnected from the network. | 12-26-2013 |
20140095121 | TRANSFERRING HEAT THROUGH AN OPTICAL LAYER OF INTEGRATED CIRCUITRY - A method in a computer-aided design system for generating a functional design model of an integrated circuitry structure including generating a functional representation of at least first and second regions of the integrated circuitry structure, generating a functional representation of an optical layer comprising optical waveguides, and generating a functional representation of a heat-conductive material for transferring heat from at least the second region through the optical layer to a heat sink. | 04-03-2014 |
20150221575 | TRANSFERRING HEAT THROUGH AN OPTICAL LAYER OF INTEGRATED CIRCUITRY - A computer program product or hardware description language (“HDL”) design structure in a computer-aided design system for generating a functional design model of an integrated circuitry structure including generating a functional representation of at least first and second regions of the integrated circuitry structure, generating a functional representation of an optical layer comprising optical waveguides, and generating a functional representation of a heat-conductive material for transferring heat from at least the second region through the optical layer to a heat sink. | 08-06-2015 |
Patent application number | Description | Published |
20100070021 | Stenting Ring with Marker - A stenting ring made of a tube or rolled-up sheet that has a characteristic wall thickness. The ring defines a lumen and is equipped with at least one marker made of a material different from that of the ring. The ring is expansible from a radially compact disposition with a relatively small circumference to a radially expanded disposition with a relatively large circumference. The ring exhibits in the compact disposition a serpentine arrangement of succeeding struts lying in alternate opposite directions to the longitudinal axis of the lumen. The marker has a thickness in the radial direction of the ring that is less than the characteristic wall thickness, and has a width that extends circumferentially around an arc of the ring. The marker is attached to the ring at a zone located at a point intermediate in the extent of said arc. The marker overlaps with a respective one of said struts, at each end of its circumferential arc, when the ring is in the compact disposition, the respective struts moving away from each other, and from the marker, when the ring expands towards said radially expanded disposition. | 03-18-2010 |
20120041542 | IMPLANT WITH ATTACHED ELEMENT AND METHOD OF MAKING SUCH AN IMPLANT - A tubular implant having an axial end to which is attached a ring of spoons of a material different from that of the implant. In another aspect, the invention provides a method of attaching elements to an axial end of a tubular implant comprising the steps of providing said elements on one end of a support tube having a radius substantially that of the implant in its unexpanded configuration, abutting the implant and elements end-to-end, fixing the elements to the implant, and parting the elements from the support tube. In a third aspect, the invention provides an implant carrying an element of another material, the element and implant having complementary tapered mating surfaces for achieving a taper form-fit of the element onto the implant. | 02-16-2012 |
20150073532 | Implant with Attached Element and Method of Making Such an Implant - A stent having an axial end to which is attached a ring of spoons of a material different from that of the stent. In one aspect, the ring of spoons is connected to the axial end through a plurality of complementary male-female form-fitting portions. In one aspect, the ring of spoons include parallel straight side edges. In one aspect, each of the side edges lies within a first distance from a facing side edge of an adjacent spoon in a stent delivery configuration, and each of the side edges lies within a second distance, greater than the first distance, from the facing side edge of an adjacent spoon in a stent deployed configuration. | 03-12-2015 |