Patent application number | Description | Published |
20080224206 | METAL OXIDE SEMICONDUCTOR FIELD EFFECT TRANSISTORS (MOSFETS) INCLUDING RECESSED CHANNEL REGIONS AND METHODS OF FABRICATING THE SAME - Unit cells of metal oxide semiconductor (MOS) transistors are provided having an integrated circuit substrate and a MOS transistor on the integrated circuit substrate. The MOS transistor includes a source region, a drain region and a gate. The gate is between the source region and the drain region. A channel region is provided between the source and drain regions. The channel region has a recessed region that is lower than bottom surfaces of the source and drain regions. Related methods of fabricating transistors are also provided. | 09-18-2008 |
20080233693 | COMPLEMENTARY METAL-OXIDE SEMICONDUCTOR (CMOS) DEVICES INCLUDING A THIN-BODY CHANNEL AND DUAL GATE DIELECTRIC LAYERS AND METHODS OF MANUFACTURING THE SAME - A complementary metal-oxide semiconductor (CMOS) device includes an NMOS thin body channel including a silicon epitaxial layer. An NMOS insulating layer is formed on a surface of the NMOS thin body channel and surrounds the NMOS thin body channel. An NMOS metal gate is formed on the NMOS insulating layer. The CMOS device further includes a p-channel metal-oxide semiconductor (PMOS) transistor including a PMOS thin body channel including a silicon epitaxial layer. A PMOS insulating layer is formed on a surface of and surrounds the PMOS thin body channel. A PMOS metal gate is formed on the PMOS insulating layer. The NMOS insulating layer includes a silicon oxide layer and the PMOS insulating layer includes an electron-trapping layer, the NMOS insulating layer includes a hole trapping dielectric layer and the PMOS insulating layer includes a silicon oxide layer, or the NMOS insulating layer includes a hole-trapping dielectric layer and the PMOS insulating layer includes an electron-trapping dielectric layer. | 09-25-2008 |
20080237641 | Surrounded-Channel Transistors with Directionally Etched Gate or Insulator Formation Regions - An elongate stacked semiconductor structure is formed on a substrate. The stacked semiconductor structure includes a second semiconductor material region disposed on a first semiconductor material region. The first semiconductor material region is selectively doped to produce spaced-apart impurity-doped first semiconductor material regions and a lower dopant concentration first semiconductor material region therebetween. Etching exposes a portion of the second semiconductor material region between the impurity-doped first semiconductor material regions. The etching removes at least a portion of the lower dopant concentration first semiconductor material region to form a hollow between the substrate and the portion of the second semiconductor material region between the impurity-doped first semiconductor material regions. An insulation layer that surrounds the exposed portion of the second semiconductor material region between the impurity-doped first semiconductor material regions is formed. The hollow may be filled with a gate electrode that completely surrounds the exposed portion of the second semiconductor material region, or the gate electrode may partially surround the exposed portion of the second semiconductor material region and an insulation region may be formed in the hollow. | 10-02-2008 |
20100044784 | Vertical Channel Fin Field-Effect Transistors Having Increased Source/Drain Contact Area and Methods for Fabricating the Same - A fin field-effect transistor (FinFET) device includes a fin-shaped active region having first and second source/drain regions therein and a channel region therebetween vertically protruding from a semiconductor substrate. A gate electrode is formed on an upper surface and sidewalls of the channel region. First and second source/drain contacts are formed on respective upper surfaces and sidewalls of the first and second source/drain regions of the fin-shaped active region at opposite sides of the gate electrode. The channel region may be narrower than the first and second source/drain regions of the fin-shaped active region. | 02-25-2010 |
20100105181 | METHODS OF FABRICATING VERTICAL TWIN-CHANNEL TRANSISTORS - A transistor includes first and second pairs of vertically overlaid source/drain regions on a substrate. Respective first and second vertical channel regions extend between the overlaid source/drain regions of respective ones of the first and second pairs of overlaid source/drain regions. Respective first and second insulation regions are disposed between the overlaid source/drain regions of the respective first and second pairs of overlaid source/drain regions and adjacent respective ones of the first and second vertical channel regions. Respective first and second gate insulators are disposed on respective ones of the first and second vertical channel regions. A gate electrode is disposed between the first and second gate insulators. The first and second vertical channel regions may be disposed near adjacent edges of the overlaid source/drain regions. | 04-29-2010 |
20100127328 | SEMICONDUCTOR-ON-INSULATOR (SOI) DEVICES USING VOID SPACES - An SOI substrate is fabricated by providing a substrate having a sacrificial layer thereon, an active semiconductor layer on the sacrificial layer remote from the substrate and a supporting layer that extends along at least two sides of the active semiconductor layer and the sacrificial layer and onto the substrate, and that exposes at least one side of the sacrificial layer. At least some of the sacrificial layer is etched through the at least one side thereof that is exposed by the supporting layer to form a void space between the substrate and the active semiconductor layer, such that the active semiconductor layer is supported in spaced-apart relation from the substrate by the supporting layer. The void space may be at least partially filled with an insulator lining. | 05-27-2010 |
20100129976 | Methods of Fabricating Electromechanical Non-Volatile Memory Devices - Electromechanical non-volatile memory devices are provided including a semiconductor substrate having an upper surface including insulation characteristics. A first electrode pattern is provided on the semiconductor substrate. The first electrode pattern exposes portions of a surface of the semiconductor substrate therethrough. A conformal bit line is provided on the first electrode pattern and the exposed surface of semiconductor substrate. The bit line is spaced apart from a sidewall of the first electrode pattern and includes a conductive material having an elasticity generated by a voltage difference. An insulating layer pattern is provided on an upper surface of the bit line located on the semiconductor substrate. A second electrode pattern is spaced apart from the bit line and provided on the insulating layer pattern. The second electrode pattern faces the first electrode pattern. Related methods are also provided. | 05-27-2010 |
20100155827 | Semiconductor device having a multi-channel type MOS transistor - In a method of manufacturing a semiconductor device, an active channel pattern is formed on a substrate. The active channel pattern includes preliminary gate patterns and single crystalline silicon patterns that are alternately stacked with each other. A source/drain layer is formed on a sidewall of the active channel pattern. Mask pattern structures including a gate trench are formed on the active channel pattern and the source/drain layer. The patterns are selectively etched to form tunnels. The gate trench is then filled with a gate electrode. The gate electrode surrounds the active channel pattern. The gate electrode is protruded from the active channel pattern. The mask pattern structures are then removed. Impurities are implanted into the source/drain regions to form source/drain regions. A silicidation process is carried out on the source/drain regions to form a metal silicide layer, thereby completing a semiconductor device having a MOS transistor. | 06-24-2010 |
20100167474 | Methods of Forming Semiconductor-On-Insulating (SOI) Field Effect Transistors with Body Contacts - Semiconductor-on-insulator (SOI) field effect transistors include a semiconductor substrate and a first semiconductor active region on a first portion of a surface of the substrate. A first electrically insulating layer is provided. This first electrically insulating layer extends on a second portion of the surface of the substrate and also on a first sidewall of the first semiconductor active region. A second electrically insulating layer is provided, which extends on a third portion of the surface of the semiconductor substrate. The second electrically insulating layer also extends on a second sidewall of the first semiconductor active region. A second semiconductor active region is provided on the first semiconductor active region. The second semiconductor active region extends on the first semiconductor active region and on ends of the first and second electrically insulating layers. Source and drain regions are also provided, which are electrically coupled to opposite ends of the second semiconductor active region. An insulated gate electrode extends on the second semiconductor active region and opposite the first semiconductor active region. | 07-01-2010 |
20110079831 | Metal Oxide Semiconductor Field Effect Transistors (MOSFETS) Including Recessed Channel Regions - Unit cells of metal oxide semiconductor (MOS) transistors are provided having an integrated circuit substrate and a MOS transistor on the integrated circuit substrate. The MOS transistor includes a source region, a drain region and a gate. The gate is between the source region and the drain region. A channel region is provided between the source and drain regions. The channel region has a recessed region that is lower than bottom surfaces of the source and drain regions. Related methods of fabricating transistors are also provided. | 04-07-2011 |
20110189829 | METHODS OF FABRICATING NONVOLATILE MEMORY DEVICES HAVING STACKED STRUCTURES - A memory device includes a first active region on a substrate and first and second source/drain regions on the substrate abutting respective first and second sidewalls of the first active region. A first gate structure is disposed on the first active region between the first and second source/drain regions. A second active region is disposed on the first gate structure between and abutting the first and second source/drain regions. A second gate structure is disposed on the second active region overlying the first gate structure. | 08-04-2011 |
20110318890 | METHODS OF FORMING SEMICONDUCTOR-ON-INSULATING (SOI) FIELD EFFECT TRANSISTORS WITH BODY CONTACTS - Semiconductor-on-insulator (SOI) field effect transistors include a semiconductor substrate and a first semiconductor active region on a first portion of a surface of the substrate. A first electrically insulating layer is provided. This first electrically insulating layer extends on a second portion of the surface of the substrate and also on a first sidewall of the first semiconductor active region. A second electrically insulating layer is provided, which extends on a third portion of the surface of the semiconductor substrate. The second electrically insulating layer also extends on a second sidewall of the first semiconductor active region. A second semiconductor active region is provided on the first semiconductor active region. The second semiconductor active region extends on the first semiconductor active region and on ends of the first and second electrically insulating layers. Source and drain regions are also provided, which are electrically coupled to opposite ends of the second semiconductor active region. An insulated gate electrode extends on the second semiconductor active region and opposite the first semiconductor active region. | 12-29-2011 |
20130124438 | METHOD OF RECOGNIZING PATTERNS BASED ON MARKOV CHAIN HIDDEN CONDITIONAL RANDOM FIELD MODEL - Provided is a method of recognizing patterns based on a hidden conditional random fields model to which full-Gaussian covariance has been applied. The method includes dividing a training input signal and outputting a frame sequence, extracting a feature vector from the frame sequence, calculating a parameter through a conditional random fields model to which Gaussian covariance has been applied using the feature vector, receiving, by the hidden conditional random fields model to which the parameter has been applied, a feature vector extracted from a test input signal measured for an actual pattern to infer a label indicating the actual pattern, and proposing a method of calculating gradient values for a conditional probability vector, a transition probability vector, a Gaussian mixture weight, a mean of Gaussian distributions, and covariance of the Gaussian distributions, as an analysis method. | 05-16-2013 |
20130132312 | DATA PROCESSING METHOD AND APPARATUS FOR CLINICAL DECISION SUPPORT SYSTEM - Provided is a data processing method for clinical decision support system. The data processing method provides an algorithm capable of performing parsing based on an Ontology technique and automatically updating rule database in order to reduce time and labor overloads accompanied by update of the rule database. According to an aspect, the data processing method includes inferring input data having a natural language format based on an Ontology technique to recognize at least one input rule included in the input data; inferring storage data having a natural language format and stored in rule database based on the Ontology technique to recognize at least one storage rule associated with the input rule from the storage data; comparing the input rule to the storage rule using a Self Evolutionary Rule-base algorithm; and updating the storage data stored in the rule database to the input data according to the result of the comparison. | 05-23-2013 |