Patent application number | Description | Published |
20080268595 | NAND flash memory devices and methods of fabricating the same - A NAND includes a device isolation pattern disposed in a region of a substrate defining a plurality of active regions. Memory transistors having memory gate patterns, constituting a cell string, cross the plurality of active regions. Select transistors are disposed over the memory transistors, and lower plugs are disposed on each side of the cell string to electrically connect the plurality of active regions on both sides of the cell string and the select transistors. | 10-30-2008 |
20090206392 | Memory device and fabrication method thereof - A method of forming a memory device, where a first insulator layer and a charge trapping layer may be formed on a substrate, and at least one of the first insulator layer and charge trapping layer may be patterned to form patterned areas. A second insulation layer and a conductive layer may be formed on the patterned areas, and one or more of the conductive layer, second insulator layer, charge trapping layer and first insulator layer may be patterned to form a string selection line, ground selection line, a plurality of word lines between the string selection and ground selection lines on the substrate, a low voltage gate electrode, and a plurality of insulators of varying thickness. The formed memory device may be a NAND-type non-volatile memory device having a SONOS gate structure, for example. | 08-20-2009 |
20090321815 | Non-volatile memory device and method of fabricating the same - A non-volatile memory device, including a substrate of a first conductivity type, the substrate including a plurality of wells of a second conductivity type, a plurality of memory cells in one of the plurality of wells of the second conductivity type, and a peripheral circuit including at least one first transistor of the second conductivity type on the substrate, and at least one second transistor of the first conductivity type in another one of the plurality of wells of the second conductivity type. | 12-31-2009 |
20100078701 | THREE-DIMENSIONAL MICROELECTRONIC DEVICES INCLUDING REPEATING LAYER PATTERNS OF DIFFERENT THICKNESSES - A vertical NAND flash memory device includes a substrate having a face and a string of serially connected flash memory cells on the substrate. A first flash memory cell is adjacent the face, and a last flash memory cell is remote from the face. The flash memory cells include repeating layer patterns that are stacked on the face, and a pillar that extends through the series of repeating layer patterns. The pillar includes at least one oblique wall. At least two of the series of repeating layer patterns in the string are of different thicknesses. Other vertical microelectronic devices and related fabrication methods are also described. | 04-01-2010 |
20100128522 | Flash memory device and programming/erasing method of the same - A flash memory device includes a bulk region, first through nth memory cell transistors arranged in a row on the bulk region, first through nth word lines respectively connected to gates of the first through nth memory cell transistors, a first dummy cell transistor connected to the first memory cell transistor, a first dummy word line connected to a gate of the first dummy cell transistor, a first selection transistor connected to the first dummy cell transistor, a first selection line connected to a gate of the first selection transistor, and a voltage control unit connected to the first selection line, the voltage control unit being adapted to output to the first selection line a voltage lower than a voltage applied to the bulk region, in an erasing mode for erasing the first through nth memory cell transistors. | 05-27-2010 |
20110101439 | INTERCONNECTION STRUCTURES FOR SEMICONDCUTOR DEVICES - An interconnection structure for a semiconductor device includes an inter-level insulation layer disposed on a semiconductor substrate. First contact constructions penetrate the inter-level insulation layer. Second contact constructions penetrate the inter-level insulation layer. Metal interconnections connect the first contact constructions to the second contact constructions on the inter-level insulation layer. The first contact constructions include first and second plugs stacked in sequence and the second contact constructions include the second plug. | 05-05-2011 |
20110233610 | Nonvolatile Memory Devices Having Memory Cell Transistors Therein with Lower Bandgap Source/Drain Regions - Nonvolatile memory devices include a plurality of nonvolatile memory cell transistors having respective channel regions within a semiconductor layer formed of a first semiconductor material and respective source/drain regions formed of a second semiconductor material, which has a smaller bandgap relative to the first semiconductor material. The source/drain regions can form non-rectifying junctions with the channel regions. The source/drain regions may include germanium (e.g., Ge or SiGe regions), the semiconductor layer may be a P-type silicon layer and the source/drain regions of the plurality of nonvolatile memory cell transistors may be P-type germanium or P-type silicon germanium. | 09-29-2011 |
20110233636 | Semiconductor Memory Device and Method of Manufacturing the Same - A non-volatile memory device and a method of manufacturing the non-volatile memory device are disclosed. The non-volatile memory device includes a substrate, at least two gate structures on the substrate, and at least one impurity region in portions of the substrate between the at least two gate structures. The center of the at least one impurity region is horizontally offset from the center of a region between the at least two gate structures. | 09-29-2011 |
20120061741 | THREE-DIMENSIONAL MICROELECTRONIC DEVICES INCLUDING HORIZONTAL AND VERTICAL PATTERNS - A vertical NAND flash memory device includes a substrate having a face and a string of serially connected flash memory cells on the substrate. A first flash memory cell is adjacent the face, and a last flash memory cell is remote from the face. The flash memory cells include repeating layer patterns that are stacked on the face, and a pillar that extends through the series of repeating layer patterns. The pillar includes at least one oblique wall. At least two of the series of repeating layer patterns in the string are of different thicknesses. Other vertical microelectronic devices and related fabrication methods are also described. | 03-15-2012 |
20120202335 | METHODS OF FABRICATING NONVOLATILE MEMORY DEVICES INCLUDING VOIDS BETWEEN ACTIVE REGIONS AND RELATED DEVICES - A method of fabricating a nonvolatile memory device includes forming trenches in a substrate defining device isolation regions therein and active regions therebetween. The trenches and the active regions therebetween extend into first and second device regions of the substrate. A sacrificial layer is formed in the trenches between the active regions in the first device region, and an insulating layer is formed to substantially fill the trenches between the active regions in the second device region. At least a portion of the sacrificial layer in the trenches in the first device region is selectively removed to define gap regions extending along the trenches between the active regions in the first device region, while substantially maintaining the insulating layer in the trenches between the active regions in the second device region. Related methods and devices are also discussed. | 08-09-2012 |
20120223379 | NON-VOLATILE MEMORY DEVICES AND METHODS OF MANUFACTURING THE SAME - A non-volatile memory device includes a substrate including a plurality of active regions and a plurality of device isolating trenches formed between a respective one of each of the active regions along a first direction in the substrate. A plurality of gate structures each including a tunnel insulating layer pattern, a floating gate electrode, a dielectric layer pattern and a control gate electrode is formed on the substrate. A first insulating layer pattern is provided within the device isolating trenches. A second insulating layer pattern is formed along an inner surface portion of a gap between the gate structures. An impurity doped polysilicon pattern is formed on the second insulating layer pattern in the gap between the gate structures. | 09-06-2012 |
20130181278 | NON-VOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE DEVICE - Provided is a non-volatile memory device that includes a substrate including a plurality of active regions extending in a first direction and a plurality of element isolation trenches disposed between the active regions, a plurality of tunnel insulating layer patterns and a plurality of storage layer patterns sequentially disposed on the substrate, a plurality of blocking insulating layers and a plurality of gate electrodes disposed on the storage layer patterns and extending in a second direction perpendicular to the first direction, and first insulating layers including air gaps disposed between the active regions on the element isolation trenches and extending in the first direction, wherein the active regions include first active regions and second active regions adjacent to the first active regions, wherein a width of first air gaps is different from a width of second air gaps. | 07-18-2013 |
20130256775 | THREE-DIMENSIONAL MICROELECTRONIC DEVICES INCLUDING HORIZONTAL AND VERTICAL PATTERNS - A vertical NAND flash memory device includes a substrate having a face and a string of serially connected flash memory cells on the substrate. A first flash memory cell is adjacent the face, and a last flash memory cell is remote from the face. The flash memory cells include repeating layer patterns that are stacked on the face, and a pillar that extends through the series of repeating layer patterns. The pillar includes at least one oblique wall. At least two of the series of repeating layer patterns in the string are of different thicknesses. Other vertical microelectronic devices and related fabrication methods are also described. | 10-03-2013 |
20140248755 | METHODS OF FABRICATING NONVOLATILE MEMORY DEVICES INCLUDING VOIDS BETWEEN ACTIVE REGIONS AND RELATED DEVICES - A method of fabricating a nonvolatile memory device includes forming trenches in a substrate defining device isolation regions therein and active regions therebetween. The trenches and the active regions therebetween extend into first and second device regions of the substrate. A sacrificial layer is formed in the trenches between the active regions in the first device region, and an insulating layer is formed to substantially fill the trenches between the active regions in the second device region. At least a portion of the sacrificial layer in the trenches in the first device region is selectively removed to define gap regions extending along the trenches between the active regions in the first device region, while substantially maintaining the insulating layer in the trenches between the active regions in the second device region. Related methods and devices are also discussed. | 09-04-2014 |