Patent application number | Description | Published |
20110320839 | MEMORY POWER MANAGEMENT VIA DYNAMIC MEMORY OPERATION STATES - Described herein are techniques for dynamic memory frequency/voltage scaling to augment existing memory power management techniques and further improve memory power efficiency. Each operating point is defined as an operational state for the memory. | 12-29-2011 |
20140089576 | METHOD, APPARATUS AND SYSTEM FOR PROVIDING A MEMORY REFRESH - A memory controller to implement targeted refreshes of potential victim rows of a row hammer event. In an embodiment, the memory controller receives an indication that a specific row of a memory device is experiencing repeated accesses which threaten the integrity of data in one or more victim rows physically adjacent to the specific row. The memory controller accesses default offset information in the absence of address map information which specifies an offset between physically adjacent rows of the memory device. In another embodiment, the memory controller determines addresses for potential victim rows based on the default offset information. In response to the received indication of the row hammer event, the memory controller sends for each of the determined plurality of addresses a respective command to the memory device, where the commands are for the memory device to perform targeted refreshes of potential victim rows. | 03-27-2014 |
20140189228 | THROTTLING SUPPORT FOR ROW-HAMMER COUNTERS - Throttling of memory access commands. Accesses to rows of a memory device are monitored for a timeframe. The timeframe is divided into at least two sub-frames. If the number of accesses for any of the rows during a first sub-frame exceeds a first threshold throttling accesses to the accessed row at a first rate. Not throttling accesses to the accessed row if the number of accesses to the accessed row does not exceed the first threshold. The first threshold is associated with risk of data corruption on a row physically adjacent to the accessed row. If a number of accesses for the accessed row during a second sub-frame exceeds a second threshold, throttling accesses to the accessed row at a second rate. Not throttling accesses to the accessed row if the number of accesses to the accessed row does not exceed the second threshold. The second threshold is greater than the first threshold. The second throttling rate is greater than the first throttling rate. | 07-03-2014 |
20140192605 | MEMORY REFRESH MANAGEMENT - Apparatus, systems, and methods to manage memory refresh operations are described. In one embodiment, an electronic device comprises a processor and memory controller logic to determine a memory refresh frequency for a memory system and transmit refresh commands to a refresh control logic in at least one memory bank coupled to the memory controller according to the memory refresh frequency. Other embodiments are also disclosed and claimed. | 07-10-2014 |
20140244922 | MULTI-PURPOSE REGISTER PROGRAMMING VIA PER DRAM ADDRESSABILITY MODE - Embodiments of an apparatus, system and method for using Per DRAM Addressability (PDA) to program Multi-Purpose Registers (MPRs) of a dynamic random access memory (DRAM) device are described herein. Embodiments of the invention allow unique 32 bit patterns to be stored for each DRAM device on a rank, thereby enabling data bus training to be done in parallel. Furthermore, embodiments of the invention provide 32 bits of storage per DRAM device on a rank for the system BIOS for storing codes such as MR values, or for any other purpose (e.g., temporary scratch storage to be used by BIOS processes). | 08-28-2014 |
20140281207 | Techniques for Determining Victim Row Addresses in a Volatile Memory - Examples are disclosed for determining a logical address of one or more victim rows of a volatile memory based on a logical address of an aggressor row and address translation schemes associated with the volatile memory. Other examples are described and claimed. | 09-18-2014 |
20140281805 | SELECTIVE REMEDIAL ACTION BASED ON CATEGORY OF DETECTED ERROR FOR A MEMORY READ - Embodiments of apparatus, methods, systems, computer-readable storage media and devices are described herein for determining an error category for a detected error in data read from a volatile memory; and selectively performing or causing an additional remedial action based at least in part on the error category determined. In various embodiments, the determining and the performing or causing may be undertaken in response to the correcting. The memory may be volatile or non-volatile memory. Other embodiments may be described and/or claimed. | 09-18-2014 |
20140372816 | ACCESSING DATA STORED IN A COMMAND/ADDRESS REGISTER DEVICE - A register not connected to a data bus is read by transferring data across an address bus to a device connected to the data bus, from which the data is read by a device connected to the data bus. The register resides in a register device connected via the address bus to a memory device that is connected to both the address bus and the data bus. A host processor triggers the register device to transfer information over the address bus to a register on the memory device. The host processor then reads the information from the register of the memory device. | 12-18-2014 |
20150089111 | ACCESSING DATA STORED IN A COMMAND/ADDRESS REGISTER DEVICE - A register not connected to a data bus is read by transferring data across an address bus to a device connected to the data bus, from which the data is read by a device connected to the data bus. The register resides in a register device connected via the address bus to a memory device that is connected to both the address bus and the data bus. A host processor triggers the register device to transfer information over the address bus to a register on the memory device. The host processor then reads the information from the register of the memory device. | 03-26-2015 |
20150089183 | MAPPING A PHYSICAL ADDRESS DIFFERENTLY TO DIFFERENT MEMORY DEVICES IN A GROUP - A memory subsystem includes a group of memory devices connected to an address bus. The memory subsystem includes logic to uniquely map a physical address of a memory access command to each memory device of the group. Thus, each physical address sent by an associated memory controller uniquely accesses a different row of each memory device, instead of being mapped to the same or corresponding row of each memory device. | 03-26-2015 |