Patent application number | Description | Published |
20110267547 | METHOD & A MODULE FOR RE-GENERATING ATSC-MH BROADCASTING SIGNAL, AN ATSC-MH BROADCAST RECEIVER, AND A STORAGE MEDIUM - The present invention relates to a re-generating method and module for an ATSC-MH broadcasting signal, an ATSC-MH broadcast receiver, and a storage medium. The ATSC-MH broadcast receiver includes: a main stream data generating module for receiving an ATSC-MH RF signal, and outputting main stream data including MHE packets; an ATSC-MH broadcasting signal re-generating module for extracting the MHE packets from the main stream data generated by the main stream data generating module, thereby re-configuring data of MPH Group format after data interleaver; and a mobile stream generating module for outputting the mobile stream data from the interleaved MPH group format data re-configured by the ATSC-MH broadcasting signal re-generating module. | 11-03-2011 |
20140160240 | APPARATUS AND METHOD FOR OFFERING BOUNDARY INFORMATION, AND APPARATUS AND METHOD FOR RECEIVING VIDEO - A boundary information providing apparatus may include a boundary information generation unit to generate boundary information of a video, the boundary information through which a switching point between a 2D video and a 3D video is recognized, based on a switching mode between the 2D video and the 3D video, and a stream transmission unit to transmit a stream including the boundary information to a video receiving apparatus. | 06-12-2014 |
20140245371 | DEVICE AND METHOD FOR PROVIDING CONTENT BY ACCESSING CONTENT STREAM IN HYBRID 3D TV, AND DEVICE AND METHOD FOR REPRODUCING CONTENT - A content providing apparatus and method, and a content reproduction apparatus and method for accessing a content stream in a hybrid three-dimensional television (3DTV) are disclosed. The content providing apparatus may include a content stream generation unit to generate a first content stream corresponding to a reference image and a second content stream corresponding to a supplementary image, a descriptor generation unit to generate a descriptor associated with the first content stream and the second content stream, and a data transmission unit to transmit the first content stream, the second content stream, and the descriptor to a content reproduction apparatus. | 08-28-2014 |
20140307049 | APPARATUS AND METHOD FOR PROVIDING IMAGE, AND APPARATUS AND METHOD FOR PLAYING IMAGE - Provided is a video providing method and a video playing method for a three-dimensional (3D) video, and an apparatus for performing the methods. The video providing method may transmit a reconstruction mode for reconstructing a low-resolution additional video having lower resolution than a high-resolution reference video. | 10-16-2014 |
20140313289 | APPARATUS AND METHOD FOR PROVIDING CONTENT FOR SYNCHRONIZING LEFT/RIGHT STREAMS IN FIXED/MOBILE CONVERGENCE 3DTV, AND APPARATUS AND METHOD FOR PLAYING CONTENT - An apparatus and a method for synchronizing left and right streams in a stationary/mobile hybrid 3DTV are disclosed. The apparatus according to an exemplary embodiment may synchronize content streams corresponding to left and right images using a timestamp pairing mode, a timestamp offset mode, and a network time protocol (NTP) synchronization mode. | 10-23-2014 |
20140320597 | 3D BROADCAST SERVICE PROVIDING METHOD AND APPARATUS, AND 3D BROADCAST SERVICE REPRODUCTION METHOD AND APPARATUS FOR USING IMAGE OF ASYMMETRIC ASPECT RATIO - Disclosed are a method and apparatus for providing a three-dimensional (3D) broadcast service using images with asymmetric aspect ratios and a method and apparatus for reproducing a 3D broadcast service. The method of providing the 3D broadcast service includes adjusting a second viewpoint image to be composed with a first viewpoint image into a 3D form with respect to the first viewpoint image and the second viewpoint image for 3D broadcasting, encoding the first viewpoint image and the adjusted second viewpoint image, and generating a broadcast stream of the first viewpoint image and a broadcast stream of the second viewpoint image by multiplexing the first viewpoint image and the second viewpoint image. | 10-30-2014 |
20140340480 | APPARATUS AND METHOD FOR MANAGING DELAY IN RECEIVING THREE-DIMENSIONAL (3D) IMAGE - An apparatus for managing a delay in receiving a three-dimensional (3D) image may include an image receiver to receive a left image and a right image for 3D image synthesis, and a substitution content output unit to output substitution content during a waiting time caused by a difference between points in time at which the left image and the right image are received. | 11-20-2014 |
20150062298 | IMAGE QUALITY INCREASING APPARATUS AND METHOD - An image quality increasing apparatus for a binocular three-dimensional television (3DTV) is disclosed. The image quality increasing apparatus may include an error detection unit to detect whether a reference image includes an error, a reference information correction unit to correct reference information for increasing an image quality of an additional image based on a detection result, an image quality increasing unit to increase the image quality of the additional image corresponding to the reference information, and a three-dimensional (3D) image synthesis unit to synthesize a 3D image using the quality increased additional image and the reference image. | 03-05-2015 |
20150109411 | IMAGE PLAYBACK APPARATUS FOR 3DTV AND METHOD PERFORMED BY THE APPARATUS - An image reproduction apparatus for a 3DTV and a processing method by the apparatus are disclosed. The image reproduction apparatus may determine an output time of a buffer to store a left image stream and a right image stream for a 3D image. The image reproduction apparatus may determine a buffer size or a buffer delay time using a reception time difference between the left image stream and the right image stream. Further, the image reproduction apparatus may correct a reference clock or a timestamp using the reception time difference between the left image stream and the right image stream. | 04-23-2015 |
20150138317 | SYSTEM AND METHOD FOR PROVIDING THREE-DIMENSIONAL (3D) BROADCAST SERVICE BASED ON RETRANSMISSION NETWORKS - A system and method for providing a three-dimensional (3D) broadcast service based on a retransmission network are provided. A 3D broadcast retransmission apparatus in a 3D broadcast service providing system may include a remultiplexer to remultiplex 3D TV service information in a received stream of a first broadcast network, based on a retransmission scenario, and to generate a stream of a retransmission network, and a retransmission network transmitter to transmit the stream of the retransmission network through the retransmission network. | 05-21-2015 |
Patent application number | Description | Published |
20080209188 | PROCESSOR AND METHOD OF PERFORMING SPECULATIVE LOAD OPERATIONS OF THE PROCESSOR - Provided is a processor and method of performing speculative load instructions of the processor in which a load instruction is performed only in the case where the load instruction substantially accesses a memory. A load instruction for canceling operations is performed in other cases except the above case, so that problems occurring by accessing an input/output (I/O) mapped memory area and the like at the time of performing speculative load instructions can be prevented using only a software-like method, thereby improving the performance of a processor. | 08-28-2008 |
20090055626 | METHOD OF SHARING COARSE GRAINED ARRAY AND PROCESSOR USING THE METHOD - A method of sharing a coarse grained array and a processor using the method is provided. A processor includes a first processor core including a plurality of first functional units which execute a first instruction set, a second processor core including a plurality of second functional units which execute a second instruction set, and a coarse grained array including a plurality of third functional units which execute a portion of instructions of the first instruction set and/or the second instruction set, instead of the first processor core and/or the second processor core. | 02-26-2009 |
20090089551 | Apparatus and method of avoiding bank conflict in single-port multi-bank memory system - Provided are a method and apparatus for avoiding bank conflict. A first instruction that is one of access instructions that are predicted to cause the bank conflict is replaced with a second instruction by changing an execute timing of the first instruction to a timing prior to the execute timing of the first instruction so as for the access instructions not to cause the bank conflict. Next, a load/store unit that is scheduled to access the bank according to the first instruction accesses the bank and reads out a data from the bank at an execute timing of the second instruction, and after that, the load/store unit is allowed to be inputted the read data at the execute timing of the first instruction. Accordingly, although the access instructions that are predicted to cause the bank conflict are allocated to the load/store units, the bank conflict can be prevented, so that it is possible to avoid deterioration in performance due the occurrence of the bank conflict. | 04-02-2009 |
20100205405 | STATIC BRANCH PREDICTION METHOD AND CODE EXECUTION METHOD FOR PIPELINE PROCESSOR, AND CODE COMPILING METHOD FOR STATIC BRANCH PREDICTION - A static branch prediction method and code execution method for a pipeline processor, and a code compiling method for static branch prediction, are provided herein. The static branch prediction method includes predicting a conditional branch code as taken or not-taken, adding the prediction information, converting the conditional branch code into a jump target address setting (JTS) code including target address information, branch time information, and a test code, and scheduling codes in a block. The code may be scheduled into a last slot of the block, and the JTS code may be scheduled into an empty slot after all the other codes in the block are scheduled. When the conditional branch code is predicted as taken in the prediction operation, a target address indicated by the target address information may be fetched at a cycle time indicated by the branch time information. | 08-12-2010 |
20110138086 | DIRECT MEMORY ACCESS CONTROLLER AND METHOD OF OPERATING THE SAME - Provided is a Direct Memory Access (DMA) controller which provides a function of searching for a specific pattern from data being transmitted during DMA transmission. The DMA controller stores at least one pattern value. The DMA controller compares data being transmitted to a pattern value while transmitting the data using a DMA method, and generates, in response to data matching the pattern value being detected, a signal indicating that the data matching the pattern value has been detected. The DMA controller stores an address of the data matching the pattern value in response to the generated signal. | 06-09-2011 |
20110219207 | RECONFIGURABLE PROCESSOR AND RECONFIGURABLE PROCESSING METHOD - A reconfigurable processor for efficiently performing a vector operation, and a method of controlling the reconfigurable processor are provided. The reconfigurable processor designates at least one of a plurality of processing elements as a vector lane based on vector lane configuration information, and allocates a vector operation to the designated vector lane. | 09-08-2011 |
20110225369 | MULTIPORT DATA CACHE APPARATUS AND METHOD OF CONTROLLING THE SAME - A multiport data cache apparatus and a method of controlling the same are provided. The multiport data cache apparatus includes a plurality of cache banks configured to share a cache line, and a data cache controller configured to receive cache requests for the cache banks, each of which including a cache bank identifier, transfer the received cache requests to the respective cache banks according to the cache bank identifiers, and process the cache requests independently from one another. | 09-15-2011 |
20120005679 | APPARATUS AND METHOD FOR THREAD PROGRESS TRACKING USING DETERMINISTIC PROGRESS INDEX - Provided is a method and apparatus for measuring a performance or a progress state of an application program to perform data processing and execute particular functions in a computing environment using a micro architecture. A thread progress tracking apparatus may include a selector to select at least one thread constituting an application program; a determination unit to determine, based on a predetermined criterion, whether an instruction execution scheme corresponds to a deterministic execution scheme having a regular cycle or a nondeterministic execution scheme having an irregular delay cycle with respect to each of at least one instruction constituting a corresponding thread; and a deterministic progress counter to generate a deterministic progress index with respect to an instruction that is executed by the deterministic execution scheme, excluding an instruction that is executed by the nondeterministic execution scheme. | 01-05-2012 |
20120124116 | APPARATUS AND METHOD FOR CONVERTING DATA BETWEEN A FLOATING-POINT NUMBER AND AN INTEGER - An apparatus and method for converting data between a floating-point number and an integer is provided. The apparatus includes a data converter configured to determine a sign of input binary data and an output format to which to convert the input binary data and convert the input binary data into a one's complement number based on the sign and the output format of the input binary data, a bias value generator configured to determine whether the input binary data has been rounded up based on a rounding mode of the input binary data and generate a bias value accordingly; and an adder configured to convert the input binary data into a two's complement number by adding the one's complement number and the bias value. | 05-17-2012 |
20120124117 | FUSED MULTIPLY-ADD APPARATUS AND METHOD - A fixed multiply-add (FMA) apparatus and method are provided. The FMA apparatus includes a partial product generator configured to generate a partial sum and a partial carry, a carry save adder configured to generate a partial sum having a first bit size and a partial carry having the first bit size by adding the partial sum and the partial carry to least significant bits (LSBs) of the mantissa of a third floating-point number, a carry select adder configured to generate a mantissa having a second bit size by adding the first bit-size partial sum and the first bit-size partial carry to most significant bits (MSBs) of the third floating-point number, and a selector configured to transmit the first bit-size partial sum and the first bit-size partial carry to the carry save adder or the carry select adder according to whether the mantissa of the third floating-point number is zero. | 05-17-2012 |
20120159507 | COMPILING APPARATUS AND METHOD OF A MULTICORE DEVICE - An apparatus and method capable of reducing idle resources in a multicore device and improving the use of available resources in the multicore device are provided. The apparatus includes a static scheduling unit configured to generate one or more task groups, and to allocate the task groups to virtual cores by dividing or combining the tasks included in the task groups based on the execution time estimates of the task groups. The apparatus also includes a dynamic scheduling unit configured to map the virtual cores to physical cores. | 06-21-2012 |
20120166762 | COMPUTING APPARATUS AND METHOD BASED ON A RECONFIGURABLE SINGLE INSTRUCTION MULTIPLE DATA (SIMD) ARCHITECTURE - Provided are a computing apparatus and method based on SIMD architecture capable of supporting various SIMD widths without wasting resources. The computing apparatus includes a plurality of configurable execution cores (CECs) that have a plurality of execution modes, and a controller for detecting a loop region from a program, determining a Single Instruction Multiple Data (SIMD) width for the detected loop region, and determining an execution mode of the processor according to the determined SIMD width. | 06-28-2012 |
20130145133 | PROCESSOR, APPARATUS AND METHOD FOR GENERATING INSTRUCTIONS - A processor, apparatus and method to use a multiple store instruction based on physical addresses of registers are provided. The processor is configured to execute an instruction to store data of a plurality of registers in a memory, the instruction including a first area in which a physical address of each of the registers is written. An instruction generating apparatus is configured to generate an instruction to store data of a plurality of registers in a memory, the instruction including a first area in which a physical address of each of the registers is written. An instruction generating method includes detecting a code area that instructs to store data of a plurality of registers in a memory, from a program code. The instruction generating method further includes generating an instruction corresponding to the code area by mapping physical addresses of the registers to a first area of the instruction. | 06-06-2013 |
20130151794 | MEMORY CONTROLLER AND MEMORY CONTROL METHOD - Provided is a memory controller that manages memory access requests between the processor and the memory. In response to the memory controller receiving two or more memory access requests for the same area of memory, the memory controller is configured to stall the memory controller and sequentially process the memory access requests. | 06-13-2013 |
20130151815 | RECONFIGURABLE PROCESSOR AND MINI-CORE OF RECONFIGURABLE PROCESSOR - A reconfigurable processor includes a plurality of mini-cores and an external network to which the mini-cores are connected. Each of the mini-cores includes a first function unit including a first group of operation elements, a second function unit including a second group of operation elements that is different from the first group of operation elements, and an internal network to which the first function unit and the second function unit are connected. | 06-13-2013 |
20140214913 | ADDER CAPABLE OF SUPPORTING ADDITION AND SUBTRACTION OF UP TO N-BIT DATA AND METHOD OF SUPPORTING ADDITION AND SUBTRACTION OF A PLURALITY OF DATA TYPE USING THE ADDER - An adder for supporting multiple data types by controlling a carry propagation is provided. The adder includes a plurality of first addition areas configured to receive pieces of incoming operand data, wherein each of the plurality of first addition areas includes a predetermined unit number of bits, and a plurality of second addition areas configured to receive pieces of control data based on a type of the operand data and an operation type, wherein the plurality of second addition areas are alternately arranged between the plurality of first addition areas. | 07-31-2014 |
20140215476 | APPARATUS AND METHOD FOR SHARING FUNCTION LOGIC BETWEEN FUNCTIONAL UNITS, AND RECONFIGURABLE PROCESSOR THEREOF - An apparatus and method for sharing a function logic between functional units and a reconfigurable processor are provided. The apparatus for sharing a function logic may include a storage which is configured to store data which is received from two or more functional units in order to share one or more function logics, and an arbitrator which is configured, based on a scheduling rule, to transmit the data stored in the storage into the function logic. | 07-31-2014 |
20140317383 | APPARATUS AND METHOD FOR COMPRESSING INSTRUCTION FOR VLIW PROCESSOR, AND APPARATUS AND METHOD FOR FETCHING INSTRUCTION - Provided are an instruction compression apparatus and method for a very long instruction word (VLIW) processor, and an instruction fetching apparatus and method. The instruction compression apparatus includes: an indicator generator configured to generate an indicator code that indicates an issue width of an instruction bundle to be executed in the VLIW processor, and a number of No-Operation (NOP) instruction bundles following the instruction bundle; an instruction compressor configured to compress the instruction bundle by removing at least one of NOP instructions from the instruction bundle and the NOP instruction bundles following the instruction bundle; and an instruction converter configured to include the generated indicator code in the compressed instruction bundle. | 10-23-2014 |
20140331025 | RECONFIGURABLE PROCESSOR AND OPERATION METHOD THEREOF - A reconfigurable processor and an operation method thereof are provided. The reconfigurable processor may include: a controller configured to control operations of a first mode, in which a first portion of a program that does not utilize loop acceleration is processed, and a second mode, in which a second portion for the program that utilizes the loop acceleration is processed, based on whether an instruction to control parallel operations of the first mode and the second mode is executed; and a shared register file configured to transfer data between the first mode and the second mode. | 11-06-2014 |
20150100772 | RECONFIGURABLE PROCESSOR AND METHOD OF OPERATING THE SAME - Provided are a reconfigurable processor and a method of operating the reconfigurable processor. In the method, configuration data is requested to access based on virtual addresses, and accessing of the configuration data by using a processor core is controlled to read the configuration data from addresses of a configuration memory mapped to the virtual addresses. | 04-09-2015 |
20150154026 | METHOD AND PROCESSOR FOR EXECUTING INSTRUCTIONS, METHOD AND APPARATUS FOR ENCODING INSTRUCTIONS, AND RECORDING MEDIUM THEREFOR - In a method to execute instructions, at least one instruction executed in a predetermined cycle is acquired based on information included in each of a plurality of instructions, and a code included in the at least one instruction acquired. An instruction is allocated to at least one slot based on the analysis result, and a slot necessary to execute the instruction is selectively used. Accordingly, power consumption of a device using the method may be reduced. | 06-04-2015 |
20150193375 | PROCESSOR AND METHOD OF CONTROLLING THE SAME - A method of controlling a processor includes receiving from a command buffer a first command corresponding to a first instruction that is processed by a second processing core and starting processing of the first command by the first processing core, storing in the command buffer a second command corresponding to a second instruction that is processed by the second processing core before the processing of the first command is completed, and starting processing of a third instruction by the second processing core before the processing of the first command is completed. | 07-09-2015 |
20150227479 | DIRECT MEMORY ACCESS CONTROLLER AND SYSTEM FOR ACCESSING CHANNEL BUFFER - A direct memory access (DMA) controller is provided. The DMA controller includes a processor interface configured to directly receive information representing a first operation sent by a processor to a buffer, and transmit data corresponding to the first operation stored in the buffer to the processor core or record data corresponding to the first operation in the buffer, and a buffer group connected to the processor interface, and including a plurality of buffers. | 08-13-2015 |
20150280740 | METHOD OF COMPRESSING AND RESTORING CONFIGURATION DATA - A method of compressing configuration data used in a reconfigurable processor including generating one piece of combined data by combining configuration data used at two or more cycles and generating a bit table indicating valid operations at each of the two or more cycles among operations included in the combined data | 10-01-2015 |
Patent application number | Description | Published |
20090122767 | METHOD AND APPARATUS FOR GENERATING DATA FRAME - Provided are a method and apparatus for generating a data frame. The method includes generating subframes from at least one media access control (MAC) service data unit (MSDU); generating a retransmission policy field for recording a policy related to a retransmission request, against an error occurring while the subframes are being transmitted, with regard to each of the subframes; and generating the data frame by using the subframes and the retransmission policy field which is generated with regard to each of the subframes. | 05-14-2009 |
20100166017 | METHOD AND APPARATUS FOR PROCESSING PACKET - Provided is a packet processing apparatus and method for audio/video (AV) data transmission, in which a simple protocol optimized for AV data transmission is used. Information distinguishing a data packet from a control packet may be included in a data link layer packet header, so that a data packet and a control packet may be distinguished from each other and thereby may be processed according to different procedures. | 07-01-2010 |
20110044208 | WIRELESS AD-HOC NETWORK CONFIGURATION METHOD AND APPARATUS - A method and apparatus for setting up a wireless ad-hoc network, the method including: interchanging a terminal identifier and Wi-Fi protected setup (WPS) capability information with other terminals of the wireless ad-hoc network; selecting a role as a registrar or an enrollee based on the interchanged terminal identifier and the interchanged WPS capability information of the wireless ad-hoc network; and optionally registering in the registrar based on the selected role. | 02-24-2011 |
20120150834 | CREATION SUPPORTING SYSTEM USING METADATA BASED ON USER AND INFORMATION PROVIDING METHOD THEREOF - Provided is a creation supporting system and method using user-based metadata. According to the creation supporting system and method, metadata collected by a user for video content are stored so as to be provided to a creator. The creation supporting system includes a user terminal configured to receive evaluation data on video content from a user who watched the video content; a utilizer terminal configured to receive a search value from a utilizer desiring a search and request a video content search; and a service providing server configured to receive the evaluation data from the user terminal, construct metadata of video content, and compare the search value received from the utilizer server with the metadata for searching for a corresponding video content. | 06-14-2012 |
20130054978 | COMPUTING SYSTEM AND METHOD OF OPERATING COMPUTING SYSTEM - A computing system including a memory that is shared by a plurality of components of the computing system in order to exchange data between the plurality of components; and a controller configured to control the plurality of components to encrypt the data and to record the encrypted data in the memory. | 02-28-2013 |
20130222690 | DATA TRANSMISSION APPARATUS, DATA RECEIVING APPARATUS, DATA TRANSCEIVING SYSTEM, DATA TRANSMISSION METHOD AND DATA RECEIVING METHOD - Disclosed is a data transmitting apparatus, which includes a packet generating unit which generates a metadata packet for multi-channel audio data; and a transmission unit which transmits the generated metadata packet to a receiving apparatus, wherein, the generated metadata packet includes an Audio Channel Allocation Standard Type (ACAT) field which indicates channel allocation standard type information of the multi-channel audio data. | 08-29-2013 |
20130223448 | DATA TRANSMITTING APPARATUS, DATA RECEIVING APPARATUS, DATA TRANSRECEIVING SYSTEM, DATA TRANSMITTING METHOD, DATA RECEIVING METHOD AND DATA TRANSRECEIVING METHOD - A data transmitting apparatus includes a packet generator which generates a plurality of packets regarding multi-channel audio sample data and transmitter which transmits the plurality of generated packets to a data receiving apparatus. Each of the plurality of packets includes an identifier field to distinguish a position or an order of the packets. | 08-29-2013 |
20130223456 | DATA TRANSMITTING APPARATUS, DATA RECEIVING APPARATUS, DATA TRANSRECEIVING SYSTEM, DATA TRANSMITTING METHOD, DATA RECEIVING METHOD AND DATA TRANSRECEIVING METHOD - A data transmitting apparatus is provided. The data transmitting apparatus includes a packet generator configured to generate a packet including a plurality of sub packets and a transmitter configured to transmit the generated packet to a data receiving apparatus. Each of the plurality of sub packets includes audio data corresponding to content among a plurality of contents. | 08-29-2013 |
20130223632 | DATA TRANSMITTING APPARATUS, DATA RECEIVING APPARATUS, DATA TRANSCEIVING SYSTEM, DATA TRANSMITTING METHOD, AND DATA RECEIVING METHOD - A data transmitting apparatus is disclosed. The data transmitting apparatus includes a block generator which generates an Extended Display Identification Data (EDID) block regarding multi-channel audio data; and a transmitter which transmits the EDID block to a data receiving apparatus, wherein the EDID block includes at least one of a first sub block representing 3D audio characteristics of the multi-channel audio data, a second sub block representing 3D speaker placement information of the multi-channel audio data, and a third sub block representing multi-stream audio characteristics of the multi-channel audio data. | 08-29-2013 |
20130230296 | DATA TRANSMITTER, DATA RECEIVER, DATA TRANSCEIVING SYSTEM, DATA TRANSMITTING METHOD, DATA RECEIVING METHOD, AND DATA TRANSCEIVING METHOD - A data transmitter is provided. The data transmitter includes a packet generating unit which generates a packet including encryption information of a content stream, and a transmitting unit which transmits the generated packet to a data receiver, wherein the generated packet comprises a first field for indicating identification information of the content stream, and a second field for indicating an encryption parameter value of the content stream. | 09-05-2013 |
20150195389 | DATA TRANSMITTING APPARATUS, DATA RECEIVING APPARATUS, DATA TRANSRECEIVING SYSTEM, DATA TRANSMITTING METHOD, DATA RECEIVING METHOD AND DATA TRANSRECEIVING METHOD - A data transmitting apparatus is provided. The data transmitting apparatus includes a packet generator configured to generate a packet including a plurality of sub packets and a transmitter configured to transmit the generated packet to a data receiving apparatus. Each of the plurality of sub packets includes audio data corresponding to content among a plurality of contents. | 07-09-2015 |