Patent application number | Description | Published |
20080320234 | Information processing apparatus and data transfer method - One aspect of the embodiments utilizes an information processing apparatus having a plurality of system boards connected via a bus, each system board including a CPU having a cache memory, a main memory that forms a shared memory, and a system controller that manages the CPU and the main memory as well as controls a data transfer of at least one of the cache memory and the main memory by a memory access request, wherein each system controller including a snoop controller that selects a transfer source CPU from transfer source candidate CPUs each having cache memory including a data requested by the memory access request when the data is available in a plurality of cache memories. | 12-25-2008 |
20080320238 | Snoop control method and information processing apparatus - One aspect of the embodiments utilizes a system controller which has a broadcast transmitting and receiving unit that receives a memory access request from each of CPU and notifies to the other system controllers and a snoop control unit that judges when the memory access request from any of the CPUs for each of the cache memories in the CPU is received, whether object data conflicts with object data requested by a prior access request received earlier than the memory access request and whether the object data is present in any of the cache memories, selects the status of the cache memory of the CPU, notifies the other system controller of a snoop processing result in which the status selected and the cache memory are associated, and set a final status as the status of the system controller based on priority of each status of other system controllers. | 12-25-2008 |
20090240893 | Information processing device, memory control method, and memory control device - The present invention provides an information processing device, a memory control method, and a memory control device. In the information processing device that includes nodes each having a main memory and a processor including a cache memory, the system controller of at least one of the nodes is designed to include a holding unit that holds specific information about primary data present in the main memory of its subject node, with the cache data corresponding to the primary data not present in the cache memory of the nodes other than its subject node. With this structure, the latency of each memory access is shortened, and the throughput of each snoop operation is improved. | 09-24-2009 |
20100046364 | Transmitting system, apparatus, and method - A system includes a first apparatus and a second apparatus connected via a transmission path. The first apparatus includes a transmitting unit that transmits a request as at least one packet and retransmits the at least one request packet if a time period between the request and a response is not less than a predetermined time period; and a receiving unit that receives the response as at least one response packet and discards any error packet and any redundant packet from among the received at least one response packet. The second apparatus includes: a receiving unit that receives the at least one request packet and discards any error packet from among the received at least one request packet; and a transmitting unit that determines a response type, selectively makes the at least one response packet redundant for any response of a specific type, and transmits the redundant response packets. | 02-25-2010 |
20100125687 | SYSTEM HAVING PROCESSOR AND I/O CONTROLLER - A method of controlling an apparatus including a processor and an I/O controller includes storing execution information, receiving a first and a second requests successively, determining whether initiation of each execution of the first and the second requests is to be supervised by either of the processor and the I/O controller in reference to the execution information, transmitting the first request to the processor from the I/O controller, and upon completion of execution of the first request at the processor, transmitting the second request to the processor from the I/O controller when the initiations of executions of the first and second request is supervised by the I/O controller, and transmitting the first and second requests to the processor regardless of completion of execution of the first request by the processor when the initiations of executions of the first and second requests is supervised by the processor. | 05-20-2010 |
20100217939 | DATA PROCESSING SYSTEM - A data processing system includes a plurality of nodes connected with each other, each of the nodes including a processor and a memory, each of the processor including a processing unit, a cache memory, a tag memory for storing tag information, the processor accessing data to be processed, in the tag memory in reference to the tag information, and a cache controller for controlling saving or evacuating of data in the cache memory, the cache controller, checking if the data to be evacuated originated from the memory of its own node or from any other memory of any other node, and when the data to be evacuated originated from any other memory of any other node, storing the data into the memory of its own node at a particular address of the memory and storing information of the particular address in the tag memory as tag information. | 08-26-2010 |
20100250862 | SYSTEM CONTROLLER, INFORMATION PROCESSING SYSTEM, AND ACCESS PROCESSING METHOD - A system controller includes an output unit which transfers an access request from an access source coupled to the system controller to an other system controller; a local snoop control unit that determines whether a destination of the access request from the access source is a local memory unit coupled to the system controller, and locks the destination when the destination is the local memory unit; a receiving unit which receives the access request from the output unit and an access request from an other system controller; a global snoop control unit which sends a response indicating whether the access request is executable or not, and controls locking of the destination of the access request when the destination is the local memory unit; and an access processing unit which unlocks the locking and accesses the memory unit when the access request from the access source becomes executable. | 09-30-2010 |
Patent application number | Description | Published |
20080310297 | ERROR CONTROL APPARATUS - A plurality of system board modules are connected to a crossbar module. An error detection unit detects an error in a packet received from a corresponding system board module. When an error is detected by the error detection unit, a transmission control unit issues a completion data generation request. When receiving the completion data generation request, a packet completion unit generates completion data. When receiving an error packet, a selector circuit outputs a completion packet in which completion data is provided in place of a data unit involving error. | 12-18-2008 |
20080313411 | SYSTEM CONTROLLER AND CACHE CONTROL METHOD - A processor module having a cache device and a system controller having a copy TAG2 of a tag of the cache device configure a system to which a protocol representing the states of a data block of the cache device by six states, that is, an invalid state I, a shared state S, an exclusive state E, a modified state M, a shared modified state O, and a writable modified state W can be applied. In order to implement the concept, information about a new state in a cache device of a requester is included in a reply packet from the cache device for transmitting the data block. After the completion of the snooping process of the TAG2 until the reception of the reply packet from the cache device for transmitting the data block and the determination of the next state, an object data block is locked in the TAG2. | 12-18-2008 |
20080320237 | SYSTEM CONTROLLER AND CACHE CONTROL METHOD - A multiprocessor system comprises a plurality of system controllers, each of which performs a snoop processing regarding a cache device in its charge. The system controllers adjust the number of steps of a snoop pipeline for the snoop processing according to communication time with the other system controllers. The number-of-steps adjustment absorbs the difference of the communication time in the results of the snoop for each scale of the multiprocessor system. When a retrial is determined by an address conflict or the like in the snoop processing, each of the system controllers resubmits the access to be retried to the snoop pipeline after waiting until no other access which may cause an address conflict precedes. The resubmission timing prevents infinite repetition of the retrial of the snoop processing in the system controllers. | 12-25-2008 |