Patent application number | Description | Published |
20110078485 | Increasing Memory Bandwidth in Processor-Based Systems - The amount of data that may be transferred between a processing unit and a memory may be increased by transferring information during both the high and low phases of a clock. As one example, in a graphics processor using a general purpose register file as a memory and a mathematical box as a processing unit, the amount of data that can be transferred can be increased by transferring data during both the high and low phases of a clock. | 03-31-2011 |
20120191951 | MFENCE and LFENCE Micro-Architectural Implementation Method and System - A system and method for fencing memory accesses. Memory loads can be fenced, or all memory access can be fenced. The system receives a fencing instruction that separates memory access instructions into older accesses and newer accesses. A buffer within the memory ordering unit is allocated to the instruction. The access instructions newer than the fencing instruction are stalled. The older access instructions are gradually retired. When all older memory accesses are retired, the fencing instruction is dispatched from the buffer. | 07-26-2012 |
20120198208 | SHARED FUNCTION MULTI-PORTED ROM APPARATUS AND METHOD - Various embodiments may be disclosed that may share a ROM pull down logic circuit among multiple ports of a processing core. The processing core may include an execution unit (EU) having an array of read only memory (ROM) pull down logic storing math functions. The ROM pull down logic circuit may implement single instruction, multiple data (SIMD) operations. The ROM pull down logic circuit may be operatively coupled with each of the multiple ports in a multi-port function sharing arrangement. Sharing the ROM pull down logic circuit reduces the need to duplicate logic and may result in a savings of chip area as well as a savings of power. | 08-02-2012 |
20120210098 | ENABLING VIRTUAL CALLS IN A SIMD ENVIRONMENT - Systems and methods of enabling virtual calls in a single instruction multiple data (SIMD) environment may involve detecting a virtual call of a function and using a single dispatch of the function to invoke the virtual call for two or more channels of the virtual call. In one example, it is determined that the two or more channels share a common target address and a single dispatch of the function is conducted with respect to the common target address. The process may be iterated for additional channels of the virtual call that share a common target address. | 08-16-2012 |
20130067200 | MFENCE AND LFENCE MICRO-ARCHITECTURAL IMPLEMENTATION METHOD AND SYSTEM - A system and method for fencing memory accesses. Memory loads can be fenced, or all memory access can be fenced. The system receives a fencing instruction that separates memory access instructions into older accesses and newer accesses. A buffer within the memory ordering unit is allocated to the instruction. The access instructions newer than the fencing instruction are stalled. The older access instructions are gradually retired. When all older memory accesses are retired, the fencing instruction is dispatched from the buffer. | 03-14-2013 |
20130073834 | MFENCE AND LFENCE MICRO-ARCHITECTURAL IMPLEMENTATION METHOD AND SYSTEM - A system and method for fencing memory accesses. Memory loads can be fenced, or all memory access can be fenced. The system receives a fencing instruction that separates memory access instructions into older accesses and newer accesses. A buffer within the memory ordering unit is allocated to the instruction. The access instructions newer than the fencing instruction are stalled. The older access instructions are gradually retired. When all older memory accesses are retired, the fencing instruction is dispatched from the buffer. | 03-21-2013 |
20130205117 | MFENCE AND LFENCE MICRO-ARCHITECTURAL IMPLEMENTATION METHOD AND SYSTEM - A system and method for fencing memory accesses. Memory loads can be fenced, or all memory access can be fenced. The system receives a fencing instruction that separates memory access instructions into older accesses and newer accesses. A buffer within the memory ordering unit is allocated to the instruction. The access instructions newer than the fencing instruction are stalled. The older access instructions are gradually retired. When all older memory accesses are retired, the fencing instruction is dispatched from the buffer. | 08-08-2013 |
20130305018 | MFENCE and LFENCE Micro-Architectural Implementation Method and System - A system and method for fencing memory accesses. Memory loads can be fenced, or all memory access can be fenced. The system receives a fencing instruction that separates memory access instructions into older accesses and newer accesses. A buffer within the memory ordering unit is allocated to the instruction. The access instructions newer than the fencing instruction are stalled. The older access instructions are gradually retired. When all older memory accesses are retired, the fencing instruction is dispatched from the buffer. | 11-14-2013 |
20140320509 | TECHNIQUES FOR GRAPHICS DATA PREFETCHING - Various embodiments are generally directed to techniques to prefetch pixel data of one or more pixels adjacent to a pixel for which pixel data is retrieved where the prefetched pixel data may be stored in noncontiguous storage locations. A device comprising a processor component and a hint generation component executed by the processor component to embed a prefetch hint in an executable read instruction, the executable read instruction to retrieve pixel data of a specified pixel and the prefetch hint to retrieve pixel data of an adjacent pixel that is geometrically adjacent to the specified pixel. Other embodiments are described and claimed. | 10-30-2014 |
20150046736 | Uncore Thermal Management - A method is described that involves controlling the traffic levels through an uncore to provide thermal management for the uncore. The method including determining if an uncore's temperature in a first uncore state is above a first threshold value and changing the first uncore state to a second uncore state if the uncore temperature is above the first threshold value. | 02-12-2015 |