Patent application number | Description | Published |
20100065914 | METHOD OF FORMING A SINGLE METAL THAT PERFORMS N AND P WORK FUNCTIONS IN HIGH-K/METAL GATE DEVICES - The present disclosure provides a method of fabricating a semiconductor device. The method includes providing a semiconductor substrate with a first region and a second region, forming a high-k dielectric layer over the semiconductor substrate, forming a metal layer over the high-k dielectric layer, the metal layer having a first work function, protecting the metal layer in the first region, treating the metal layer in the second region with a de-coupled plasma that includes carbon and nitrogen, and forming a first gate structure in the first region and a second gate structure in the second region. The first gate structure includes the high-k dielectric layer and the untreated metal layer. The second gate structure includes the high-k dielectric layer and the treated metal layer. | 03-18-2010 |
20130174982 | METAL HARD MASK FABRICATION - The present disclosure provides for methods of fabricating a metal hard mask and a metal hard mask fabricated by such methods. A method includes flowing at least one metal reactant gas into a reaction chamber configured to perform chemical vapor deposition (CVD), wherein the at least one metal reactant gas includes a metal-halogen gas or a metal-organic gas. The method further includes depositing a hard mask metal layer by CVD using the at least one metal reactant gas. | 07-11-2013 |
20140154848 | N/P METAL CRYSTAL ORIENTATION FOR HIGH-K METAL GATE Vt MODULATION - The present disclosure provides an integrated circuit. The integrated circuit includes a semiconductor substrate having a first region and a second region; a first gate stack of an n-type field-effect transistor (FET) in the first region; and a second gate stack of a p-type FET in the second region. The first gate stack includes a high k dielectric layer on the semiconductor substrate, a first crystalline metal layer in a first orientation on the high k dielectric layer, and a conductive material layer on the first crystalline metal layer. The second gate stack includes the high k dielectric layer on the semiconductor substrate, a second crystalline metal layer in a second orientation on the high k dielectric layer, and the conductive material layer on the second crystalline metal layer. | 06-05-2014 |
20140238864 | Layer by Layer Electro Chemical Plating (ECP) Process - The present disclosure relates to an electro-chemical plating (ECP) process that provides for an isotropic deposition, and a related apparatus. In some embodiments, the disclosed ECP process is performed by providing a substrate into an electroplating solution comprising a plurality of ions of a material to be deposited. A periodic patterned signal, which alternates between a first value and a different second value, is applied to the substrate. When the periodic patterned signal is at the first value, ions from the electroplating solution affix to the substrate. When the periodic patterned signal is at the second value, ions from the electroplating solution do not affix to the substrate. By using the periodic patterned signal to perform electro-chemical plating, the deposition rate of the plating process is reduced, resulting in an isotropic deposition over the substrate that mitigates gap fill problems (e.g., void formation). | 08-28-2014 |
20150146841 | METROLOGY DEVICE AND METROLOGY METHOD THEREOF - A metrology device includes a light source and an image sensor. The light source is configured for providing an X-ray illuminating a wafer. The image sensor is configured for detecting a spatial domain pattern produced when the X-ray illuminating the wafer. | 05-28-2015 |
20150152991 | MECHANISMS FOR SUPPLYING PROCESS GAS INTO WAFER PROCESS APPARATUS - Embodiments of mechanisms for processing a semiconductor wafer are provided. A method for processing a wafer includes providing a wafer process apparatus. The wafer process apparatus includes a chamber and a stage positioned in the chamber for supporting the semiconductor wafer. The method also includes supplying a process gas to the semiconductor wafer via a discharged assembly that is adjacent to the stage. The discharged assembly includes a discharged passage configured without a vertical flow path section. | 06-04-2015 |
20150206951 | SEMICONDUCTOR STRUCTURE AND MANUFACUTURING METHOD OF THE SAME - Some embodiments of the present disclosure provide a semiconductor structure. The semiconductor structure includes a substrate, a high k dielectric layer disposed over the substrate, and a gate layer over the high k dielectric layer. The high k dielectric layer is partially crystallized and comprising an average thickness of from about 10 Å to about 30 Å. Some embodiments of the present disclosure provide a method for manufacturing a semiconductor structure. The method includes (i) forming a high k dielectric layer with a thickness of from about 10 Å to about 30 Å over a substrate, (ii) forming a gate layer over the dielectric layer, and (iii) transforming at least a portion of the dielectric layer from a first phase to a second phase by microwave irradiation. | 07-23-2015 |