Patent application number | Description | Published |
20090115601 | Footwear with embedded tracking device and method of manufacture - Footwear with an embedded tracking device includes a sole and an upper. The tracking device is disposed in a cavity formed in the top surface of the sole. A wireless communication antenna and/or a location signal antenna is disposed on the upper. The antenna(s) is/are connected to the tracking device via a flexible circuit substrate. In a particular embodiment, the location signal antenna is a passive, directional GPS antenna supported in an upwardly facing position in the heel portion of the upper. A method for manufacturing footwear with an embedded tracking device is also disclosed. The method includes providing a footwear upper, incorporating an antenna in the footwear upper, providing a footwear sole, fixing the footwear upper to the footwear sole, incorporating a tracking device into the footwear sole, and connecting the tracking device to the antenna. | 05-07-2009 |
20110187528 | FOOTWEAR WITH EMBEDDED TRACKING DEVICE AND METHOD OF MANUFACTURE - Footwear with an embedded tracking device includes a sole and an upper. The tracking device is disposed in a cavity formed in the top surface of the sole. A wireless communication antenna and/or a location signal antenna is disposed on the upper. The antenna(s) is/are connected to the tracking device via a flexible circuit substrate. In a particular embodiment, the location signal antenna is a passive, directional GPS antenna supported in an upwardly facing position in the heel portion of the upper. A method for manufacturing footwear with an embedded tracking device is also disclosed. The method includes providing a footwear upper, incorporating an antenna in the footwear upper, providing a footwear sole, fixing the footwear upper to the footwear sole, incorporating a tracking device into the footwear sole, and connecting the tracking device to the antenna. | 08-04-2011 |
20130043994 | FOOTWEAR WITH EMBEDDED TRACKING DEVICE AND METHOD OF MANUFACTURE - Footwear with an embedded tracking device includes a sole and an upper. The tracking device is disposed in a cavity formed in the top surface of the sole. A wireless communication antenna and/or a location signal antenna is disposed on the upper. The antenna(s) is/are connected to the tracking device via a flexible circuit substrate. In a particular embodiment, the location signal antenna is a passive, directional GPS antenna supported in an upwardly facing position in the heel portion of the upper. A method for manufacturing footwear with an embedded tracking device is also disclosed. The method includes providing a footwear upper, incorporating an antenna in the footwear upper, providing a footwear sole, fixing the footwear upper to the footwear sole, incorporating a tracking device into the footwear sole, and connecting the tracking device to the antenna. | 02-21-2013 |
Patent application number | Description | Published |
20080217742 | TAILORED BIPOLAR TRANSISTOR DOPING PROFILE FOR IMPROVED RELIABILITY - Bipolar transistor device structures that improve bipolar device reliability with little or no negative impact on device performance. In one embodiment, the bipolar device has a collector of first conductivity type material formed in a substrate, a base of a second conductivity type material including an extrinsic base layer and an intrinsic base layer, a raised emitter of a first conductivity type semiconductor material formed on the intrinsic base layer, and, a dielectric material layer separating the intrinsic base region and the raised emitter region, and, a thin “shunt” layer of dopant of second conductivity type material added to the region below the emitter dielectric layer. In a second embodiment, a selectively implanted collector (pedestal implant) is added to the vertical bipolar transistor device to enable a reduction in overall subcollector doping level to improve reliability without sacrificing device performance. These solutions add no additional masking steps and only one additional implantation step. | 09-11-2008 |
20080268604 | METHODS OF BASE FORMATION IN A BiCMOS PROCESS - Methods for fabricating a heterojunction bipolar transistor having a raised extrinsic base is provided in which the base resistance is reduced by forming a silicide atop the raised extrinsic base that extends to the emitter region in a self-aligned manner. The silicide formation is incorporated into a BiCMOS process flow after the raised extrinsic base has been formed. The present invention also provides a heterojunction bipolar transistor having a raised extrinsic base and a silicide located atop the raised extrinsic base. The silicide atop the raised extrinsic base extends to the emitter in a self-aligned manner. The emitter is separated from the silicide by a spacer. | 10-30-2008 |
20090256174 | DEVICE STRUCTURES FOR A HIGH VOLTAGE JUNCTION FIELD EFFECT TRANSISTOR MANUFACTURED USING A HYBRID ORIENTATION TECHNOLOGY WAFER AND DESIGN STRUCTURES FOR A HIGH VOLTAGE INTEGRATED CIRCUIT - Device structures for a high voltage junction field effect transistor and design structures for a high voltage integrated circuit. The device structure is manufactured using a hybrid orientation technology wafer with a first semiconductor layer with a first crystalline orientation, a second semiconductor layer with a second crystalline orientation, and an insulating layer between the first and second semiconductor layers. The device structure includes an epitaxial semiconductor region having the second crystalline orientation and first and second p-n junctions in the epitaxial semiconductor region. The epitaxial semiconductor region extends from the second semiconductor layer through the insulating layer and the first semiconductor layer toward a top surface of the first semiconductor layer. The first and second p-n junctions are arranged in depth within the epitaxial semiconductor region between the second semiconductor layer and the top surface of the first semiconductor layer. | 10-15-2009 |
20090258464 | METHODS FOR MANUFACTURING A HIGH VOLTAGE JUNCTION FIELD EFFECT TRANSISTOR USING A HYBRID ORIENTATION TECHNOLOGY WAFER - Methods for manufacturing a high voltage junction field effect transistor. The method includes forming an opening extending from a top surface of a device layer of a hybrid orientation technology (HOT) wafer through the device layer and an insulating layer to expose a portion of a bulk layer, and filling the opening with epitaxial semiconductor material having the crystalline orientation of the bulk layer. The method further includes forming first and second p-n junctions in the epitaxial semiconductor material that are arranged in depth within the epitaxial semiconductor material between the second semiconductor layer and the top surface of the first semiconductor layer. | 10-15-2009 |
20110156223 | STRUCTURE AND METHOD TO CREATE STRESS TRENCH - An integrated circuit (IC) chip is provided comprising at least one trench including a stress-inducing material which imparts a stress on a channel region of a device, such as a junction gate field-effect transistor (JFET) or a metal-oxide-semiconductor field-effect transistor (MOSFET). A related method is also disclosed. | 06-30-2011 |
20110309471 | TRANSISTOR STRUCTURE WITH A SIDEWALL-DEFINED INTRINSIC BASE TO EXTRINSIC BASE LINK-UP REGION AND METHOD OF FORMING THE STRUCTURE - Disclosed are embodiments of an improved transistor structure (e.g., a bipolar transistor (BT) structure or heterojunction bipolar transistor (HBT) structure) and a method of forming the transistor structure. The structure embodiments can incorporate a dielectric layer sandwiched between an intrinsic base layer and a raised extrinsic base layer to reduce collector-base capacitance C | 12-22-2011 |
20150123655 | ELECTROSTATIC DISCHARGE PROTECTION FOR A MAGNETORESISTIVE SENSOR - A method of designing, for a magneto-resistive (MR) sensor, a protection circuit having a first and a second N-channel field-effect transistor (NFET) and at least one positive-negative (PN) diode is disclosed. The method may include determining a safe operating voltage range for the MR sensor and determining, within the safe operating voltage range, a normal operating voltage range for the MR sensor. The method may also include determining a protection threshold voltage range outside of the normal operating voltage range and within the safe operating voltage range of the MR sensor. The method may also include selecting device parameters to configure the first and second NFETs and the at least one PN diode to, in response to a voltage applied to the MR sensor being within a protection threshold voltage range, limit, by shunting current, the voltage applied to the MR sensor. | 05-07-2015 |
Patent application number | Description | Published |
20120326766 | Silicon Controlled Rectifier with Stress-Enhanced Adjustable Trigger Voltage - Device structures, fabrication methods, operating methods, and design structures for a silicon controlled rectifier. The method includes applying a mechanical stress to a region of a silicon controlled rectifier (SCR) at a level sufficient to modulate a trigger current of the SCR. The device and design structures include a SCR with an anode, a cathode, a first region, and a second region of opposite conductivity type to the first region. The first and second regions of the SCR are disposed in a current-carrying path between the anode and cathode of the SCR. A layer is positioned on a top surface of a semiconductor substrate relative to the first region and configured to cause a mechanical stress in the first region of the SCR at a level sufficient to modulate a trigger current of the SCR. | 12-27-2012 |
20130313607 | Silicon Controlled Rectifier With Stress-Enhanced Adjustable Trigger Voltage - Device structures, fabrication methods, operating methods, and design structures for a silicon controlled rectifier. The method includes applying a mechanical stress to a region of a silicon controlled rectifier (SCR) at a level sufficient to modulate a trigger current of the SCR. The device and design structures include a SCR with an anode, a cathode, a first region, and a second region of opposite conductivity type to the first region. The first and second regions of the SCR are disposed in a current-carrying path between the anode and cathode of the SCR. A layer is positioned on a top surface of a semiconductor substrate relative to the first region and configured to cause a mechanical stress in the first region of the SCR at a level sufficient to modulate a trigger current of the SCR. | 11-28-2013 |
20160118138 | PROGRAMMING AN ELECTRICAL FUSE WITH A SILICON-CONTROLLED RECTIFIER - Circuits for programming an electrical fuse, methods for programming an electrical fuse, and methods for designing a silicon-controlled rectifier for use in programming an electrical fuse. A programming current for the electrical fuse is directed through the electrical fuse and the silicon-controlled rectifier. Upon reaching a programmed resistance value for the electrical fuse, the silicon-controlled rectifier switches from a low-impedance state to a high-impedance state that interrupts the programming current. | 04-28-2016 |