| Patent application number | Description | Published |
|---|
| 20090112960 | System and Method for Providing a Double Adder for Decimal Floating Point Operations - A method for implementing an adder including receiving a first and second operand. A sum of one or more corresponding digits from the first operand and the second operand is calculated. The calculating is performed by a plurality of adder blocks. Output from the calculating includes the sum of the corresponding digits and a carry out indicator for the corresponding digits. The sums of the corresponding digits and the carry out indicators in a carry chain are stored in an intermediate result register. Each of the sums in the intermediate result register is incremented by one. A selection between each of the sums and the sums incremented by one is performed. Input to the selecting includes the carry chain, and the output from the selecting includes a final sum of the first operand and the second operand. The final sum is stored in an output register. | 04-30-2009 |
| 20090132627 | Method for Performing Decimal Floating Point Addition - A method for performing a decimal floating point operation including receiving a first operand having a first coefficient and a first exponent into a first register. A second operand having a second coefficient and a second exponent are received into a second register. An operation, either addition or subtraction, associated with the first operand and the second operand is received. Three concurrent calculations are performed on the first operand and the second operand. The three concurrent calculations include: applying the operation to the first operand and the second operand based on a first assumption; applying the operation to the first operand and the second operand based on a second assumption; and applying the operation to the first operand and the second operand based on a third assumption. A final result is selected from the first result, the second result and the third result. | 05-21-2009 |
| 20090132628 | Method for Performing Decimal Division - A method for performing decimal division including receiving a scaled divisor and a scaled dividend into input registers. A subset of multiples of the scaled divisor is stored in a plurality of multiples registers. Quotient digits are calculated in response to the scaled divisor and the scaled dividend. Each quotient digit is calculated in three clock cycles by a pipeline mechanism. The calculating includes selecting a new quotient digit, and calculating a new remainder. Input to the calculating a new remainder includes data from one or more of the multiples registers. | 05-21-2009 |
| 20090132629 | Method for Providing a Decimal Multiply Algorithm Using a Double Adder - A method for performing decimal multiplication including storing a multiplier and a multiplicand in operand registers, the multiplier including one or more digits. A running sum is stored in a shifter and initialized to zero. The method includes performing for each of the digits in the multiplier in order from least significant digit to most significant digit: creating a partial product of the digit and the multiplicand and adding the partial product to the running sum. The running sum is output as the result of multiplying the multiplier and the multiplicand. The performing and outputting are implemented by a mechanism that includes one or more two cycle adders connected to the operand registers, multiplicand multiples circuitry connected to the operand registers, and a result digits register connected to the two cycle adders. | 05-21-2009 |
| 20090210472 | METHOD, SYSTEM AND COMPUTER PROGRAM PRODUCT FOR IDENTIFYING DECIMAL FLOATING POINT ADDITION OPERATIONS THAT DO NOT REQUIRE ALIGNMENT, NORMALIZATION OR ROUNDING - A method, computer program product and a system for identifying decimal floating point addition operations that guarantee operand alignment and do not require alignment, normalization or rounding are provided. The method includes: receiving an instruction to perform an addition of a first operand and a second operand; extracting a first exponent (EXP) and a first most significant digit (MSD) from the first operand; extracting a second EXP and a second MSD from the second operand; and determining whether alignment between the first operand and the second operand is guaranteed, based on the first EXP, the first MSD, the second EXP and the second MSD. | 08-20-2009 |
| 20090210659 | PROCESSOR AND METHOD FOR WORKAROUND TRIGGER ACTIVATED EXCEPTIONS - A processor includes a microarchitecture for working around a processing flaw, the microarchitecture including: at least one detector adapted for detecting a predetermined state associated with the processing flaw; and at least one mechanism to modify default processor processing behavior; and upon modification of processing behavior, the processing of an instruction involving the processing flaw can be completed by avoiding the processing flaw. | 08-20-2009 |
| 20090240753 | METHOD, HARDWARE PRODUCT, AND COMPUTER PROGRAM PRODUCT FOR USING A DECIMAL FLOATING POINT UNIT TO EXECUTE FIXED POINT INSTRUCTIONS - A decimal floating point (DFP) unit is used to execute fixed point instructions. Two or more operands are accepted, wherein each operand is in a packed binary coded decimal (BCD) format. Any invalid BCD formats are detected by checking the operands for any invalid BCD codes. It is determined if an exception flag exists and, if so, outputting the flag; it is determined if a condition code exists and, if so, outputting the code. An operation is performed on the two or more operands to generate a result; wherein the operation takes place directly on BCD data, thus using the DFP unit to perform a BCD operation; appending a result sign to the result of the operation; and providing the result of the operation and the appended result sign as a result output in a packed BCD format. | 09-24-2009 |
| 20100306632 | ERROR DETECTION USING PARITY COMPENSATION IN BINARY CODED DECIMAL AND DENSELY PACKED DECIMAL CONVERSIONS - Error detection using parity compensation in binary coded decimal (BCD) and densely packed decimal (DPD) conversions, including a computer program product having a tangible storage medium readable by a processing circuit and storing instructions for execution by the processing circuit for performing a method. The method includes receiving formatted decimal data in a first format, the formatted decimal data consisting of a DPD format data or a BCD format data. One or more first parity bits are generated by converting the received data into a second format of the formatted decimal data, and by determining the parity of the data in the second format. One or more second parity bits are generated directly from the received data. An error flag is set to indicate an error in the data in the second format in response to the first parity bits not being equal to the second parity bits. | 12-02-2010 |
| 20110131266 | Decimal Floating Point Multiplier and Design Structure - Several implementations and a design structure for decimal multiplication that uses a BCD 4221 encoding scheme, separate accumulation of partial products, accumulation of the partial products into a final product and conversion from and to a BCD 8421 coding scheme. | 06-02-2011 |
| 20130339802 | DYNAMIC HARDWARE TRACE SUPPORTING MULTIPHASE OPERATIONS - A method and system for tracing in a data processing system. The method includes receiving a plurality of signals associated with an operation during execution of the operation. The method also includes, in response to an indication that the operation is a multiphase operation, during execution of the operation, selection logic, during a first phase of the multiphase operation, selecting and outputting as a trace signal a first signal of the plurality of signals, and during a second phase of the multiphase operation, selecting and outputting as the trace signal a second signal of the plurality of signals. | 12-19-2013 |
| 20140089732 | THREAD SPARING BETWEEN CORES IN A MULTI-THREADED PROCESSOR - Embodiments relate to thread sparing between cores in a processor. An aspect includes determining that a number of recovery attempts made by a first thread on the first core has exceeded a recovery attempt threshold, and sending a request to transfer the first thread. Another aspect includes, selecting a second core from a plurality of cores to receive the first thread from the first core, wherein the second core is selected based on the second core having an idle thread. Another aspect includes transferring a last good architected state of the first thread from the first core to the second core. Another aspect includes loading the last good architected state of the first thread by the idle thread on the second core. Yet another aspect includes resuming execution of the first thread on the second core from the last good architected state of the first thread by the idle thread. | 03-27-2014 |
| 20140089734 | THREAD SPARING BETWEEN CORES IN A MULTI-THREADED PROCESSOR - Embodiments relate to thread sparing between cores in a processor. An aspect includes determining that a number of recovery attempts made by a first thread on the first core has exceeded a recovery attempt threshold, and sending a request to transfer the first thread. Another aspect includes, selecting a second core from a plurality of cores to receive the first thread from the first core, wherein the second core is selected based on the second core having an idle thread. Another aspect includes transferring a last good architected state of the first thread from the first core to the second core. Another aspect includes loading the last good architected state of the first thread by the idle thread on the second core. Yet another aspect includes resuming execution of the first thread on the second core from the last good architected state of the first thread by the idle thread. | 03-27-2014 |
| 20140095941 | DYNAMIC HARDWARE TRACE SUPPORTING MULTIPHASE OPERATIONS - A method and system for tracing in a data processing system. The method includes receiving a plurality of signals associated with an operation during execution of the operation. The method also includes, in response to an indication that the operation is a multiphase operation, during execution of the operation, selection logic, during a first phase of the multiphase operation, selecting and outputting as a trace signal a first signal of the plurality of signals, and during a second phase of the multiphase operation, selecting and outputting as the trace signal a second signal of the plurality of signals. | 04-03-2014 |
| 20140149481 | Decimal Multi-Precision Overflow and Tininess Detection - An approach is provided in which a processor includes an adder that concurrently generates one or more intermediate results and a boundary indicator based upon instructions retrieved from a memory area. The boundary indicator indicates whether a collective result generated from the intermediate results is within a boundary precision value. | 05-29-2014 |
| 20140201508 | CONFIDENCE THRESHOLD-BASED OPPOSING BRANCH PATH EXECUTION FOR BRANCH PREDICTION - Embodiments relate to confidence threshold-based opposing path execution for branch prediction. An aspect includes determining a branch prediction for a first branch instruction that is encountered during execution of a first thread, wherein the branch prediction indicates a primary path and an opposing path for the first branch instruction. Another aspect includes executing the primary path by the first thread. Another aspect includes determining a confidence of the branch prediction and comparing the confidence of the branch prediction to a confidence threshold. Yet another aspect includes, based on the confidence of the branch prediction being less than the confidence threshold, starting a second thread that executes the opposing path of the first branch instruction, wherein the second thread is executed in parallel with the first thread. | 07-17-2014 |
| 20150058607 | CONFIDENCE THRESHOLD-BASED OPPOSING BRANCH PATH EXECUTION FOR BRANCH PREDICTION - Embodiments relate to confidence threshold-based opposing path execution for branch prediction. An aspect includes determining a branch prediction for a first branch instruction that is encountered during execution of a first thread, wherein the branch prediction indicates a primary path and an opposing path for the first branch instruction. Another aspect includes executing the primary path by the first thread. Another aspect includes determining a confidence of the branch prediction and comparing the confidence of the branch prediction to a confidence threshold. Yet another aspect includes, based on the confidence of the branch prediction being less than the confidence threshold, starting a second thread that executes the opposing path of the first branch instruction, wherein the second thread is executed in parallel with the first thread. | 02-26-2015 |
