Patent application number | Description | Published |
20080315274 | DEEP TRENCH CAPACITOR AND METHOD OF MAKING SAME - A trench capacitor and method of forming a trench capacitor. The trench capacitor including: a trench in a single-crystal silicon substrate, a conformal dielectric liner on the sidewalls and the bottom of the trench; an electrically conductive polysilicon inner plate filling regions of the trench not filled by the liner; an electrically conductive doped outer plate in the substrate surrounding the sidewalls and the bottom of the trench; a doped silicon region in the substrate; a first electrically conductive metal silicide layer on a surface region of the doped silicon region exposed at the top surface of the substrate; a second electrically conductive metal silicide layer on a surface region of the inner plate exposed at the top surface of the substrate; and an insulating ring on the top surface of the substrate between the first and second metal silicide layers. | 12-25-2008 |
20090095998 | DEEP TRENCH CAPACITOR AND METHOD - Disclosed herein are embodiments of a deep trench capacitor structure and a method of forming the structure that incorporates a buried capacitor plate contact that is simultaneously formed using an adjacent deep trench. This configuration eliminates the need for additional photolithographic processing, thereby, optimizing process windows. This configuration further eliminates the need to form the deep trench capacitor through an N-doped diffusion region connector and, thereby, allows for greater design flexibility when connecting the deep trench capacitor to another integrated circuit structure (e.g., a memory cell or decoupling capacitor array). Also, disclosed herein are embodiments of another integrated circuit structure and method, and more specifically, a memory cell (e.g., a static random access memory (SRAM) cell)) and method of forming the memory cell that incorporates one or more of these deep trench capacitors in order to minimize or eliminate soft errors. | 04-16-2009 |
20090100388 | DEEP TRENCH CAPACITOR AND METHOD OF MAKING SAME - A trench capacitor, method of forming a trench capacitor and a design structure for a trench capacitor. The trench capacitor including: a trench in a single-crystal silicon substrate, a conformal dielectric liner on the sidewalls and the bottom of the trench; an electrically conductive polysilicon inner plate filling regions of the trench not filled by the liner; an electrically conductive doped outer plate in the substrate surrounding the sidewalls and the bottom of the trench; a doped silicon region in the substrate; a first electrically conductive metal silicide layer on a surface region of the doped silicon region exposed at the top surface of the substrate; a second electrically conductive metal silicide layer on a surface region of the inner plate exposed at the top surface of the substrate; and an insulating ring on the top surface of the substrate between the first and second metal silicide layers. | 04-16-2009 |
20100025813 | STRUCTURE FOR DUAL CONTACT TRENCH CAPACITOR AND STRUCTURE THEROF - A dual contact trench capacitor and design structure for a dual contact trench capacitor is provided. The structure includes a first plate extending from a trench and isolated from a wafer body, and a second plate extending from the trench and isolated from the wafer body and the first plate. | 02-04-2010 |
20100025814 | STRUCTURE FOR DUAL CONTACT TRENCH CAPACITOR AND STRUCTURE THEREOF - A dual contact trench capacitor and design structure for a dual contact trench capacitor is provided. The structure includes a first plate extending from a trench and isolated from a wafer body, and a second plate extending from the trench and isolated from the wafer body and the first plate. | 02-04-2010 |
20100029055 | METHOD OF MANUFACTURING A DUAL CONTACT TRENCH CAPACITOR. - A method of manufacturing a dual contact trench capacitor is provided. The method includes forming a first plate provided within a trench and isolated from a wafer body by a first insulator layer formed in the trench. The method further includes forming a second plate provided within the trench and isolated from the wafer body and the first plate by a second insulator layer formed in the trench. | 02-04-2010 |
20100029056 | METHOD OF MANUFACTURING A DUAL CONTACT TRENCH CAPACITOR - A method of manufacturing a dual contact trench capacitor is provided. The method includes a first plate extending from a trench and isolated from a wafer body, and forming a second plate extending from the trench and isolated from the wafer body and the first plate. | 02-04-2010 |
20120149133 | MEMS PROCESS METHOD FOR HIGH ASPECT RATIO STRUCTURES - Methods for the controlled manufacture of high aspect ratio features. The method may include forming a layer stack on a top surface of a substrate and forming features in the layers of the layer stack. The high aspect ratio features may be defined using a resist layer that is patterned with a photolithographic condition. After removing at least one of the layers removed from the top of the layer stack, a feature dimension may be measured for features at different locations on the substrate. The method may further include changing the photolithographic condition based on the measured dimension and processing another substrate using the changed photolithographic condition. | 06-14-2012 |
20120205776 | DUAL CONTACT TRENCH RESISTOR IN SHALLOW TRENCH ISOLATION (STI) AND METHODS OF MANUFACTURE - The invention relates to a semiconductor structures and methods of manufacture and, more particularly, to a dual contact trench resistor in shallow trench isolation (STI) and methods of manufacture. In a first aspect of the invention, a method comprises forming a trench in a substrate; forming a first insulator layer within the trench; forming a first electrode within the trench, on the first insulator layer, and isolated from the substrate by the first insulator layer; forming a second insulator layer within the trench and on the first electrode; and forming a second electrode within the trench, on the second insulator layer, and isolated from the substrate by the first insulator layer and the second insulator layer. | 08-16-2012 |
20120299152 | DUAL CONTACT TRENCH RESISTOR AND CAPACITOR IN SHALLOW TRENCH ISOLATION (STI) AND METHODS OF MANUFACTURE - A resistor and capacitor are provided in respective shallow trench isolation structures. The method includes forming a first and second trench in a substrate and forming a first insulator layer within the first and second trench. The method includes forming a first electrode material within the first and second trench, on the first insulator layer, and forming a second insulator layer within the first and second trench and on the first electrode material. The method includes forming a second electrode material within the first and second trench, on the second insulator layer. The second electrode material pinches off the second trench. The method includes removing a portion of the second electrode material and the second insulator layer at a bottom portion of the first trench, and filling in the first trench with additional second electrode material. The additional second electrode material is in electrical contact with the first electrode material. | 11-29-2012 |
20130292798 | DUAL CONTACT TRENCH RESISTOR AND CAPACITOR IN SHALLOW TRENCH ISOLATION (STI) AND METHODS OF MANUFACTURE - A resistor and capacitor are provided in respective shallow trench isolation structures. The method includes forming a first and second trench in a substrate and forming a first insulator layer within the first and second trench. The method includes forming a first electrode material within the first and second trench, on the first insulator layer, and forming a second insulator layer within the first and second trench and on the first electrode material. The method includes forming a second electrode material within the first and second trench, on the second insulator layer. The second electrode material pinches off the second trench. The method includes removing a portion of the second electrode material and the second insulator layer at a bottom portion of the first trench, and filling in the first trench with additional second electrode material. The additional second electrode material is in electrical contact with the first electrode material. | 11-07-2013 |
20140027826 | GERMANIUM PHOTODETECTOR SCHOTTKY CONTACT FOR INTEGRATION WITH CMOS AND Si NANOPHOTONICS - A method of forming an integrated photonic semiconductor structure having a photodetector device and a CMOS device may include depositing a dielectric stack over the photodetector device such that the dielectric stack encapsulates the photodetector. An opening is etched into the dielectric stack down to an upper surface of a region of an active area of the photodetector. A first metal layer is deposited directly onto the upper surface of the region of the active area via the opening such that the first metal layer may cover the region of the active area. Within the same mask level, a plurality of contacts including a second metal layer are located on the first metal layer and on the CMOS device. The first metal layer isolates the active area from the occurrence of metal intermixing between the second metal layer and the active area of the photodetector. | 01-30-2014 |
20140185981 | SILICON PHOTONICS PHOTODETECTOR INTEGRATION - A method of forming an integrated photonic semiconductor structure having a photonic device and adjacent CMOS devices may include depositing a first silicon nitride layer over the adjacent CMOS devices and depositing an oxide layer over the first silicon nitride layer, wherein the oxide layer conformally covers the first silicon nitride layer and the underlying adjacent CMOS devices to form a substantially planarized surface over the adjacent CMOS devices. A second silicon nitride layer is then deposited over the oxide layer and a region corresponding to forming the photonic device. A germanium layer is deposited over the oxide layer and the region corresponding to forming the photonic device. The germanium layer deposited over the adjacent CMOS devices is etched to form a germanium active layer within the photonic region, whereby the oxide layer and the second silicon nitride layer protect the adjacent CMOS devices during the etching of the germanium. | 07-03-2014 |
20140191302 | PHOTONICS DEVICE AND CMOS DEVICE HAVING A COMMON GATE - A semiconductor chip having a photonics device and a CMOS device which includes a photonics device portion and a CMOS device portion on a semiconductor chip; a metal or polysilicon gate on the CMOS device portion, the metal or polysilicon gate having a gate extension that extends toward the photonics device portion; a germanium gate on the photonics device portion such that the germanium gate is coplanar with the metal or polysilicon gate, the germanium gate having a gate extension that extends toward the CMOS device portion, the germanium gate extension and metal or polysilicon gate extension joined together to form a common gate; spacers formed on the germanium gate and the metal or polysilicon gate; and nitride encapsulation formed on the germanium gate. A method is also disclosed pertaining to fabricating the semiconductor chip. | 07-10-2014 |
20140191326 | PHOTONICS DEVICE AND CMOS DEVICE HAVING A COMMON GATE - A semiconductor chip having a photonics device and a CMOS device which includes a photonics device portion and a CMOS device portion on a semiconductor chip; a metal or polysilicon gate on the CMOS device portion, the metal or polysilicon gate having a gate extension that extends toward the photonics device portion; a germanium gate on the photonics device portion such that the germanium gate is coplanar with the metal or polysilicon gate, the germanium gate having a gate extension that extends toward the CMOS device portion, the germanium gate extension and metal or polysilicon gate extension joined together to form a common gate; spacers formed on the germanium gate and the metal or polysilicon gate; and nitride encapsulation formed on the germanium gate. | 07-10-2014 |
20140197507 | BURIED WAVEGUIDE PHOTODETECTOR - A method of forming an integrated photonic semiconductor structure having a photodetector and a CMOS device may include forming the CMOS device on a first silicon-on-insulator region, forming a silicon optical waveguide on a second silicon-on-insulator region, and forming a shallow trench isolation (STI) region surrounding the silicon optical waveguide such that the shallow trench isolation electrically isolating the first and second silicon-on-insulator region. Within a first region of the STI region, a first germanium material is deposited adjacent a first side wall of the semiconductor optical waveguide. Within a second region of the STI region, a second germanium material is deposited adjacent a second side wall of the semiconductor optical waveguide, whereby the second side wall opposes the first side wall. The first and second germanium material form an active region that evanescently receives propagating optical signals from the first and second side wall of the semiconductor optical waveguide. | 07-17-2014 |
20140209985 | GERMANIUM PHOTODETECTOR SCHOTTKY CONTACT FOR INTEGRATION WITH CMOS AND Si NANOPHOTONICS - A method of forming an integrated photonic semiconductor structure having a photodetector device and a CMOS device may include depositing a dielectric stack over the photodetector device such that the dielectric stack encapsulates the photodetector. An opening is etched into the dielectric stack down to an upper surface of a region of an active area of the photodetector. A first metal layer is deposited directly onto the upper surface of the region of the active area via the opening such that the first metal layer may cover the region of the active area. Within the same mask level, a plurality of contacts including a second metal layer are located on the first metal layer and on the CMOS device. The first metal layer isolates the active area from the occurrence of metal intermixing between the second metal layer and the active area of the photodetector. | 07-31-2014 |
20140217485 | STRESS ENGINEERED MULTI-LAYERS FOR INTEGRATION OF CMOS AND Si NANOPHOTONICS - A method of forming an integrated photonic semiconductor structure having a photonic device and a CMOS device may include depositing a first silicon nitride layer having a first stress property over the photonic device, depositing an oxide layer having a stress property over the deposited first silicon nitride layer, and depositing a second silicon nitride layer having a second stress property over the oxide layer. The deposited first silicon nitride layer, the oxide layer, and the second silicon nitride layer encapsulate the photonic device. | 08-07-2014 |
20140312443 | BUTT-COUPLED BURIED WAVEGUIDE PHOTODETECTOR - A method of forming an integrated photonic semiconductor structure having a photodetector and a CMOS device may include forming the CMOS device on a first silicon-on-insulator region, forming a silicon optical waveguide on a second silicon-on-insulator region, and forming a shallow trench isolation (STI) region surrounding the silicon optical waveguide such that the shallow trench isolation electrically isolates the first and second silicon-on-insulator region. Within the STI region, a germanium material is deposited adjacent an end facet of the semiconductor optical waveguide. The germanium material forms an active region that receives propagating optical signals from the end facet of the semiconductor optical waveguide. | 10-23-2014 |
20140353759 | Self-Aligned Gate Electrode Diffusion Barriers - A self-aligned diffusion barrier may be formed by forming a first masking layer, having a vertical sidewall on a semiconductor layer, above a first portion of the semiconductor layer. A first spacer layer, including a spacer region on the vertical sidewall, may be formed above the semiconductor layer. A second portion of the semiconductor layer not covered by the first masking layer or the spacer region may then be doped. A second masking layer may then be formed over the first spacer layer and planarized to expose at least a portion of the spacer region. The spacer region may then be etched to form a notch exposing a third portion of the semiconductor layer. The third portion may then be doped with a barrier dopant. The first masking layer may be removed and a second spacer layer filling the notch may be formed. The first portion may then be doped. | 12-04-2014 |
20150035076 | Self-Aligned Gate Electrode Diffusion Barriers - A structure that provides a diffusion barrier between two doped regions. The structure includes a diffusion barrier including a semiconductor layer comprising a first doped region and a second doped region; and a diffusion barrier separating the first doped region and the second doped region, wherein the diffusion barrier comprises a doped portion and a notch above the doped portion. | 02-05-2015 |
20150054041 | CMOS PROTECTION DURING GERMANIUM PHOTODETECTOR PROCESSING - A method of protecting a CMOS device within an integrated photonic semiconductor structure is provided. The method may include depositing a conformal layer of germanium over the CMOS device and an adjacent area to the CMOS device, depositing a conformal layer of dielectric hardmask over the germanium, and forming, using a mask level, a patterned layer of photoresist for covering the CMOS device and a photonic device formation region within the adjacent area. Openings are etched into areas of the deposited layer of silicon nitride not covered by the patterned photoresist, such that the areas are adjacent to the photonic device formation region. The germanium material is then etched from the conformal layer of germanium at a location underlying the etched openings for forming the photonic device at the photonic device formation region. The conformal layer of germanium deposited over the CMOS device protects the CMOS device. | 02-26-2015 |