Patent application number | Description | Published |
20080217730 | METHODS OF FORMING GAS DIELECTRIC AND RELATED STRUCTURE - Methods of forming a gas dielectric and a related structure are disclosed. In one embodiment, the method includes providing a wiring level including at least one conductive portion within a sacrificial dielectric; forming a nanofiber layer over the wiring level; vaporizing the sacrificial dielectric by heating; evacuating the vaporized sacrificial layer; and sealing pores in the nanofiber layer. | 09-11-2008 |
20080225251 | Immersion optical lithography system having protective optical coating - An immersion lithography system is provided which includes an optical source operable to produce light having a nominal wavelength and an optical imaging system. The optical imaging system has an optical element in an optical path from the optical source to an article to be patterned thereby. The optical element has a face which is adapted to contact a liquid occupying a space between the face and the article. The optical element includes a material which is degradable by the liquid and a protective coating which covers the degradable material at the face for protecting the face from the liquid, the protective coating being transparent to the light, stable when exposed to the light and stable when exposed to the liquid. | 09-18-2008 |
20080242041 | Selective Deposition of Germanium Spacers on Nitride - A method of selectively forming a germanium structure within semiconductor manufacturing processes removes the native oxide from a nitride surface in a chemical oxide removal (COR) process and then exposes the heated nitride and oxide surface to a heated germanium containing gas to selectively form germanium only on the nitride surface but not the oxide surface. | 10-02-2008 |
20080257156 | Carbon Nanotubes As Low Voltage Field Emission Sources for Particle Precipitators - An air particle precipitator and a method of air filtration comprise a housing unit; a first conductor in the housing unit; a second conductor in the housing unit; and a carbon nanotube grown on the second conductor. Preferably, the first conductor is positioned opposite to the second conductor. The air particle precipitator further comprises an electric field source adapted to apply an electric field to the housing unit. Moreover, the carbon nanotube is adapted to ionize gas in the housing unit, wherein the ionized gas charges gas particulates located in the housing unit, and wherein the first conductor is adapted to trap the charged gas particulates. The air particle precipitator may further comprise a metal layer over the carbon nanotube. | 10-23-2008 |
20080271606 | CHEMICAL AND PARTICULATE FILTERS CONTAINING CHEMICALLY MODIFIED CARBON NANOTUBE STRUCTURES - A carbon nanotube filter, a use for a carbon nanotube filter and a method of forming a carbon nanotube filter. The method including (a) providing a carbon source and a carbon nanotube catalyst; (b) growing carbon nanotubes by reacting the carbon source with the nanotube catalyst; (c) forming chemically active carbon nanotubes by forming a chemically active layer on the carbon nanotubes or forming chemically reactive groups on sidewalls of the carbon nanotubes; and (d) placing the chemically active nanotubes in a filter housing. | 11-06-2008 |
20080282893 | CHEMICAL AND PARTICULATE FILTERS CONTAINING CHEMICALLY MODIFIED CARBON NANOTUBE STRUCTURES - A carbon nanotube filter. The filter including a filter housing; and chemically active carbon nanotubes within the filter housing, the chemically active carbon nanotubes comprising a chemically active layer formed on carbon nanotubes or comprising chemically reactive groups on sidewalls of the carbon nanotubes; and media containing the chemically active carbon nanotubes. | 11-20-2008 |
20080284992 | EXPOSURES SYSTEM INCLUDING CHEMICAL AND PARTICULATE FILTERS CONTAINING CHEMICALLY MODIFIED CARBON NANOTUBE STRUCTURES - An exposure system for exposing a photoresist layer on a top surface of a wafer to light. The exposure system including: an environment chamber containing a light source, one or more focusing lenses, a mask holder, a slit and a wafer stage, the light source, all aligned to an optical axis, the wafer stage moveable in two different orthogonal directions orthogonal to the optical axis, the mask holder and the slit moveable in one of the two orthogonal directions; a filter in a sidewall of the environment chamber, the filter including: a filter housing containing chemically active carbon nanotubes, the chemically active carbon nanotubes comprising a chemically active layer formed on carbon nanotubes or comprising chemically reactive groups on sidewalls of the carbon nanotubes; and means for forcing air or inert gas first through the filter then into the environment chamber and then out of the environment chamber. | 11-20-2008 |
20080286466 | CHEMICAL AND PARTICULATE FILTERS CONTAINING CHEMICALLY MODIFIED CARBON NANOTUBE STRUCTURES - A carbon nanotube filter, a use for a carbon nanotube filter and a method of forming a carbon nanotube filter. The method including (a) providing a carbon source and a carbon nanotube catalyst; (b) growing carbon nanotubes by reacting the carbon source with the nanotube catalyst; (c) forming chemically active carbon nanotubes by forming a chemically active layer on the carbon nanotubes or forming chemically reactive groups on sidewalls of the carbon nanotubes; and (d) placing the chemically active nanotubes in a filter housing. | 11-20-2008 |
20080286971 | CMOS Gate Structures Fabricated by Selective Oxidation - A sidewall image transfer process for forming sub-lithographic structures employs a layer of sacrificial material that is deposited over a structure layer and covered by a cover layer. The sacrificial material layer and the cover layer are patterned with conventional resist and etched to form a sacrificial mandrel. The edges of the mandrel are oxidized or nitrided in a plasma at low temperature, after which the material layer and the cover layer are stripped, leaving sublithographic sidewalls. The sidewalls are used as hardmasks to etch sublithographic gate structures in the gate conductor layer. | 11-20-2008 |
20090001337 | Phase Change Memory Cell with Vertical Transistor - A memory cell in an integrated circuit is fabricated in part by forming a lower electrode feature, an island, a sacrificial feature, a gate feature, and a phase change feature. The island is formed on the lower electrode feature and has one or more sidewalls. It comprises a lower doped feature, a middle doped feature formed above the lower doped feature, and an upper doped feature formed above the middle doped feature. The sacrificial feature is formed above the island, while the gate feature is formed along each sidewall of the island. The gate feature overlies at least a portion of the middle doped feature of the island and is operative to control an electrical resistance therein. Finally, the phase feature is formed above the island at least in part by replacing at least a portion of the sacrificial feature with a phase change material. The phase change material is operative to switch between lower and higher electrical resistance states in response to an application of an electrical signal. | 01-01-2009 |
20090014767 | CARBON NANOTUBE CONDUCTOR FOR TRENCH CAPACITORS - A trench-type storage device includes a trench in a substrate ( | 01-15-2009 |
20090032491 | CONDUCTIVE ELEMENT FORMING USING SACRIFICIAL LAYER PATTERNED TO FORM DIELECTRIC LAYER - Methods of forming a conductive element for an integrated circuit (IC) chip and a related structure are disclosed. One embodiment of the method may include forming a first sacrificial layer having a pattern therein for a first dielectric layer to surround the conductive element; forming the first dielectric layer within the patterned first sacrificial layer; removing the patterned first sacrificial layer, leaving the first dielectric layer; and forming the conductive element in a space vacated by the patterned first sacrificial layer. The methods prevent damage caused to low dielectric constant dielectric layers during etching and stripping/cleaning processes. | 02-05-2009 |
20090057730 | METHODS FOR FORMING SELF-ALIGNED BORDERLESS CONTACTS FOR STRAIN ENGINEERED LOGIC DEVICES AND STRUCTURE THEREOF - A method for forming a borderless contact for a semiconductor FET (Field Effect Transistor) device, the method comprising, forming a gate conductor stack on a substrate, forming spacers on the substrate, such that the spacers and the gate conductor stack partially define a volume above the gate conductor stack, wherein the spacers are sized to define the volume such that a stress liner layer deposited on the gate conductor stack substantially fills the volume, depositing a liner layer on the substrate, the spacers, and the gate conductor stack, depositing a dielectric layer on the liner layer, etching to form a contact hole in the dielectric layer, etching to form the contact hole in the liner layer, such that a portion of a source/drain diffusion area formed in the substrate is exposed and depositing contact metal in the contact hole. | 03-05-2009 |
20090072317 | MICROELECTRONIC STRUCTURE BY SELECTIVE DEPOSITION - A finFET structure includes a semiconductor fin located over a substrate. A gate electrode is located traversing the semiconductor fin. The gate electrode has a spacer layer located adjoining a sidewall thereof. The spacer layer does not cover completely a sidewall of the semiconductor fin. The gate electrode and the spacer layer may be formed using a vapor deposition method that provides for selective deposition upon a sidewall of a mandrel layer but not upon an adjoining surface of the substrate, so that the spacer layer does not cover completely the sidewall of the semiconductor fin. Other microelectronic structures may be fabricated using the lateral growth methodology. | 03-19-2009 |
20090075439 | MICROELECTRONIC STRUCTURE BY SELECTIVE DEPOSITION - A finFET structure includes a semiconductor fin located over a substrate. A gate electrode is located traversing the semiconductor fin. The gate electrode has a spacer layer located adjoining a sidewall thereof. The spacer layer does not cover completely a sidewall of the semiconductor fin. The gate electrode and the spacer layer may be formed using a vapor deposition method that provides for selective deposition upon a sidewall of a mandrel layer but not upon an adjoining surface of the substrate so that the spacer layer does not cover completely the sidewall of the semiconductor fin. Other microelectronic structures may be fabricated using the lateral growth methodology. | 03-19-2009 |
20090087795 | METHOD AND APPARATUS FOR CLEANING A SEMICONDUCTOR SUBSTRATE IN AN IMMERSION LITHOGRAPHY SYSTEM - A method and apparatus for reduction and prevention of residue formation and removal of residues formed in an immersion lithography tool. The apparatus including incorporation of a cleaning mechanism within the immersion head of an immersion lithographic system or including a cleaning mechanism in a cleaning station of an immersion lithographic system. | 04-02-2009 |
20090121298 | FIELD EFFECT TRANSISTOR - A transistor. The transistor including: a well region in a substrate; a gate dielectric layer on a top surface of the well region; a polysilicon gate electrode on a top surface of the gate dielectric layer; spacers formed on opposite sidewalls of the polysilicon gate electrode; source/drain regions formed on opposite sides of the polysilicon gate electrode in the well region; a first doped region in the polysilicon gate electrode, the first doped region extending into the polysilicon gate electrode from a top surface of the polysilicon gate electrode; and a buried second doped region in the polysilicon gate electrode. | 05-14-2009 |
20090121343 | CARBON NANOTUBE STRUCTURES FOR ENHANCEMENT OF THERMAL DISSIPATION FROM SEMICONDUCTOR MODULES - Disclosed are embodiments of an improved semiconductor wafer structure having protected clusters of carbon nanotubes (CNTs) on the back surface and a method of forming the improved semiconductor wafer structure. Also disclosed are embodiments of a semiconductor module with exposed CNTs on the back surface for providing enhanced thermal dissipation in conjunction with a heat sink and a method of forming the semiconductor module using the disclosed semiconductor wafer structure. | 05-14-2009 |
20090184400 | VIA GOUGING METHODS AND RELATED SEMICONDUCTOR STRUCTURE - Methods for via gouging and a related semiconductor structure are disclosed. In one embodiment, the method includes forming a via opening in a dielectric material, the via opening aligned with a conductor; forming a protective coating over the dielectric material and in the via opening; performing via gouging; and removing the protective coating over horizontal surfaces of the dielectric material. A semiconductor structure may include a via having an interface with a conductor, the interface including a three-dimensionally shaped region extending into and past a surface of the conductor, wherein an outer edge of the three-dimensionally shaped region is distanced from an outermost surface of the via. | 07-23-2009 |
20090246958 | METHOD FOR REMOVING RESIDUES FROM A PATTERNED SUBSTRATE - The present invention relates to a method for removing residues from open areas of a patterned substrate involving the steps of providing a layer of a developable anti-reflective coating (DBARC) over a substrate; providing a layer of a photoresist over said DBARC layer; pattern-wise exposing said photoresist layer and said DBARC layer to a radiation; developing said photoresist layer and said DBARC layer with a first developer to form patterned structures in said photoresist and DBARC layers; depositing a layer of a developer soluble material over said patterned structures; and removing said developer soluble material with a second developer. | 10-01-2009 |
20090321833 | VERTICAL PROFILE FinFET GATE FORMED VIA PLATING UPON A THIN GATE DIELECTRIC - Methods of making vertical profile FinFET gate electrodes via plating upon a thin gate dielectric are disclosed. In one embodiment, a method for forming a transistor, comprises: providing a semiconductor topography comprising a semiconductor substrate and a semiconductor fin structure extending above the substrate; forming a gate dielectric across exposed surfaces of the semiconductor topography; patterning a mask upon the semiconductor topography such that only a select portion of the gate dielectric is exposed that defines where a gate electrode is to be formed; and plating a metallic material upon the select portion of the gate dielectric to form a gate electrode across a portion of the fin structure. | 12-31-2009 |
20100009131 | MULTI-EXPOSURE LITHOGRAPHY EMPLOYING A SINGLE ANTI-REFLECTIVE COATING LAYER - A first photoresist is applied over an optically dense layer and lithographically patterned to form an array of first photoresist portions having a pitch near twice a minimum feature size. The pattern in the first photoresist portions, or a first pattern, is transferred into the ARC layer and partly into the optically dense layer. A second photoresist is applied and patterned into another array having a pitch near twice the minimum feature size and interlaced with the first pattern. The pattern in the second photoresist, or a second pattern, is transferred through the ARC portions and partly into the optically dense layer. The ARC portions are patterned with a composite pattern including the first pattern and the second pattern. The composite pattern is transferred through the optically dense layer and into the underlayer to form a sublithographic pattern in the underlayer. | 01-14-2010 |
20100028801 | LITHOGRAPHY FOR PITCH REDUCTION - In one embodiment, a photoresist is lithographically patterned to form an array of patterned photoresist portions having a pitch near twice a minimum feature size. Fluorine-containing polymer spacers are formed on sidewalls of the patterned photoresist portions. The pattern of the fluorine-containing polymer spacers is transferred into an underlying layer to form a pattern having a sublithographic pitch. In another embodiment, a first pattern in a first photoresist is transferred into a first ARC layer underneath to form first ARC portions. A planarizing second optically dense layer, a second ARC layer, and a second photoresist are applied over the first ARC portions. A second pattern in the second photoresist is transferred into the second ARC layer to form second ARC portions. The combination of the first ARC portions and second ARC portions function as an etch mask to pattern an underlying layer with a composite pattern having a sublithographic pitch. | 02-04-2010 |
20100119422 | CHEMICAL AND PARTICULATE FILTERS CONTAINING CHEMICALLY MODIFIED CARBON NANOTUBE STRUCTURES - A carbon nanotube filter. The filter including a filter housing; and chemically active carbon nanotubes within the filter housing, the chemically active carbon nanotubes comprising a chemically active layer formed on carbon nanotubes or comprising chemically reactive groups on sidewalls of the carbon nanotubes; and media containing the chemically active carbon nanotubes. | 05-13-2010 |
20110027951 | SHARED GATE FOR CONVENTIONAL PLANAR DEVICE AND HORIZONTAL CNT - A semiconductor structure in which a planar semiconductor device and a horizontal carbon nanotube transistor have a shared gate and a method of fabricating the same are provided in the present application. The hybrid semiconductor structure includes at least one horizontal carbon nanotube transistor and at least one planar semiconductor device, in which the at least one horizontal carbon nanotube transistor and the at least one planar semiconductor device have a shared gate and the at least one horizontal carbon nanotube transistor is located above a gate of the at least one planar semiconductor device. | 02-03-2011 |
20110034000 | SELECTIVE DEPOSITION OF GERMANIUM SPACERS ON NITRIDE - A method of selectively forming a germanium structure within semiconductor manufacturing processes removes the native oxide from a nitride surface in a chemical oxide removal (COR) process and then exposes the heated nitride and oxide surface to a heated germanium containing gas to selectively form germanium only on the nitride surface but not the oxide surface. | 02-10-2011 |
20110147984 | METHODS OF DIRECTED SELF-ASSEMBLY, AND LAYERED STRUCTURES FORMED THEREFROM - A method of forming a layered structure comprising a self-assembled material comprises: disposing a non-crosslinking photoresist layer on a substrate; pattern-wise exposing the photoresist layer to first radiation; optionally heating the exposed photoresist layer; developing the exposed photoresist layer in a first development process with an aqueous alkaline developer, forming an initial patterned photoresist layer; treating the initial patterned photoresist layer photochemically, thermally and/or chemically, thereby forming a treated patterned photoresist layer comprising non-crosslinked treated photoresist disposed on a first substrate surface; casting a solution of an orientation control material in a first solvent on the treated patterned photoresist layer, and removing the first solvent, forming an orientation control layer; heating the orientation control layer to effectively bind a portion of the orientation control material to a second substrate surface; removing at least a portion of the treated photoresist and, optionally, any non-bound orientation control material in a second development process, thereby forming a pre-pattern for self-assembly; optionally heating the pre-pattern; casting a solution of a material capable of self-assembly dissolved in a second solvent on the pre-pattern and removing the second solvent; and allowing the casted material to self-assemble with optional heating and/or annealing, thereby forming the layered structure comprising the self-assembled material. | 06-23-2011 |
20110204523 | METHOD OF FABRICATING DUAL DAMASCENE STRUCTURES USING A MULTILEVEL MULTIPLE EXPOSURE PATTERNING SCHEME - A method for fabricating a dual damascene structure includes providing a first photoresist layer coated on an underlying dielectric stack, exposing said first photoresist layer to a first predetermined pattern of light, coating a second photoresist layer onto the pre-exposed first photoresist layer, exposing said second photoresist layer to a second predetermined pattern of light, optionally post-exposure baking the multi-tiered photoresist layers and developing said photoresist layers to form a multi-tiered dual damascene structure in the photoresist layers. | 08-25-2011 |
20110266621 | FIELD EFFECT TRANSISTOR - A transistor. The transistor including: a well region in a substrate; a gate dielectric layer on a top surface of the well region; a polysilicon gate electrode on a top surface of the gate dielectric layer; spacers formed on opposite sidewalls of the polysilicon gate electrode; source/drain regions formed on opposite sides of the polysilicon gate electrode in the well region; a first doped region in the polysilicon gate electrode, the first doped region extending into the polysilicon gate electrode from a top surface of the polysilicon gate electrode; and a buried second doped region in the polysilicon gate electrode. | 11-03-2011 |
20120018813 | BARRIER COAT FOR ELIMINATION OF RESIST RESIDUES ON HIGH k/METAL GATE STACKS - A technique for substantially eliminating resist residues from a gate stack that includes, from bottom to top, a high k gate dielectric and a metal gate, e.g., a high k/metal gate stack, is provided. In particular and in one embodiment, a method is disclosed in which a patterned resist and optionally a patterned barrier coating are formed atop a surface of the metal gate electrode of a high k/metal gate stack prior to patterning the metal gate electrode. At least the metal gate electrode not protected by the patterned material is then etched. The presence of the barrier coating eliminates resist residues from the resultant gate stack. The technique provided can be used in fabricating planar semiconductor devices such as, for example, metal oxide semiconductor field effect transistors (MOSFETS) including complementary metal oxide semiconductor (CMOS) field effect transistors, as well as non-planar semiconductor devices such as, for example, finFETs. | 01-26-2012 |
20120126358 | TONE INVERSION WITH PARTIAL UNDERLAYER ETCH - A method for tone inversion for integrated circuit fabrication includes providing a substrate with an underlayer on top of the substrate; creating a first pattern, the first pattern being partially etched into a portion of the underlayer such that a remaining portion of the underlayer is protected and forms a second pattern, and such that the first pattern does not expose the substrate located underneath the underlayer; covering the first pattern with a layer of image reverse material (IRM); and etching the second pattern into the substrate. A structure for tone inversion for integrated circuit fabrication includes a substrate; a partially etched underlayer comprising a first pattern located over the substrate, the first pattern being partially etched into a portion of the underlayer such that a remaining portion of the underlayer is protected and forms a second pattern, and such that the first pattern does not expose the substrate located underneath the underlayer; and an image reversal material (IRM) layer located over the partially etched underlayer. | 05-24-2012 |
20120142182 | MICROELECTRONIC STRUCTURE BY SELECTIVE DEPOSITION - A finFET structure includes a semiconductor fin located over a substrate. A gate electrode is located traversing the semiconductor fin. The gate electrode has a spacer layer located adjoining a sidewall thereof. The spacer layer does not cover completely a sidewall of the semiconductor fin. The gate electrode and the spacer layer may be formed using a vapor deposition method that provides for selective deposition upon a sidewall of a mandrel layer but not upon an adjoining surface of the substrate, so that the spacer layer does not cover completely the sidewall of the semiconductor fin. Other microelectronic structures may be fabricated using the lateral growth methodology. | 06-07-2012 |
20120168931 | CARBON NANOTUBE STRUCTURES FOR ENHANCEMENT OF THERMAL DISSIPATION FROM SEMICONDUCTOR MODULES - Disclosed are embodiments of an improved semiconductor wafer structure having protected clusters of carbon nanotubes (CNTs) on the back surface and a method of forming the improved semiconductor wafer structure. Also disclosed are embodiments of a semiconductor module with exposed CNTs on the back surface for providing enhanced thermal dissipation in conjunction with a heat sink and a method of forming the semiconductor module using the disclosed semiconductor wafer structure. | 07-05-2012 |
20120181613 | Methods for Forming Field Effect Transistor Devices With Protective Spacers - A method for forming a field effect transistor device includes forming a first gate stack and a second gate stack on a substrate, depositing a first photoresist material over the second gate stack and a portion of the substrate, implanting ions in exposed regions of the substrate to define a first source region and a first drain region adjacent to the first gate stack, depositing a first protective layer over the first source region, the first gate stack, the first drain region, and the first photoresist material, removing portions of the first protective layer to expose the first photoresist material and to define a first spacer disposed on a portion of the first source region and a portion of the first drain region, removing the first photoresist material, and removing the first spacer. | 07-19-2012 |
20120241913 | MICROELECTRONIC SUBSTRATE HAVING REMOVABLE EDGE EXTENSION ELEMENT - An article including a microelectronic substrate is provided as an article usable during the processing of the microelectronic substrate. Such article includes a microelectronic substrate having a front surface, a rear surface opposite the front surface and a peripheral edge at boundaries of the front and rear surfaces. The front surface is a major surface of the article. A removable annular edge extension element having a front surface, a rear surface and an inner edge extending between the front and rear surfaces has the inner edge joined to the peripheral edge of the microelectronic substrate. In such way, a continuous surface is formed which includes the front surface of the edge extension element extending laterally from the peripheral edge of the microelectronic substrate and the front surface of the microelectronic substrate, the continuous surface being substantially co-planar and flat where the peripheral edge is joined to the inner edge. | 09-27-2012 |
20130026639 | Method of fabricating dual damascene structures using a multilevel multiple exposure patterning scheme - A method for fabricating a dual damascene structure includes providing a first photoresist layer coated on an underlying dielectric stack, exposing said first photoresist layer to a first predetermined pattern of light, coating a second photoresist layer onto the pre-exposed first photoresist layer, exposing said second photoresist layer to a second predetermined pattern of light, optionally post-exposure baking the multi-tiered photoresist layers and developing said photoresist layers to form a multi-tiered dual damascene structure in the photoresist layers. | 01-31-2013 |
20130040238 | DEVELOPABLE BOTTOM ANTIREFLECTIVE COATING COMPOSITIONS FOR NEGATIVE RESISTS - A negative developable bottom antireflective coating (NDBARC) material includes a polymer containing an aliphatic alcohol moiety, an aromatic moiety, and a carboxylic acid moiety. The NDBARC composition is insoluble in a typical resist solvent such as propylene glycol methyl ether acetate (PGMEA) after coating and baking. The NDBARC material also includes a photoacid generator, and optionally a crosslinking compound. In the NDBARC material, the carboxylic acid provides the developer solubility, while the alcohol alone, the carboxylic acid alone, or their combination provides the PGMEA resistance. The NDBARC material has resistance to the resist solvent, and thus, intermixing does not occur between NDBARC and resist during resist coating over NDBARC. After exposure and bake, the lithographically exposed portions of both the negative photoresist and the NDBARC layer become insoluble in developer due to the chemically amplified crosslinking of the polymers in negative resist and NDBARC layer in the lithographically exposed portions. | 02-14-2013 |
20130115767 | Metal Alloy Cap Integration - A metal interconnect structure, which includes metal alloy capping layers, and a method of manufacturing the same. The originally deposited alloy capping layer element within the interconnect features will diffuse into and segregate onto top surface of the metal interconnect. The metal alloy capping material is deposited on a reflowed copper surface and is not physically in contact with sidewalls of the interconnect features. The metal alloy capping layer is also reflowed on the copper. Thus, there is a reduction in electrical resistivity impact from residual alloy elements in the interconnect structure. That is, there is a reduction, of alloy elements inside the features of the metal interconnect structure. The metal interconnect structure includes a dielectric layer with a recessed line, a liner material on sidewalls, a copper material, an alloy capping layer, and a dielectric cap. | 05-09-2013 |
20130122421 | HYBRID PHOTORESIST COMPOSITION AND PATTERN FORMING METHOD USING THEREOF - The present invention relates to a hybrid photoresist composition for improved resolution and a pattern forming method using the photoresist composition. The photoresist composition includes a radiation sensitive acid generator, a crosslinking agent and a polymer having a hydrophobic monomer unit and a hydrophilic monomer unit containing a hydroxyl group. At least some of the hydroxyl groups are protected with an acid labile moiety having a low activation energy. The photoresist is capable of producing a hybrid response to a single exposure. The patterning forming method utilizes the hybrid response to form a patterned structure in the photoresist layer. The photoresist composition and the pattern forming method of the present invention are useful for printing small features with precise image control, particularly spaces of small dimensions. | 05-16-2013 |
20130168775 | METHODS FOR FORMING FIELD EFFECT TRANSISTOR DEVICES WITH PROTECTIVE SPACERS - A field effect transistor device prepared by a process including forming a first gate stack and a second gate stack on a substrate and depositing a first photoresist material over the second gate stack and a portion of the substrate. The process also includes implanting ions in exposed regions of the substrate to define a first source region and a first drain region adjacent to the first gate stack and depositing a first protective layer over the first source region, the first gate stack, the first drain region, and the first photoresist material. The process further includes removing portions of the first protective layer to expose the first photoresist material and to define a first spacer disposed on a portion of the first source region and a portion of the first drain region and removing the first photoresist material. | 07-04-2013 |
20130175658 | TONE INVERSION WITH PARTIAL UNDERLAYER ETCH FOR SEMICONDUCTOR DEVICE FORMATION - A structure for tone inversion for integrated circuit fabrication includes a substrate; a partially etched underlayer comprising a first pattern located over the substrate, the first pattern being partially etched into a portion of the underlayer such that a remaining portion of the underlayer is protected and forms a second pattern, and such that the first pattern does not expose the substrate located underneath the underlayer; and an image reversal material (IRM) layer located over the partially etched underlayer. | 07-11-2013 |
20130207270 | DUAL-METAL SELF-ALIGNED WIRES AND VIAS - Method of forming a semiconductor structure which includes forming first conductive spacers on a semiconductor substrate; forming second conductive spacers with respect to the first conductive spacers, at least one of the second conductive spacers adjacent to and in contact with each of the first conductive spacers to form combined conductive spacers; recessing the second conductive spacers with respect to the first conductive spacers so that the first conductive spacers extend beyond the second conductive spacers; depositing an ILD to cover the first and second spacers except for an exposed edge of the first conductive spacers; patterning the exposed edges of the first conductive spacers to recess the edges of the first conductive spacers in predetermined locations to form recesses with respect to the ILD; and filling the recesses with an insulating material to leave unrecessed edges of the first conductive spacers as vias to subsequent wiring features. | 08-15-2013 |
20130216776 | DUAL HARD MASK LITHOGRAPHY PROCESS - A first metallic hard mask layer over an interconnect-level dielectric layer is patterned with a line pattern. At least one dielectric material layer, a second metallic hard mask layer, a first organic planarization layer (OPL), and a first photoresist are applied above the first metallic hard mask layer. A first via pattern is transferred from the first photoresist layer into the second metallic hard mask layer. A second OPL and a second photoresist are applied and patterned with a second via pattern, which is transferred into the second metallic hard mask layer. A first composite pattern of the first and second via patterns is transferred into the at least one dielectric material layer. A second composite pattern that limits the first composite pattern with the areas of the openings in the first metallic hard mask layer is transferred into the interconnect-level dielectric layer. | 08-22-2013 |
20130252419 | Metal Alloy Cap Integration - A metal interconnect structure, which includes metal alloy capping layers, and a method of manufacturing the same. The originally deposited alloy capping layer element within the interconnect features will diffuse into and segregate onto top surface of the metal interconnect. The metal alloy capping material is deposited on a reflowed copper surface and is not physically in contact with sidewalls of the interconnect features. The metal alloy capping layer is also reflowed on the copper. Thus, there is a reduction in electrical resistivity impact from residual alloy elements in the interconnect structure. That is, there is a reduction, of alloy elements inside the features of the metal interconnect structure. The metal interconnect structure includes a dielectric layer with a recessed line, a liner material on sidewalls, a copper material, an alloy capping layer, and a dielectric cap. | 09-26-2013 |
20130313643 | Structure and Method to Modulate Threshold Voltage For High-K Metal Gate Field Effect Transistors (FETs) - A method for forming an electrical device that includes forming a high-k gate dielectric layer over a semiconductor substrate that is patterned to separate a first portion of the high-k gate dielectric layer that is present on a first conductivity device region from a second portion of the high-k gate dielectric layer that is present on a second conductivity device region. A connecting gate conductor is formed on the first portion and the second portion of the high-k gate dielectric layer. The connecting gate conductor extends from the first conductivity device region over the isolation region to the second conductivity device region. One of the first conductivity device region and the second conductivity device region may then be exposed to an oxygen containing atmosphere. Exposure with the oxygen containing atmosphere modifies a threshold voltage of the semiconductor device that is exposed. | 11-28-2013 |
20130313717 | SPACER FOR ENHANCING VIA PATTERN OVERLAY TOLERENCE - After formation of line openings in a hard mask layer, hard mask level spacers are formed on sidewalls of the hard mask layer. A photoresist is applied and patterned to form a via pattern including a via opening. The overlay tolerance for printing the via pattern is increased by the lateral thickness of the hard mask level spacers. A portion of a dielectric material layer is patterned to form a via cavity pattern by an etch that employs the hard mask layer and the hard mask level spacers as etch masks. The hard mask level spacers are subsequently removed, and the pattern of the line is subsequently transferred into an upper portion of the dielectric material layer, while the via cavity pattern is transferred to a lower portion of the dielectric material layer. | 11-28-2013 |
20130316503 | STRUCTURE AND METHOD TO MODULATE THRESHOLD VOLTAGE FOR HIGH-K METAL GATE FIELD EFFECT TRANSISTORS (FETs) - A method for forming an electrical device that includes forming a high-k gate dielectric layer over a semiconductor substrate that is patterned to separate a first portion of the high-k gate dielectric layer that is present on a first conductivity device region from a second portion of the high-k gate dielectric layer that is present on a second conductivity device region. A connecting gate conductor is formed on the first portion and the second portion of the high-k gate dielectric layer. The connecting gate conductor extends from the first conductivity device region over the isolation region to the second conductivity device region. One of the first conductivity device region and the second conductivity device region may then be exposed to an oxygen containing atmosphere. Exposure with the oxygen containing atmosphere modifies a threshold voltage of the semiconductor device that is exposed. | 11-28-2013 |
20130328208 | DUAL DAMASCENE DUAL ALIGNMENT INTERCONNECT SCHEME - A stack of a first metal line and a first dielectric cap material portion is formed within a line trench of first dielectric material layer. A second dielectric material layer is formed thereafter. A line trench extending between the top surface and the bottom surface of the second dielectric material layer is patterned. A photoresist layer is applied over the second dielectric material layer and patterned with a via pattern. An underlying portion of the first dielectric cap material is removed by an etch selective to the dielectric materials of the first and second dielectric material layer to form a via cavity that is laterally confined along the widthwise direction of the line trench and along the widthwise direction of the first metal line. A dual damascene line and via structure is formed, which includes a via structure that is laterally confined along two independent horizontal directions. | 12-12-2013 |
20140004712 | DEVELOPABLE BOTTOM ANTIREFLECTIVE COATING COMPOSITION AND PATTERN FORMING METHOD USING THEREOF | 01-02-2014 |
20140024191 | METHOD OF MULTIPLE PATTERNING TO FORM SEMICONDUCTOR DEVICES - A method of forming different structures of a semiconductor device using a single mask and a hybrid photoresist. The method includes: applying a first photoresist layer on a semiconductor substrate; patterning the first photoresist layer using a photomask to form a first patterned photoresist layer; using the first patterned photoresist layer to form a first structure of a semiconductor device; removing the first patterned photoresist layer; applying a second photoresist layer on the semiconductor substrate; patterning the second photoresist layer using the photomask to form a second patterned photoresist layer; using the second patterned photoresist layer to form a second structure of a semiconductor device; removing the second patterned photoresist layer; and wherein either the first or the second photoresist layer is a hybrid photoresist layer comprising a hybrid photoresist. | 01-23-2014 |
20140035142 | PROFILE CONTROL IN INTERCONNECT STRUCTURES - The profile of a via can be controlled by forming a profile control liner within each via opening that is formed into a dielectric material prior to forming a line opening within the dielectric material. The presence of the profile control liner within each via opening during the formation of the line opening prevents rounding of the corners of a dielectric material portion that is present beneath the line opening and adjacent the via opening. | 02-06-2014 |
20140061930 | OVERLAY-TOLERANT VIA MASK AND REACTIVE ION ETCH (RIE) TECHNIQUE - A method is provided that includes first etching a substrate according to a first mask. The first etching forms a first etch feature in the substrate to a first depth. The first etching also forms a sliver opening in the substrate. The sliver opening may then be filled with a fill material. A second mask may be formed by removing a portion of the first mask. The substrate exposed by the second mask may be etched with a second etch, in which the second etching is selective to the fill material. The second etching extends the first etch feature to a second depth that is greater than the first depth, and the second etch forms a second etch feature. The first etch feature and the second etch feature may then be filled with a conductive metal. | 03-06-2014 |
20140099583 | SIMULTANEOUS PHOTORESIST DEVELOPMENT AND NEUTRAL POLYMER LAYER FORMATION - A photoresist layer is lithographically exposed to form lithographically exposed photoresist regions and lithographically unexposed photoresist regions. The photoresist layer is developed with a non-polar or weakly polar solvent including a dissolved neutral polymer material. A neutral polymer layer is selectively formed on physically exposed surfaces of a hard mask layer underlying the photoresist layer. The neutral polymer layer has a pattern corresponding to the complement of the area of remaining portions of the photoresist layer. The remaining portions of the photoresist layer are then removed with a polar solvent without removing the neutral polymer layer on the hard mask layer. A block copolymer material can be subsequently applied over the neutral polymer, and the neutral polymer layer can guide the alignment of a phase-separated block copolymer material in a directed self-assembly. | 04-10-2014 |
20140138863 | METHODS OF FORMING NANOPARTICLES USING SEMICONDUCTOR MANUFACTURING INFRASTRUCTURE - A method of preparing particles comprises forming by optical lithography a topographic template layer disposed on a surface of a substrate, which is suitable for spin casting. The template layer comprises a non-crosslinked template polymer having a pattern of independent wells therein for molding independent particles. Spin casting a particle-forming composition onto the template layer forms a composite layer comprising the template polymer and the particles disposed in the wells. The composite layer is removed from the substrate using a stripping agent that dissolves the template polymer without dissolving the particles. The particles are then isolated. | 05-22-2014 |
20140148012 | TONE INVERSION OF SELF-ASSEMBLED SELF-ALIGNED STRUCTURES - A stack of an organic planarization layer (OPL) and a template layer is provided over a substrate. The template layer is patterned to induce self-assembly of a copolymer layer to be subsequently deposited. A copolymer layer is deposited and annealed to form phase-separated copolymer blocks. An original self-assembly pattern is formed by removal of a second phase separated polymer relative to a first phase separated polymer. The original pattern is transferred into the OPL by an anisotropic etch, and the first phase separated polymer and the template layer are removed. A spin-on dielectric (SOD) material layer is deposited over the patterned OPL that includes the original pattern to form SOD portions that fill trenches within the patterned OPL. The patterned OPL is removed selective to the SOD portions, which include a complementary pattern. The complementary pattern of the SOD portions is transferred into underlying layers by an anisotropic etch. | 05-29-2014 |
20140264490 | REPLACEMENT GATE ELECTRODE WITH A SELF-ALIGNED DIELECTRIC SPACER - A dielectric disposable gate structure can be formed across a semiconductor material portion, and active semiconductor regions are formed within the semiconductor material portion. Raised active semiconductor regions are grown over the active semiconductor regions while the dielectric disposable gate structure limits the extent of the raised active semiconductor regions. A planarization dielectric layer is formed over the raised active semiconductor regions. In one embodiment, the dielectric disposable gate structure is removed, and a dielectric gate spacer can be formed by conversion of surface portions of the raised active semiconductor regions around a gate cavity. Alternately, an etch mask layer overlying peripheral portions of the disposable gate structure can be formed, and a gate cavity and a dielectric spacer can be formed by anisotropically etching an unmasked portion of the dielectric disposable gate structure. A replacement gate structure can be formed in the gate cavity. | 09-18-2014 |
20140353800 | TONE INVERSION OF SELF-ASSEMBLED SELF-ALIGNED STRUCTURES - A stack of an organic planarization layer (OPL) and a template layer is provided over a substrate. The template layer is patterned to induce self-assembly of a copolymer layer to be subsequently deposited. A copolymer layer is deposited and annealed to form phase-separated copolymer blocks. An original self-assembly pattern is formed by removal of a second phase separated polymer relative to a first phase separated polymer. The original pattern is transferred into the OPL by an anisotropic etch, and the first phase separated polymer and the template layer are removed. A spin-on dielectric (SOD) material layer is deposited over the patterned OPL that includes the original pattern to form SOD portions that fill trenches within the patterned OPL. The patterned OPL is removed selective to the SOD portions, which include a complementary pattern. The complementary pattern of the SOD portions is transferred into underlying layers by an anisotropic etch. | 12-04-2014 |
20140363941 | REPLACEMENT GATE ELECTRODE WITH A SELF-ALIGNED DIELECTRIC SPACER - A dielectric disposable gate structure can be formed across a semiconductor material portion, and active semiconductor regions are formed within the semiconductor material portion. Raised active semiconductor regions are grown over the active semiconductor regions while the dielectric disposable gate structure limits the extent of the raised active semiconductor regions. A planarization dielectric layer is formed over the raised active semiconductor regions. In one embodiment, the dielectric disposable gate structure is removed, and a dielectric gate spacer can be formed by conversion of surface portions of the raised active semiconductor regions around a gate cavity. Alternately, an etch mask layer overlying peripheral portions of the disposable gate structure can be formed, and a gate cavity and a dielectric spacer can be formed by anisotropically etching an unmasked portion of the dielectric disposable gate structure. A replacement gate structure can be formed in the gate cavity. | 12-11-2014 |
20150035157 | SPACER FOR ENHANCING VIA PATTERN OVERLAY TOLERENCE - After formation of line openings in a hard mask layer, hard mask level spacers are formed on sidewalls of the hard mask layer. A photoresist is applied and patterned to form a via pattern including a via opening. The overlay tolerance for printing the via pattern is increased by the lateral thickness of the hard mask level spacers. A portion of a dielectric material layer is patterned to form a via cavity pattern by an etch that employs the hard mask layer and the hard mask level spacers as etch masks. The hard mask level spacers are subsequently removed , and the pattern of the line is subsequently transferred into an upper portion of the dielectric material layer, while the via cavity pattern is transferred to a lower portion of the dielectric material layer. | 02-05-2015 |