Patent application number | Description | Published |
20080244230 | SCALABLE PROCESSING ARCHITECTURE - A computation node according to various embodiments of the invention includes at least one input port capable of being coupled to at least one first other | 10-02-2008 |
20090013135 | UNORDERED LOAD/STORE QUEUE - A method and processor for providing full load/store queue functionality to an unordered load/store queue for a processor with out-of-order execution. Load and store instructions are inserted in a load/store queue in execution order. Each entry in the load/store queue includes an identification corresponding to a program order. Conflict detection in such an unordered load/store queue may be performed by searching a first CAM for all addresses that are the same or overlap with the address of the load or store instruction to be executed. A further search may be performed in a second CAM to identify those entries that are associated with younger or older instructions with respect to the sequence number of the load or store instruction to be executed. The output results of the Address CAM and Age CAM are logically ANDed. | 01-08-2009 |
20090013160 | DYNAMICALLY COMPOSING PROCESSOR CORES TO FORM LOGICAL PROCESSORS - A method, system and computer program product for dynamically composing processor cores to form logical processors. Processor cores are composable in that the processor cores are dynamically allocated to form a logical processor to handle a change in the operating status. Once a change in the operating status is detected, a mechanism may be triggered to recompose one or more processor cores into a logical processor to handle the change in the operating status. An analysis may be performed as to how one or more processor cores should be recomposed to handle the change in the operating status. After the analysis, the one or more processor cores are recomposed into the logical processor to handle the change in the operating status. By dynamically allocating the processor cores to handle the change in the operating status, performance and power efficiency is improved. | 01-08-2009 |
20100146209 | METHOD AND APPARATUS FOR COMBINING INDEPENDENT DATA CACHES - Methods, apparatus, computer programs and systems related to combining independent data caches are described. Various implementations can dynamically aggregate multiple level-one (L1) data caches from distinct processors together, change the degree of interleaving (e.g., how much consecutive data is mapped to each participating data cache before addresses go on to the next one) among the cache banks, and retain the ability to subsequently adjust the number of data caches participating as one coherent cache, i.e., the degree of interleaving, such as when the requirements of an application or process change. | 06-10-2010 |
20100146249 | Control-Flow Prediction Using Multiple Independent Predictors - The present disclosure generally describes computing systems with a multi-core processor comprising one or more branch predictor arrangements. The branch predictor are configured to predict a single and complete flow of program instructions associated therewith and to be performed on at least one processor core of the computing system. Overall processor performance and physical scalability may be improved by the described methods. | 06-10-2010 |
20100211718 | METHOD AND APPARATUS FOR CONGESTION-AWARE ROUTING IN A COMPUTER INTERCONNECTION NETWORK - The present disclosure relates to an example of a method for a first router to adaptively determine status within a network. The network may include the first router, a second router and a third router. The method for the first router may comprise determining status information regarding the second router located in the network, and transmitting the status information to the third router located in the network. The second router and the third router may be indirectly coupled to one another. | 08-19-2010 |
20100325308 | SCALABLE BUS-BASED ON-CHIP INTERCONNECTION NETWORKS - The present disclosure generally relates to systems for routing data across a multinodal network. Example systems include a multinodal array having a plurality of nodes and a plurality of physical communication channels connecting the nodes. At least one of the physical communication channels may be configured to route data from a first node to two or more other destination nodes of the plurality of nodes. The present disclosure also generally relates to methods for routing data across a multinodal network and computer accessible mediums having stored thereon computer executable instructions for performing techniques for routing data across a multinodal network. | 12-23-2010 |
20100325395 | DEPENDENCE PREDICTION IN A MEMORY SYSTEM - Techniques related to dependence prediction for a memory system are generally described. Various implementations may include a predictor storage storing a value corresponding to at least one prediction type associated with at least one load operation, and a state-machine having multiple states. For example, the state-machine may determine whether to execute the load operation based upon a prediction type associated with each of the states and a corresponding precedent to the load operation for the associated prediction type. The state-machine may further determine the prediction type for a subsequent load operation based on a result of the load operation. The states of the state machine may correspond to prediction types, which may be a conservative prediction type, an aggressive prediction type, or one or more N-store prediction types, for example. | 12-23-2010 |
20110072239 | DATA MULTICASTING IN A DISTRIBUTED PROCESSOR SYSTEM - Methods, procedures, apparatuses, computer programs, computer-accessible mediums, processing arrangements and systems generally related to data multi-casting in a distributed processor architecture are described. Various implementations may include identifying a plurality of target instructions that are configured to receive a first message from a source; providing target routing instructions to the first message for each of the target instructions including selected information commonly shared by the target instructions; and, when two of the identified target instructions are located in different directions from one another relative to a router, replicating the first message and routing the replicated messages to each of the identified target instructions in the different directions. The providing target routing instructions may further comprise the selected information utilizing a subset of bits that is commonly shared by the target instructions and being identified as a left operand, right operand or predicate operand, and may include the selection of one of a plurality of multiple-instruction subsets of the target instructions. | 03-24-2011 |
20130086370 | COMBINED BRANCH TARGET AND PREDICATE PREDICTION - Embodiments provide methods, apparatus, systems, and computer readable media associated with predicting predicates and branch targets during execution of programs using combined branch target and predicate predictions. The predictions may be made using one or more prediction control flow graphs which represent predicates in instruction blocks and branches between blocks in a program. The prediction control flow graphs may be structured as trees such that each node in the graphs is associated with a predicate instruction, and each leaf associated with a branch target which jumps to another block. During execution of a block, a prediction generator may take a control point history and generate a prediction. Following the path suggested by the prediction through the tree, both predicate values and branch targets may be predicted. Other embodiments may be described and claimed. | 04-04-2013 |