Patent application number | Description | Published |
20110191434 | OBTAINING CONSENT FOR ELECTRONIC DELIVERY OF COMPLIANCE INFORMATION - A method and related system obtains consent from an individual for computer-aided delivery of compliance information. Initially, a computer-readable data storage device is provided to the individual. The device stores the compliance information and computer-executable instructions. By inserting the device into a computer, the instructions are executed and the individual is prompted by the computer to consent to the computer-aided delivery of additional compliance information. Once consent is indicated, it is communicated from the individual's computer to another computer such as a server over, for example, a modem connection. Having secured the individual's consent, the additional compliance information can be delivered to the individual's computer as, for example, a file attachment to an email message. | 08-04-2011 |
20110191435 | METHOD AND SYSTEM FOR ELECTRONIC DELIVERY OF SENSITIVE INFORMATION - A method and related system obtains consent from a user for electronic delivery of sensitive information. The user operating a first computer accesses a web page on a server system to input the consent. The web page prompts for the consent from the user. Once the consent is received at the server system, the consent is stored and sensitive information is delivered electronically to an e-mail address specified by the user. Once consent is indicated, it is communicated from the individual's computer to another computer such as a server over, for example, a modem connection. Having secured the individual's consent, the additional sensitive information may be delivered to the individual's computer as, for example, a URL attachment to an email message. | 08-04-2011 |
20140046860 | OBTAINING CONSENT FOR ELECTRONIC DELIVERY OF COMPLIANCE INFORMATION - A method and related system obtains consent from an individual for computer-aided deliver of compliance information. Initially, a computer-readable data storage device is provided to the individual. The device stores the compliance information and computer-executable instructions. By inserting the device into a computer, the instructions are executed and the individual is prompted by the computer to consent to the computer-aided delivery of additional compliance information. Once consent is indicated, it is communicated from the individual's computer to another computer such as a server over, for example, a modem connection. Having secured the individual s consent, the additional compliance information can be delivered to the individual's computer as, for example, a file attachment to an email message. | 02-13-2014 |
20140101276 | METHOD AND SYSTEM FOR ELECTRONIC DELIVERY OF SENSITIVE INFORMATION - A method and related system obtains consent from a user for electronic delivery of sensitive information. The user operating a first computer accesses a web page on a server system to input the consent. The web page prompts for the consent from the user. Once the consent is received at the server system, the consent is stored and sensitive information is delivered electronically to an e-mail address specified by the user. Once consent is indicated, it is communicated from the individual's computer to another computer such as a server over, for example, a modem connection. Having secured the individual's consent, the additional sensitive information may be delivered to the individual's computer as, for example, a URL attachment to an email message. | 04-10-2014 |
Patent application number | Description | Published |
20120323165 | MULTIPLE TISSUE LAYER ELECTROPORATION APPLICATOR AND DEVICE - The present invention relates to dual depth electroporation devices capable of electorporating both muscle tissue and skin tissue in a single application in order to generate a broad immune response in a subject, and uses of the same. | 12-20-2012 |
20130041310 | Oral Mucosal Electroporation Device and Use Thereof - The present invention relates to electroporation (EP) devices that are able to generate an electroporation causing electrical field at the mucosal layer, and preferably in a tolerable manner. Further, it includes the generation of a protective immune response, cellular and/or humoral, using the oral EP device along with a genetic construct that encodes an immunogenic sequence. | 02-14-2013 |
20130066296 | TOLERABLE AND MINIMALLY INVASIVE SKIN ELECTROPORATION DEVICE - A novel electroporation device for the delivery of vaccines that is both effective in generating a protective immune response and tolerable delivery to a subject (or near painless); and also methods of using same device to vaccinate a subject against a variety of infectious diseases and types of cancer in a near painless. | 03-14-2013 |
20140222105 | MINIMINALLY INVASIVE DERMAL ELECTROPORATION DEVICE - The disclosure is directed to a device for electroporating and delivering one or more antigens and a method of electroporating and delivering one or more antigens to cells of epidermal tissues using the device. The device comprises a housing, a plurality of electrode arrays projecting from the housing, each electrode array including at least one electrode, a pulse generator electrically coupled to the electrodes, a programmable microcontroller electrically coupled to the pulse generator, and an electrical power source coupled to the pulse generator and the microcontroller. The electrode arrays define spatially separate sites. | 08-07-2014 |
Patent application number | Description | Published |
20080203445 | Three-Dimensional Cascaded Power Distribution in a Semiconductor Device - An IC structure having reduced power loss and/or noise includes two or more active semiconductor regions stacked in a substantially vertical dimension, each active semiconductor region including an active layer. The IC structure further includes two or more voltage supply planes, each of the voltage supply planes corresponding to a respective one of the active layers. | 08-28-2008 |
20080225573 | STATIC RANDOM ACCESS MEMORY CELL WITH IMPROVED STABILITY - A memory cell comprises a wordline, a first digital inverter with a first input and a first output, and a second digital inverter with a second input and a second output. Moreover, the memory cell further comprises a first feedback connection connecting the first output to the second input, and a second feedback connection connecting the second output to the first input. The first feedback connection comprises a first resistive element and the second feedback connection comprises a second resistive element. What is more, each digital inverter has an associated capacitance. The memory cell is configured such that reading the memory cell includes applying a read voltage pulse to the wordline. In addition, the first and second resistive elements are configured such that the first and second feedback connections have resistance-capacitance induced delays longer than the applied read voltage pulse. | 09-18-2008 |
20100041227 | METHODS FOR INCORPORATING HIGH DIELECTRIC MATERIALS FOR ENHANCED SRAM OPERATION AND STRUCTURES PRODUCED THEREBY - Methods for fabricating a hybrid interconnect structure that possesses a higher interconnect capacitance in one set of regions than in other regions on the same microelectronic chip. Several methods to fabricate such a structure are provided. Circuit implementations of such hybrid interconnect structures are described that enable increased static noise margin and reduce the leakage in SRAM cells and common power supply voltages for SRAM and logic in such a chip. Methods that enable combining these circuit benefits with higher interconnect performance speed and superior mechanical robustness in such chips are also taught. | 02-18-2010 |
20110316569 | Digital Interface for Fast, Inline, Statistical Characterization of Process, MOS Device and Circuit Variations - A Circuit architecture and a method for rapid and accurate statistical characterization of the variations in the electrical characteristics of CMOS process structures, MOS devices and Circuit parameters is provided. The proposed circuit architecture and method enables a statistical characterization throughput of <1 ms/DC sweep at <2 mV or <1 nA resolution accuracy of variations in voltage or current of the device under test. Salient features of proposed circuit architecture include a programmable ramp voltage generator that stimulates the device under test, a dual input 9-11 bit cyclic ADC that captures input and output DC voltage/current signals to/from the device under test, a 2 Kb latch bank that captures 9-11 bit streams for each measurement point in a DC sweep of programmable granularity and a clocking and control scheme that enables continuous measurement and stream out of digital data blocks from which the analog characteristics of the devices under test are reconstructed post measurement. | 12-29-2011 |
Patent application number | Description | Published |
20090198974 | METHODS FOR CONFLICT-FREE, COOPERATIVE EXECUTION OF COMPUTATIONAL PRIMITIVES ON MULTIPLE EXECUTION UNITS - A method for executing multiple computational primitives is provided in accordance with exemplary embodiments. A first computational unit and at least a second computational unit cooperate to execute multiple computational primitives. The first computational unit independently computes other computational primitives. By virtue of arbitration for shared source operand buses or shared result buses, availability of the first and second computational units needed to execute cooperatively the multiple computational primitives is assured by a process of reservation as used for a computational primitive executed on a dedicated computational unit. | 08-06-2009 |
20090251171 | Methods and Apparatus for Monitoring Power Gating Circuitry and for Controlling Circuit Operations in Dependence on Monitored Power Gating Conditions - A circuit incorporating a current starved ring oscillator is coupled to a power gate switch in an integrated circuit. The circuit incorporating the current starved ring oscillator amplifies a voltage difference between a virtual ground associated with the power gate switch and ground, and converts the difference to a frequency. Digital logic monitors the output of the ring oscillator using a counter and a reference clock. Control circuitry controls operation of the integrated circuit in dependence on the monitored conditions associated with the power gate switch. A method monitors a virtual ground voltage across a power gate switch in an integrated circuit; and controls operation of the integrated circuit in dependence on the monitored virtual ground voltage. | 10-08-2009 |
20090251974 | MEMORY CIRCUITS WITH REDUCED LEAKAGE POWER AND DESIGN STRUCTURES FOR SAME - A memory circuit includes a global read bit line, a global read bit line latch, and a plurality of sub-arrays, each of which includes first and second local read bit lines, first and second local write bit lines, and first and second pluralities of memory cells interconnected, respectively, with the first and second local read bit lines and the first and second local write bit lines. The local read bit lines are decoupled from the local write bit lines. A local multiplexing block is interconnected with the first and second local read bit lines and is configured to ground the first and second local read bit lines upon assertion of a SLEEP signal, and to selectively interconnect the local read bit lines to the global read bit line. A global multiplexing block is interconnected with the global read bit line and is configured to maintain the global read bit line in a substantially discharged state upon assertion of the SLEEP signal and to interconnect the global read bit line to the global read bit line latch. Also included are design structures for circuits of the kind described. | 10-08-2009 |
20100072961 | INTERPOSER INCLUDING VOLTAGE REGULATOR AND METHOD THEREFOR - A device that includes an electronic device referred to as an integrated circuit interposer is disclosed. The integrated circuit includes a voltage regulator module. The interposer is attached to an electronic device, such as another integrated circuit, and facilitates control and distribution of power to the electronic device. The integrated circuit interposer can also conduct signaling between the attached electronic device and another electronic device. The voltage regulator module at the integrated circuit interposer can be configured to provide a voltage reference signal to the attached electronic device. Generation of the voltage reference signal by the integrated circuit interposer can be enabled or disabled and the value of the voltage reference signal can be adjusted, depending on operating requirements of the electronic device. | 03-25-2010 |
20110186930 | RING POWER GATING WITH DISTRIBUTED CURRENTS USING NON-LINEAR C4 CONTACT PLACEMENTS - A power gate includes a series of electrical contacts along at least a portion of an integrated circuit and a series of power gate transistors electrically coupled to the electrical contacts on the integrated circuit to form a power gate boundary, e.g., at the integrated circuit periphery. The electrical contacts along at least a portion of a running length of the power gate boundary define a substantially non-linear profile. The non-linear profile provides increased contact density which improves current balancing across the electrical contacts and current throughput through the power gate. The non-linear profile is a sinusoidal or zigzag pattern with intermediate offset bump contacts. The contact profiles along the power gate boundary can include both linear and non-linear profiles. | 08-04-2011 |
20110261064 | 10T SRAM FOR GRAPHICS PROCESSING - A method, apparatus, computer chip, circuit board, computer and system are provided in which data is stored in a low-voltage, maskable memory. Also provided is a computer readable storage device encoded with data for adapting a manufacturing facility to create an apparatus. The method includes storing a data value in a memory cell in a storage device if a first access parameter associated with the memory cell matches a first pre-determined value and if a second access parameter associated with the memory cell matches a second pre-determined value. The method also includes maintaining a data value in the memory cell in the storage device if the first access parameter differs from the first pre-determined value. The apparatus includes a first and second pair of access parameter ports operatively coupled together and associated with a first and second access parameter respectively. The first and second pair of access parameter ports may be adapted to allow access through the first and second pair of access parameter ports if the first access parameter matches a first pre-determined value, and if the second access parameter matches a second pre-determined value. | 10-27-2011 |
20120126847 | POWER SUPPLY MONITOR - Power supply variations and jitter are measured by monitoring the performance of a ring oscillator on a cycle-by-cycle basis. Performance is measured by counting the number of stages of the ring oscillator that are traversed during the clock cycle and mapping the number of stages traversed to a particular voltage level. Counters are used to count the number of ring oscillator revolutions and latches are used to latch the state of the ring oscillator at the end of the cycle. Based on the counters and latches, a monitor output is generated that may also incorporate an adjustment for a reset delay associated with initializing the ring oscillator and counters to a known state. | 05-24-2012 |
20130257525 | CIRCUIT BOARD WITH INTEGRATED VOLTAGE REGULATOR - Various circuit board voltage regulators and methods of making and using the same are disclosed. In one aspect, a method of manufacturing is provided that includes fabricating at least one inductor in a circuit board and coupling a semiconductor chip to the circuit board. The at least one inductor is electrically coupled to the semiconductor chip. Regulator logic is electrically coupled to the at least one inductor, the regulator logic and the at least one inductor are operable to deliver a regulated voltage to the semiconductor chip. | 10-03-2013 |
20140298068 | DISTRIBUTION OF POWER GATING CONTROLS FOR HIERARCHICAL POWER DOMAINS - An integrated circuit device includes a first module disposed within a first power domain, a second module disposed in a second power domain that is a sub-domain of the first power domain, first power gating logic, and second power gating logic. The first power gating logic generates a first virtual power supply for the first module. The second power gating logic is powered by the first virtual power supply for generating a second virtual power supply for the second power domain. | 10-02-2014 |
20140340114 | FAULT DETECTION FOR A DISTRIBUTED SIGNAL LINE - An integrated circuit device includes a first signal line for distributing a first signal. The first signal line includes a plurality of branch lines, and a leaf node is defined at an end of each branch line. First logic is coupled to the leaf nodes and operable to generate a first status signal indicative of a collective first logic state of the leaf nodes of the signal line corresponding to the first signal. | 11-20-2014 |
20150026406 | SIZE ADJUSTING CACHES BY WAY - A size of a cache of a processing system is adjusted by ways, such that each set of the cache has the same number of ways. The cache is a set-associative cache, whereby each set includes a number of ways. In response to defined events at the processing system, a cache controller changes the number of ways of each set of the cache. For example, in response to a processor core indicating that it is entering a period of reduced activity, the cache controller can reduce the number of ways available in each set of the cache. | 01-22-2015 |
20150026407 | SIZE ADJUSTING CACHES BASED ON PROCESSOR POWER MODE - As a processor enters selected low-power modes, a cache is flushed of data by writing data stored at the cache to other levels of a memory hierarchy. The flushing of the cache allows the size of the cache to be reduced without suffering an additional performance penalty of writing the data at the reduced cache locations to the memory hierarchy. Accordingly, when the cache exits the selected low-power modes, it is sized to a minimum size by setting the number of ways of the cache to a minimum number. In response to defined events at the processing system, a cache controller changes the number of ways of each set of the cache. | 01-22-2015 |
20150026531 | POWER SUPPLY MONITOR FOR DETECTING FAULTS DURING SCAN TESTING - Some embodiments of a power supply monitor include a measurement circuit to measure a voltage provided to the power supply monitor, a comparator to compare the voltage to a predetermined voltage threshold, and an interface to provide, during a scan test of a processing device including the power supply monitor, a fault signal in response to the voltage being below the voltage threshold. Some embodiments of a method include providing a first test pattern to one or more power supply monitors associated with one or more circuit blocks in the processing device and capturing a first result generated by the power supply monitor(s) based on the first test pattern. The first result indicates whether a voltage provided to the circuit block(s) is below a voltage threshold. | 01-22-2015 |